197fb5e8dSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
20eb0d9f4SGeorgi Djakov /*
30eb0d9f4SGeorgi Djakov * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
40eb0d9f4SGeorgi Djakov *
50eb0d9f4SGeorgi Djakov * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
60eb0d9f4SGeorgi Djakov */
70eb0d9f4SGeorgi Djakov
80eb0d9f4SGeorgi Djakov #include <linux/module.h>
90eb0d9f4SGeorgi Djakov #include <linux/delay.h>
10415b5a75SGeorgi Djakov #include <linux/mmc/mmc.h>
1167e6db11SPramod Gurav #include <linux/pm_runtime.h>
120472f8d3SRajendra Nayak #include <linux/pm_opp.h>
13415b5a75SGeorgi Djakov #include <linux/slab.h>
14cc392c58SRitesh Harjani #include <linux/iopoll.h>
15ac06fba1SVijay Viswanath #include <linux/regulator/consumer.h>
16b4fc8278SPradeep P V K #include <linux/interconnect.h>
17c62da8a8SRob Herring #include <linux/of.h>
18b5c833b7SVeerabhadrarao Badiganti #include <linux/pinctrl/consumer.h>
193e5a8e84SShaik Sajida Bhanu #include <linux/reset.h>
200eb0d9f4SGeorgi Djakov
21c7eed31eSAbel Vesa #include <soc/qcom/ice.h>
22c7eed31eSAbel Vesa
2308b863bbSBrian Norris #include "sdhci-cqhci.h"
240eb0d9f4SGeorgi Djakov #include "sdhci-pltfm.h"
2587a8df0dSRitesh Harjani #include "cqhci.h"
260eb0d9f4SGeorgi Djakov
273a3ad3e9SGeorgi Djakov #define CORE_MCI_VERSION 0x50
283a3ad3e9SGeorgi Djakov #define CORE_VERSION_MAJOR_SHIFT 28
293a3ad3e9SGeorgi Djakov #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
303a3ad3e9SGeorgi Djakov #define CORE_VERSION_MINOR_MASK 0xff
313a3ad3e9SGeorgi Djakov
3252884f8fSBjorn Andersson #define CORE_MCI_GENERICS 0x70
3352884f8fSBjorn Andersson #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29)
3452884f8fSBjorn Andersson
350eb0d9f4SGeorgi Djakov #define HC_MODE_EN 0x1
360eb0d9f4SGeorgi Djakov #define CORE_POWER 0x0
370eb0d9f4SGeorgi Djakov #define CORE_SW_RST BIT(7)
38ff06ce41SVenkat Gopalakrishnan #define FF_CLK_SW_RST_DIS BIT(13)
390eb0d9f4SGeorgi Djakov
40ad81d387SGeorgi Djakov #define CORE_PWRCTL_BUS_OFF BIT(0)
41ad81d387SGeorgi Djakov #define CORE_PWRCTL_BUS_ON BIT(1)
42ad81d387SGeorgi Djakov #define CORE_PWRCTL_IO_LOW BIT(2)
43ad81d387SGeorgi Djakov #define CORE_PWRCTL_IO_HIGH BIT(3)
44ad81d387SGeorgi Djakov #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
4592a21738SVeerabhadrarao Badiganti #define CORE_PWRCTL_BUS_FAIL BIT(1)
46ad81d387SGeorgi Djakov #define CORE_PWRCTL_IO_SUCCESS BIT(2)
4792a21738SVeerabhadrarao Badiganti #define CORE_PWRCTL_IO_FAIL BIT(3)
48ad81d387SGeorgi Djakov #define REQ_BUS_OFF BIT(0)
49ad81d387SGeorgi Djakov #define REQ_BUS_ON BIT(1)
50ad81d387SGeorgi Djakov #define REQ_IO_LOW BIT(2)
51ad81d387SGeorgi Djakov #define REQ_IO_HIGH BIT(3)
52ad81d387SGeorgi Djakov #define INT_MASK 0xf
53415b5a75SGeorgi Djakov #define MAX_PHASES 16
54415b5a75SGeorgi Djakov #define CORE_DLL_LOCK BIT(7)
5502e4293dSRitesh Harjani #define CORE_DDR_DLL_LOCK BIT(11)
56415b5a75SGeorgi Djakov #define CORE_DLL_EN BIT(16)
57415b5a75SGeorgi Djakov #define CORE_CDR_EN BIT(17)
58415b5a75SGeorgi Djakov #define CORE_CK_OUT_EN BIT(18)
59415b5a75SGeorgi Djakov #define CORE_CDR_EXT_EN BIT(19)
60415b5a75SGeorgi Djakov #define CORE_DLL_PDN BIT(29)
61415b5a75SGeorgi Djakov #define CORE_DLL_RST BIT(30)
62cc392c58SRitesh Harjani #define CORE_CMD_DAT_TRACK_SEL BIT(0)
63415b5a75SGeorgi Djakov
6402e4293dSRitesh Harjani #define CORE_DDR_CAL_EN BIT(0)
6583736352SVenkat Gopalakrishnan #define CORE_FLL_CYCLE_CNT BIT(18)
6683736352SVenkat Gopalakrishnan #define CORE_DLL_CLOCK_DISABLE BIT(21)
6783736352SVenkat Gopalakrishnan
685c30f340SVeerabhadrarao Badiganti #define DLL_USR_CTL_POR_VAL 0x10800
695c30f340SVeerabhadrarao Badiganti #define ENABLE_DLL_LOCK_STATUS BIT(26)
705c30f340SVeerabhadrarao Badiganti #define FINE_TUNE_MODE_EN BIT(27)
715c30f340SVeerabhadrarao Badiganti #define BIAS_OK_SIGNAL BIT(29)
725c30f340SVeerabhadrarao Badiganti
7304816e67SSarthak Garg #define DLL_CONFIG_3_LOW_FREQ_VAL 0x08
7404816e67SSarthak Garg #define DLL_CONFIG_3_HIGH_FREQ_VAL 0x10
7504816e67SSarthak Garg
76946932d9SVeerabhadrarao Badiganti #define CORE_VENDOR_SPEC_POR_VAL 0xa9c
77415b5a75SGeorgi Djakov #define CORE_CLK_PWRSAVE BIT(1)
78ff06ce41SVenkat Gopalakrishnan #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
79ff06ce41SVenkat Gopalakrishnan #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
80ff06ce41SVenkat Gopalakrishnan #define CORE_HC_MCLK_SEL_MASK (3 << 8)
81946932d9SVeerabhadrarao Badiganti #define CORE_IO_PAD_PWR_SWITCH_EN BIT(15)
82946932d9SVeerabhadrarao Badiganti #define CORE_IO_PAD_PWR_SWITCH BIT(16)
83ff06ce41SVenkat Gopalakrishnan #define CORE_HC_SELECT_IN_EN BIT(18)
84ff06ce41SVenkat Gopalakrishnan #define CORE_HC_SELECT_IN_HS400 (6 << 19)
85ff06ce41SVenkat Gopalakrishnan #define CORE_HC_SELECT_IN_MASK (7 << 19)
86415b5a75SGeorgi Djakov
87946932d9SVeerabhadrarao Badiganti #define CORE_3_0V_SUPPORT BIT(25)
88946932d9SVeerabhadrarao Badiganti #define CORE_1_8V_SUPPORT BIT(26)
895c132323SVijay Viswanath #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
90ac06fba1SVijay Viswanath
91cc392c58SRitesh Harjani #define CORE_CSR_CDC_CTLR_CFG0 0x130
92cc392c58SRitesh Harjani #define CORE_SW_TRIG_FULL_CALIB BIT(16)
93cc392c58SRitesh Harjani #define CORE_HW_AUTOCAL_ENA BIT(17)
94cc392c58SRitesh Harjani
95cc392c58SRitesh Harjani #define CORE_CSR_CDC_CTLR_CFG1 0x134
96cc392c58SRitesh Harjani #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
97cc392c58SRitesh Harjani #define CORE_TIMER_ENA BIT(16)
98cc392c58SRitesh Harjani
99cc392c58SRitesh Harjani #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
100cc392c58SRitesh Harjani #define CORE_CSR_CDC_REFCOUNT_CFG 0x140
101cc392c58SRitesh Harjani #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
102cc392c58SRitesh Harjani #define CORE_CDC_OFFSET_CFG 0x14C
103cc392c58SRitesh Harjani #define CORE_CSR_CDC_DELAY_CFG 0x150
104cc392c58SRitesh Harjani #define CORE_CDC_SLAVE_DDA_CFG 0x160
105cc392c58SRitesh Harjani #define CORE_CSR_CDC_STATUS0 0x164
106cc392c58SRitesh Harjani #define CORE_CALIBRATION_DONE BIT(0)
107cc392c58SRitesh Harjani
108cc392c58SRitesh Harjani #define CORE_CDC_ERROR_CODE_MASK 0x7000000
109cc392c58SRitesh Harjani
110cc392c58SRitesh Harjani #define CORE_CSR_CDC_GEN_CFG 0x178
111cc392c58SRitesh Harjani #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
112cc392c58SRitesh Harjani #define CORE_CDC_SWITCH_RC_EN BIT(1)
113cc392c58SRitesh Harjani
114cc392c58SRitesh Harjani #define CORE_CDC_T4_DLY_SEL BIT(0)
11544bf2312SRitesh Harjani #define CORE_CMDIN_RCLK_EN BIT(1)
116cc392c58SRitesh Harjani #define CORE_START_CDC_TRAFFIC BIT(6)
117bc99266bSSayali Lokhande
11802e4293dSRitesh Harjani #define CORE_PWRSAVE_DLL BIT(3)
11902e4293dSRitesh Harjani
120fa56ac97SVeerabhadrarao Badiganti #define DDR_CONFIG_POR_VAL 0x80040873
121cc392c58SRitesh Harjani
1223a3ad3e9SGeorgi Djakov
123abf270e5SRitesh Harjani #define INVALID_TUNING_PHASE -1
12480031bdeSRitesh Harjani #define SDHCI_MSM_MIN_CLOCK 400000
125ff06ce41SVenkat Gopalakrishnan #define CORE_FREQ_100MHZ (100 * 1000 * 1000)
12680031bdeSRitesh Harjani
127415b5a75SGeorgi Djakov #define CDR_SELEXT_SHIFT 20
128415b5a75SGeorgi Djakov #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
129415b5a75SGeorgi Djakov #define CMUX_SHIFT_PHASE_SHIFT 24
130415b5a75SGeorgi Djakov #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
131415b5a75SGeorgi Djakov
13267e6db11SPramod Gurav #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
133c0309b38SVijay Viswanath
134c0309b38SVijay Viswanath /* Timeout value to avoid infinite waiting for pwr_irq */
135c0309b38SVijay Viswanath #define MSM_PWR_IRQ_TIMEOUT_MS 5000
136c0309b38SVijay Viswanath
13792a21738SVeerabhadrarao Badiganti /* Max load for eMMC Vdd-io supply */
13892a21738SVeerabhadrarao Badiganti #define MMC_VQMMC_MAX_LOAD_UA 325000
13992a21738SVeerabhadrarao Badiganti
140bc99266bSSayali Lokhande #define msm_host_readl(msm_host, host, offset) \
141bc99266bSSayali Lokhande msm_host->var_ops->msm_readl_relaxed(host, offset)
142bc99266bSSayali Lokhande
143bc99266bSSayali Lokhande #define msm_host_writel(msm_host, val, host, offset) \
144bc99266bSSayali Lokhande msm_host->var_ops->msm_writel_relaxed(val, host, offset)
145bc99266bSSayali Lokhande
14687a8df0dSRitesh Harjani /* CQHCI vendor specific registers */
14787a8df0dSRitesh Harjani #define CQHCI_VENDOR_CFG1 0xA00
14887a8df0dSRitesh Harjani #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0x3 << 13)
14987a8df0dSRitesh Harjani
150f1535888SSayali Lokhande struct sdhci_msm_offset {
151f1535888SSayali Lokhande u32 core_hc_mode;
152f1535888SSayali Lokhande u32 core_mci_data_cnt;
153f1535888SSayali Lokhande u32 core_mci_status;
154f1535888SSayali Lokhande u32 core_mci_fifo_cnt;
155f1535888SSayali Lokhande u32 core_mci_version;
156f1535888SSayali Lokhande u32 core_generics;
157f1535888SSayali Lokhande u32 core_testbus_config;
158f1535888SSayali Lokhande u32 core_testbus_sel2_bit;
159f1535888SSayali Lokhande u32 core_testbus_ena;
160f1535888SSayali Lokhande u32 core_testbus_sel2;
161f1535888SSayali Lokhande u32 core_pwrctl_status;
162f1535888SSayali Lokhande u32 core_pwrctl_mask;
163f1535888SSayali Lokhande u32 core_pwrctl_clear;
164f1535888SSayali Lokhande u32 core_pwrctl_ctl;
165f1535888SSayali Lokhande u32 core_sdcc_debug_reg;
166f1535888SSayali Lokhande u32 core_dll_config;
167f1535888SSayali Lokhande u32 core_dll_status;
168f1535888SSayali Lokhande u32 core_vendor_spec;
169f1535888SSayali Lokhande u32 core_vendor_spec_adma_err_addr0;
170f1535888SSayali Lokhande u32 core_vendor_spec_adma_err_addr1;
171f1535888SSayali Lokhande u32 core_vendor_spec_func2;
172f1535888SSayali Lokhande u32 core_vendor_spec_capabilities0;
173f1535888SSayali Lokhande u32 core_ddr_200_cfg;
174f1535888SSayali Lokhande u32 core_vendor_spec3;
175f1535888SSayali Lokhande u32 core_dll_config_2;
176fa56ac97SVeerabhadrarao Badiganti u32 core_dll_config_3;
177fa56ac97SVeerabhadrarao Badiganti u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
178f1535888SSayali Lokhande u32 core_ddr_config;
1795c30f340SVeerabhadrarao Badiganti u32 core_dll_usr_ctl; /* Present on SDCC5.1 onwards */
180f1535888SSayali Lokhande };
181f1535888SSayali Lokhande
182f1535888SSayali Lokhande static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
183f1535888SSayali Lokhande .core_mci_data_cnt = 0x35c,
184f1535888SSayali Lokhande .core_mci_status = 0x324,
185f1535888SSayali Lokhande .core_mci_fifo_cnt = 0x308,
186f1535888SSayali Lokhande .core_mci_version = 0x318,
187f1535888SSayali Lokhande .core_generics = 0x320,
188f1535888SSayali Lokhande .core_testbus_config = 0x32c,
189f1535888SSayali Lokhande .core_testbus_sel2_bit = 3,
190f1535888SSayali Lokhande .core_testbus_ena = (1 << 31),
191f1535888SSayali Lokhande .core_testbus_sel2 = (1 << 3),
192f1535888SSayali Lokhande .core_pwrctl_status = 0x240,
193f1535888SSayali Lokhande .core_pwrctl_mask = 0x244,
194f1535888SSayali Lokhande .core_pwrctl_clear = 0x248,
195f1535888SSayali Lokhande .core_pwrctl_ctl = 0x24c,
196f1535888SSayali Lokhande .core_sdcc_debug_reg = 0x358,
197f1535888SSayali Lokhande .core_dll_config = 0x200,
198f1535888SSayali Lokhande .core_dll_status = 0x208,
199f1535888SSayali Lokhande .core_vendor_spec = 0x20c,
200f1535888SSayali Lokhande .core_vendor_spec_adma_err_addr0 = 0x214,
201f1535888SSayali Lokhande .core_vendor_spec_adma_err_addr1 = 0x218,
202f1535888SSayali Lokhande .core_vendor_spec_func2 = 0x210,
203f1535888SSayali Lokhande .core_vendor_spec_capabilities0 = 0x21c,
204f1535888SSayali Lokhande .core_ddr_200_cfg = 0x224,
205f1535888SSayali Lokhande .core_vendor_spec3 = 0x250,
206f1535888SSayali Lokhande .core_dll_config_2 = 0x254,
207fa56ac97SVeerabhadrarao Badiganti .core_dll_config_3 = 0x258,
208fa56ac97SVeerabhadrarao Badiganti .core_ddr_config = 0x25c,
2095c30f340SVeerabhadrarao Badiganti .core_dll_usr_ctl = 0x388,
210f1535888SSayali Lokhande };
211f1535888SSayali Lokhande
212f1535888SSayali Lokhande static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
213f1535888SSayali Lokhande .core_hc_mode = 0x78,
214f1535888SSayali Lokhande .core_mci_data_cnt = 0x30,
215f1535888SSayali Lokhande .core_mci_status = 0x34,
216f1535888SSayali Lokhande .core_mci_fifo_cnt = 0x44,
217f1535888SSayali Lokhande .core_mci_version = 0x050,
218f1535888SSayali Lokhande .core_generics = 0x70,
219f1535888SSayali Lokhande .core_testbus_config = 0x0cc,
220f1535888SSayali Lokhande .core_testbus_sel2_bit = 4,
221f1535888SSayali Lokhande .core_testbus_ena = (1 << 3),
222f1535888SSayali Lokhande .core_testbus_sel2 = (1 << 4),
223f1535888SSayali Lokhande .core_pwrctl_status = 0xdc,
224f1535888SSayali Lokhande .core_pwrctl_mask = 0xe0,
225f1535888SSayali Lokhande .core_pwrctl_clear = 0xe4,
226f1535888SSayali Lokhande .core_pwrctl_ctl = 0xe8,
227f1535888SSayali Lokhande .core_sdcc_debug_reg = 0x124,
228f1535888SSayali Lokhande .core_dll_config = 0x100,
229f1535888SSayali Lokhande .core_dll_status = 0x108,
230f1535888SSayali Lokhande .core_vendor_spec = 0x10c,
231f1535888SSayali Lokhande .core_vendor_spec_adma_err_addr0 = 0x114,
232f1535888SSayali Lokhande .core_vendor_spec_adma_err_addr1 = 0x118,
233f1535888SSayali Lokhande .core_vendor_spec_func2 = 0x110,
234f1535888SSayali Lokhande .core_vendor_spec_capabilities0 = 0x11c,
235f1535888SSayali Lokhande .core_ddr_200_cfg = 0x184,
236f1535888SSayali Lokhande .core_vendor_spec3 = 0x1b0,
237f1535888SSayali Lokhande .core_dll_config_2 = 0x1b4,
238fa56ac97SVeerabhadrarao Badiganti .core_ddr_config_old = 0x1b8,
239fa56ac97SVeerabhadrarao Badiganti .core_ddr_config = 0x1bc,
240f1535888SSayali Lokhande };
241f1535888SSayali Lokhande
2426ed4bb43SVijay Viswanath struct sdhci_msm_variant_ops {
2436ed4bb43SVijay Viswanath u32 (*msm_readl_relaxed)(struct sdhci_host *host, u32 offset);
2446ed4bb43SVijay Viswanath void (*msm_writel_relaxed)(u32 val, struct sdhci_host *host,
2456ed4bb43SVijay Viswanath u32 offset);
2466ed4bb43SVijay Viswanath };
2476ed4bb43SVijay Viswanath
2486ed4bb43SVijay Viswanath /*
2496ed4bb43SVijay Viswanath * From V5, register spaces have changed. Wrap this info in a structure
2506ed4bb43SVijay Viswanath * and choose the data_structure based on version info mentioned in DT.
2516ed4bb43SVijay Viswanath */
2526ed4bb43SVijay Viswanath struct sdhci_msm_variant_info {
2536ed4bb43SVijay Viswanath bool mci_removed;
25421f1e2d4SVeerabhadrarao Badiganti bool restore_dll_config;
2556ed4bb43SVijay Viswanath const struct sdhci_msm_variant_ops *var_ops;
2566ed4bb43SVijay Viswanath const struct sdhci_msm_offset *offset;
2576ed4bb43SVijay Viswanath };
2586ed4bb43SVijay Viswanath
2590eb0d9f4SGeorgi Djakov struct sdhci_msm_host {
2600eb0d9f4SGeorgi Djakov struct platform_device *pdev;
2610eb0d9f4SGeorgi Djakov void __iomem *core_mem; /* MSM SDCC mapped address */
262ad81d387SGeorgi Djakov int pwr_irq; /* power irq */
2630eb0d9f4SGeorgi Djakov struct clk *bus_clk; /* SDHC bus voter clock */
26483736352SVenkat Gopalakrishnan struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
265c7eed31eSAbel Vesa /* core, iface, cal and sleep clocks */
266c7eed31eSAbel Vesa struct clk_bulk_data bulk_clks[4];
267c7eed31eSAbel Vesa #ifdef CONFIG_MMC_CRYPTO
268c7eed31eSAbel Vesa struct qcom_ice *ice;
269c7eed31eSAbel Vesa #endif
270edc609fdSRitesh Harjani unsigned long clk_rate;
2710eb0d9f4SGeorgi Djakov struct mmc_host *mmc;
27283736352SVenkat Gopalakrishnan bool use_14lpp_dll_reset;
273ff06ce41SVenkat Gopalakrishnan bool tuning_done;
274ff06ce41SVenkat Gopalakrishnan bool calibration_done;
275abf270e5SRitesh Harjani u8 saved_tuning_phase;
27602e4293dSRitesh Harjani bool use_cdclp533;
277c0309b38SVijay Viswanath u32 curr_pwr_state;
278c0309b38SVijay Viswanath u32 curr_io_level;
279c0309b38SVijay Viswanath wait_queue_head_t pwr_irq_wait;
280c0309b38SVijay Viswanath bool pwr_irq_flag;
281ac06fba1SVijay Viswanath u32 caps_0;
2826ed4bb43SVijay Viswanath bool mci_removed;
28321f1e2d4SVeerabhadrarao Badiganti bool restore_dll_config;
2846ed4bb43SVijay Viswanath const struct sdhci_msm_variant_ops *var_ops;
2856ed4bb43SVijay Viswanath const struct sdhci_msm_offset *offset;
286a89e7bcbSLoic Poulain bool use_cdr;
287a89e7bcbSLoic Poulain u32 transfer_mode;
288fa56ac97SVeerabhadrarao Badiganti bool updated_ddr_cfg;
2895c30f340SVeerabhadrarao Badiganti bool uses_tassadar_dll;
29003591160SSarthak Garg u32 dll_config;
2911dfbe3ffSSarthak Garg u32 ddr_config;
29292a21738SVeerabhadrarao Badiganti bool vqmmc_enabled;
2930eb0d9f4SGeorgi Djakov };
2940eb0d9f4SGeorgi Djakov
sdhci_priv_msm_offset(struct sdhci_host * host)295bc99266bSSayali Lokhande static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host)
296bc99266bSSayali Lokhande {
297bc99266bSSayali Lokhande struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
298bc99266bSSayali Lokhande struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
299bc99266bSSayali Lokhande
300bc99266bSSayali Lokhande return msm_host->offset;
301bc99266bSSayali Lokhande }
302bc99266bSSayali Lokhande
3036ed4bb43SVijay Viswanath /*
3046ed4bb43SVijay Viswanath * APIs to read/write to vendor specific registers which were there in the
3056ed4bb43SVijay Viswanath * core_mem region before MCI was removed.
3066ed4bb43SVijay Viswanath */
sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host * host,u32 offset)3076ed4bb43SVijay Viswanath static u32 sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host *host,
3086ed4bb43SVijay Viswanath u32 offset)
3096ed4bb43SVijay Viswanath {
3106ed4bb43SVijay Viswanath struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
3116ed4bb43SVijay Viswanath struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
3126ed4bb43SVijay Viswanath
3136ed4bb43SVijay Viswanath return readl_relaxed(msm_host->core_mem + offset);
3146ed4bb43SVijay Viswanath }
3156ed4bb43SVijay Viswanath
sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host * host,u32 offset)3166ed4bb43SVijay Viswanath static u32 sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host *host,
3176ed4bb43SVijay Viswanath u32 offset)
3186ed4bb43SVijay Viswanath {
3196ed4bb43SVijay Viswanath return readl_relaxed(host->ioaddr + offset);
3206ed4bb43SVijay Viswanath }
3216ed4bb43SVijay Viswanath
sdhci_msm_mci_variant_writel_relaxed(u32 val,struct sdhci_host * host,u32 offset)3226ed4bb43SVijay Viswanath static void sdhci_msm_mci_variant_writel_relaxed(u32 val,
3236ed4bb43SVijay Viswanath struct sdhci_host *host, u32 offset)
3246ed4bb43SVijay Viswanath {
3256ed4bb43SVijay Viswanath struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
3266ed4bb43SVijay Viswanath struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
3276ed4bb43SVijay Viswanath
3286ed4bb43SVijay Viswanath writel_relaxed(val, msm_host->core_mem + offset);
3296ed4bb43SVijay Viswanath }
3306ed4bb43SVijay Viswanath
sdhci_msm_v5_variant_writel_relaxed(u32 val,struct sdhci_host * host,u32 offset)3316ed4bb43SVijay Viswanath static void sdhci_msm_v5_variant_writel_relaxed(u32 val,
3326ed4bb43SVijay Viswanath struct sdhci_host *host, u32 offset)
3336ed4bb43SVijay Viswanath {
3346ed4bb43SVijay Viswanath writel_relaxed(val, host->ioaddr + offset);
3356ed4bb43SVijay Viswanath }
3366ed4bb43SVijay Viswanath
msm_get_clock_mult_for_bus_mode(struct sdhci_host * host)337f16c8fd4SDouglas Anderson static unsigned int msm_get_clock_mult_for_bus_mode(struct sdhci_host *host)
3380fb8a3d4SRitesh Harjani {
3390fb8a3d4SRitesh Harjani struct mmc_ios ios = host->mmc->ios;
3400fb8a3d4SRitesh Harjani /*
3410fb8a3d4SRitesh Harjani * The SDHC requires internal clock frequency to be double the
3420fb8a3d4SRitesh Harjani * actual clock that will be set for DDR mode. The controller
3430fb8a3d4SRitesh Harjani * uses the faster clock(100/400MHz) for some of its parts and
3440fb8a3d4SRitesh Harjani * send the actual required clock (50/200MHz) to the card.
3450fb8a3d4SRitesh Harjani */
3460fb8a3d4SRitesh Harjani if (ios.timing == MMC_TIMING_UHS_DDR50 ||
3470fb8a3d4SRitesh Harjani ios.timing == MMC_TIMING_MMC_DDR52 ||
348d7507aa1SRitesh Harjani ios.timing == MMC_TIMING_MMC_HS400 ||
349d7507aa1SRitesh Harjani host->flags & SDHCI_HS400_TUNING)
350f16c8fd4SDouglas Anderson return 2;
351f16c8fd4SDouglas Anderson return 1;
3520fb8a3d4SRitesh Harjani }
3530fb8a3d4SRitesh Harjani
msm_set_clock_rate_for_bus_mode(struct sdhci_host * host,unsigned int clock)3540fb8a3d4SRitesh Harjani static void msm_set_clock_rate_for_bus_mode(struct sdhci_host *host,
3550fb8a3d4SRitesh Harjani unsigned int clock)
3560fb8a3d4SRitesh Harjani {
3570fb8a3d4SRitesh Harjani struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
3580fb8a3d4SRitesh Harjani struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
3590fb8a3d4SRitesh Harjani struct mmc_ios curr_ios = host->mmc->ios;
360e4bf91f6SBjorn Andersson struct clk *core_clk = msm_host->bulk_clks[0].clk;
361a8cd989eSDouglas Anderson unsigned long achieved_rate;
362f16c8fd4SDouglas Anderson unsigned int desired_rate;
363f16c8fd4SDouglas Anderson unsigned int mult;
3640fb8a3d4SRitesh Harjani int rc;
3650fb8a3d4SRitesh Harjani
366f16c8fd4SDouglas Anderson mult = msm_get_clock_mult_for_bus_mode(host);
367f16c8fd4SDouglas Anderson desired_rate = clock * mult;
368f16c8fd4SDouglas Anderson rc = dev_pm_opp_set_rate(mmc_dev(host->mmc), desired_rate);
3690fb8a3d4SRitesh Harjani if (rc) {
3700fb8a3d4SRitesh Harjani pr_err("%s: Failed to set clock at rate %u at timing %d\n",
371f16c8fd4SDouglas Anderson mmc_hostname(host->mmc), desired_rate, curr_ios.timing);
3720fb8a3d4SRitesh Harjani return;
3730fb8a3d4SRitesh Harjani }
374a8cd989eSDouglas Anderson
375a8cd989eSDouglas Anderson /*
376a8cd989eSDouglas Anderson * Qualcomm clock drivers by default round clock _up_ if they can't
377a8cd989eSDouglas Anderson * make the requested rate. This is not good for SD. Yell if we
378a8cd989eSDouglas Anderson * encounter it.
379a8cd989eSDouglas Anderson */
380a8cd989eSDouglas Anderson achieved_rate = clk_get_rate(core_clk);
381f16c8fd4SDouglas Anderson if (achieved_rate > desired_rate)
382a8cd989eSDouglas Anderson pr_warn("%s: Card appears overclocked; req %u Hz, actual %lu Hz\n",
383f16c8fd4SDouglas Anderson mmc_hostname(host->mmc), desired_rate, achieved_rate);
384f16c8fd4SDouglas Anderson host->mmc->actual_clock = achieved_rate / mult;
385a8cd989eSDouglas Anderson
386f16c8fd4SDouglas Anderson /* Stash the rate we requested to use in sdhci_msm_runtime_resume() */
387f16c8fd4SDouglas Anderson msm_host->clk_rate = desired_rate;
388f16c8fd4SDouglas Anderson
3890fb8a3d4SRitesh Harjani pr_debug("%s: Setting clock at rate %lu at timing %d\n",
390a8cd989eSDouglas Anderson mmc_hostname(host->mmc), achieved_rate, curr_ios.timing);
3910fb8a3d4SRitesh Harjani }
3920fb8a3d4SRitesh Harjani
3930eb0d9f4SGeorgi Djakov /* Platform specific tuning */
msm_dll_poll_ck_out_en(struct sdhci_host * host,u8 poll)394415b5a75SGeorgi Djakov static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
395415b5a75SGeorgi Djakov {
396415b5a75SGeorgi Djakov u32 wait_cnt = 50;
397415b5a75SGeorgi Djakov u8 ck_out_en;
398415b5a75SGeorgi Djakov struct mmc_host *mmc = host->mmc;
399bc99266bSSayali Lokhande const struct sdhci_msm_offset *msm_offset =
400bc99266bSSayali Lokhande sdhci_priv_msm_offset(host);
401415b5a75SGeorgi Djakov
402415b5a75SGeorgi Djakov /* Poll for CK_OUT_EN bit. max. poll time = 50us */
403bc99266bSSayali Lokhande ck_out_en = !!(readl_relaxed(host->ioaddr +
404bc99266bSSayali Lokhande msm_offset->core_dll_config) & CORE_CK_OUT_EN);
405415b5a75SGeorgi Djakov
406415b5a75SGeorgi Djakov while (ck_out_en != poll) {
407415b5a75SGeorgi Djakov if (--wait_cnt == 0) {
408415b5a75SGeorgi Djakov dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
409415b5a75SGeorgi Djakov mmc_hostname(mmc), poll);
410415b5a75SGeorgi Djakov return -ETIMEDOUT;
411415b5a75SGeorgi Djakov }
412415b5a75SGeorgi Djakov udelay(1);
413415b5a75SGeorgi Djakov
414bc99266bSSayali Lokhande ck_out_en = !!(readl_relaxed(host->ioaddr +
415bc99266bSSayali Lokhande msm_offset->core_dll_config) & CORE_CK_OUT_EN);
416415b5a75SGeorgi Djakov }
417415b5a75SGeorgi Djakov
418415b5a75SGeorgi Djakov return 0;
419415b5a75SGeorgi Djakov }
420415b5a75SGeorgi Djakov
msm_config_cm_dll_phase(struct sdhci_host * host,u8 phase)421415b5a75SGeorgi Djakov static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
422415b5a75SGeorgi Djakov {
423415b5a75SGeorgi Djakov int rc;
424415b5a75SGeorgi Djakov static const u8 grey_coded_phase_table[] = {
425415b5a75SGeorgi Djakov 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
426415b5a75SGeorgi Djakov 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
427415b5a75SGeorgi Djakov };
428415b5a75SGeorgi Djakov unsigned long flags;
429415b5a75SGeorgi Djakov u32 config;
430415b5a75SGeorgi Djakov struct mmc_host *mmc = host->mmc;
431bc99266bSSayali Lokhande const struct sdhci_msm_offset *msm_offset =
432bc99266bSSayali Lokhande sdhci_priv_msm_offset(host);
433415b5a75SGeorgi Djakov
434abf270e5SRitesh Harjani if (phase > 0xf)
435abf270e5SRitesh Harjani return -EINVAL;
436abf270e5SRitesh Harjani
437415b5a75SGeorgi Djakov spin_lock_irqsave(&host->lock, flags);
438415b5a75SGeorgi Djakov
439bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
440415b5a75SGeorgi Djakov config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
441415b5a75SGeorgi Djakov config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
442bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
443415b5a75SGeorgi Djakov
444415b5a75SGeorgi Djakov /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
445415b5a75SGeorgi Djakov rc = msm_dll_poll_ck_out_en(host, 0);
446415b5a75SGeorgi Djakov if (rc)
447415b5a75SGeorgi Djakov goto err_out;
448415b5a75SGeorgi Djakov
449415b5a75SGeorgi Djakov /*
450415b5a75SGeorgi Djakov * Write the selected DLL clock output phase (0 ... 15)
451415b5a75SGeorgi Djakov * to CDR_SELEXT bit field of DLL_CONFIG register.
452415b5a75SGeorgi Djakov */
453bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
454415b5a75SGeorgi Djakov config &= ~CDR_SELEXT_MASK;
455415b5a75SGeorgi Djakov config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
456bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
457415b5a75SGeorgi Djakov
458bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
45929301f40SRitesh Harjani config |= CORE_CK_OUT_EN;
460bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
461415b5a75SGeorgi Djakov
462415b5a75SGeorgi Djakov /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
463415b5a75SGeorgi Djakov rc = msm_dll_poll_ck_out_en(host, 1);
464415b5a75SGeorgi Djakov if (rc)
465415b5a75SGeorgi Djakov goto err_out;
466415b5a75SGeorgi Djakov
467bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
468415b5a75SGeorgi Djakov config |= CORE_CDR_EN;
469415b5a75SGeorgi Djakov config &= ~CORE_CDR_EXT_EN;
470bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
471415b5a75SGeorgi Djakov goto out;
472415b5a75SGeorgi Djakov
473415b5a75SGeorgi Djakov err_out:
474415b5a75SGeorgi Djakov dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
475415b5a75SGeorgi Djakov mmc_hostname(mmc), phase);
476415b5a75SGeorgi Djakov out:
477415b5a75SGeorgi Djakov spin_unlock_irqrestore(&host->lock, flags);
478415b5a75SGeorgi Djakov return rc;
479415b5a75SGeorgi Djakov }
480415b5a75SGeorgi Djakov
481415b5a75SGeorgi Djakov /*
482415b5a75SGeorgi Djakov * Find out the greatest range of consecuitive selected
483415b5a75SGeorgi Djakov * DLL clock output phases that can be used as sampling
484415b5a75SGeorgi Djakov * setting for SD3.0 UHS-I card read operation (in SDR104
485ff06ce41SVenkat Gopalakrishnan * timing mode) or for eMMC4.5 card read operation (in
486ff06ce41SVenkat Gopalakrishnan * HS400/HS200 timing mode).
487415b5a75SGeorgi Djakov * Select the 3/4 of the range and configure the DLL with the
488415b5a75SGeorgi Djakov * selected DLL clock output phase.
489415b5a75SGeorgi Djakov */
490415b5a75SGeorgi Djakov
msm_find_most_appropriate_phase(struct sdhci_host * host,u8 * phase_table,u8 total_phases)491415b5a75SGeorgi Djakov static int msm_find_most_appropriate_phase(struct sdhci_host *host,
492415b5a75SGeorgi Djakov u8 *phase_table, u8 total_phases)
493415b5a75SGeorgi Djakov {
494415b5a75SGeorgi Djakov int ret;
495415b5a75SGeorgi Djakov u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
496415b5a75SGeorgi Djakov u8 phases_per_row[MAX_PHASES] = { 0 };
497415b5a75SGeorgi Djakov int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
498415b5a75SGeorgi Djakov int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
499415b5a75SGeorgi Djakov bool phase_0_found = false, phase_15_found = false;
500415b5a75SGeorgi Djakov struct mmc_host *mmc = host->mmc;
501415b5a75SGeorgi Djakov
502415b5a75SGeorgi Djakov if (!total_phases || (total_phases > MAX_PHASES)) {
503415b5a75SGeorgi Djakov dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
504415b5a75SGeorgi Djakov mmc_hostname(mmc), total_phases);
505415b5a75SGeorgi Djakov return -EINVAL;
506415b5a75SGeorgi Djakov }
507415b5a75SGeorgi Djakov
508415b5a75SGeorgi Djakov for (cnt = 0; cnt < total_phases; cnt++) {
509415b5a75SGeorgi Djakov ranges[row_index][col_index] = phase_table[cnt];
510415b5a75SGeorgi Djakov phases_per_row[row_index] += 1;
511415b5a75SGeorgi Djakov col_index++;
512415b5a75SGeorgi Djakov
513415b5a75SGeorgi Djakov if ((cnt + 1) == total_phases) {
514415b5a75SGeorgi Djakov continue;
515415b5a75SGeorgi Djakov /* check if next phase in phase_table is consecutive or not */
516415b5a75SGeorgi Djakov } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
517415b5a75SGeorgi Djakov row_index++;
518415b5a75SGeorgi Djakov col_index = 0;
519415b5a75SGeorgi Djakov }
520415b5a75SGeorgi Djakov }
521415b5a75SGeorgi Djakov
522415b5a75SGeorgi Djakov if (row_index >= MAX_PHASES)
523415b5a75SGeorgi Djakov return -EINVAL;
524415b5a75SGeorgi Djakov
525415b5a75SGeorgi Djakov /* Check if phase-0 is present in first valid window? */
526415b5a75SGeorgi Djakov if (!ranges[0][0]) {
527415b5a75SGeorgi Djakov phase_0_found = true;
528415b5a75SGeorgi Djakov phase_0_raw_index = 0;
529415b5a75SGeorgi Djakov /* Check if cycle exist between 2 valid windows */
530415b5a75SGeorgi Djakov for (cnt = 1; cnt <= row_index; cnt++) {
531415b5a75SGeorgi Djakov if (phases_per_row[cnt]) {
532415b5a75SGeorgi Djakov for (i = 0; i < phases_per_row[cnt]; i++) {
533415b5a75SGeorgi Djakov if (ranges[cnt][i] == 15) {
534415b5a75SGeorgi Djakov phase_15_found = true;
535415b5a75SGeorgi Djakov phase_15_raw_index = cnt;
536415b5a75SGeorgi Djakov break;
537415b5a75SGeorgi Djakov }
538415b5a75SGeorgi Djakov }
539415b5a75SGeorgi Djakov }
540415b5a75SGeorgi Djakov }
541415b5a75SGeorgi Djakov }
542415b5a75SGeorgi Djakov
543415b5a75SGeorgi Djakov /* If 2 valid windows form cycle then merge them as single window */
544415b5a75SGeorgi Djakov if (phase_0_found && phase_15_found) {
545415b5a75SGeorgi Djakov /* number of phases in raw where phase 0 is present */
546415b5a75SGeorgi Djakov u8 phases_0 = phases_per_row[phase_0_raw_index];
547415b5a75SGeorgi Djakov /* number of phases in raw where phase 15 is present */
548415b5a75SGeorgi Djakov u8 phases_15 = phases_per_row[phase_15_raw_index];
549415b5a75SGeorgi Djakov
550415b5a75SGeorgi Djakov if (phases_0 + phases_15 >= MAX_PHASES)
551415b5a75SGeorgi Djakov /*
552415b5a75SGeorgi Djakov * If there are more than 1 phase windows then total
553415b5a75SGeorgi Djakov * number of phases in both the windows should not be
554415b5a75SGeorgi Djakov * more than or equal to MAX_PHASES.
555415b5a75SGeorgi Djakov */
556415b5a75SGeorgi Djakov return -EINVAL;
557415b5a75SGeorgi Djakov
558415b5a75SGeorgi Djakov /* Merge 2 cyclic windows */
559415b5a75SGeorgi Djakov i = phases_15;
560415b5a75SGeorgi Djakov for (cnt = 0; cnt < phases_0; cnt++) {
561415b5a75SGeorgi Djakov ranges[phase_15_raw_index][i] =
562415b5a75SGeorgi Djakov ranges[phase_0_raw_index][cnt];
563415b5a75SGeorgi Djakov if (++i >= MAX_PHASES)
564415b5a75SGeorgi Djakov break;
565415b5a75SGeorgi Djakov }
566415b5a75SGeorgi Djakov
567415b5a75SGeorgi Djakov phases_per_row[phase_0_raw_index] = 0;
568415b5a75SGeorgi Djakov phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
569415b5a75SGeorgi Djakov }
570415b5a75SGeorgi Djakov
571415b5a75SGeorgi Djakov for (cnt = 0; cnt <= row_index; cnt++) {
572415b5a75SGeorgi Djakov if (phases_per_row[cnt] > curr_max) {
573415b5a75SGeorgi Djakov curr_max = phases_per_row[cnt];
574415b5a75SGeorgi Djakov selected_row_index = cnt;
575415b5a75SGeorgi Djakov }
576415b5a75SGeorgi Djakov }
577415b5a75SGeorgi Djakov
578415b5a75SGeorgi Djakov i = (curr_max * 3) / 4;
579415b5a75SGeorgi Djakov if (i)
580415b5a75SGeorgi Djakov i--;
581415b5a75SGeorgi Djakov
582415b5a75SGeorgi Djakov ret = ranges[selected_row_index][i];
583415b5a75SGeorgi Djakov
584415b5a75SGeorgi Djakov if (ret >= MAX_PHASES) {
585415b5a75SGeorgi Djakov ret = -EINVAL;
586415b5a75SGeorgi Djakov dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
587415b5a75SGeorgi Djakov mmc_hostname(mmc), ret);
588415b5a75SGeorgi Djakov }
589415b5a75SGeorgi Djakov
590415b5a75SGeorgi Djakov return ret;
591415b5a75SGeorgi Djakov }
592415b5a75SGeorgi Djakov
msm_cm_dll_set_freq(struct sdhci_host * host)593415b5a75SGeorgi Djakov static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
594415b5a75SGeorgi Djakov {
595415b5a75SGeorgi Djakov u32 mclk_freq = 0, config;
596bc99266bSSayali Lokhande const struct sdhci_msm_offset *msm_offset =
597bc99266bSSayali Lokhande sdhci_priv_msm_offset(host);
598415b5a75SGeorgi Djakov
599415b5a75SGeorgi Djakov /* Program the MCLK value to MCLK_FREQ bit field */
600415b5a75SGeorgi Djakov if (host->clock <= 112000000)
601415b5a75SGeorgi Djakov mclk_freq = 0;
602415b5a75SGeorgi Djakov else if (host->clock <= 125000000)
603415b5a75SGeorgi Djakov mclk_freq = 1;
604415b5a75SGeorgi Djakov else if (host->clock <= 137000000)
605415b5a75SGeorgi Djakov mclk_freq = 2;
606415b5a75SGeorgi Djakov else if (host->clock <= 150000000)
607415b5a75SGeorgi Djakov mclk_freq = 3;
608415b5a75SGeorgi Djakov else if (host->clock <= 162000000)
609415b5a75SGeorgi Djakov mclk_freq = 4;
610415b5a75SGeorgi Djakov else if (host->clock <= 175000000)
611415b5a75SGeorgi Djakov mclk_freq = 5;
612415b5a75SGeorgi Djakov else if (host->clock <= 187000000)
613415b5a75SGeorgi Djakov mclk_freq = 6;
614415b5a75SGeorgi Djakov else if (host->clock <= 200000000)
615415b5a75SGeorgi Djakov mclk_freq = 7;
616415b5a75SGeorgi Djakov
617bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
618415b5a75SGeorgi Djakov config &= ~CMUX_SHIFT_PHASE_MASK;
619415b5a75SGeorgi Djakov config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
620bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
621415b5a75SGeorgi Djakov }
622415b5a75SGeorgi Djakov
623415b5a75SGeorgi Djakov /* Initialize the DLL (Programmable Delay Line) */
msm_init_cm_dll(struct sdhci_host * host)624415b5a75SGeorgi Djakov static int msm_init_cm_dll(struct sdhci_host *host)
625415b5a75SGeorgi Djakov {
626415b5a75SGeorgi Djakov struct mmc_host *mmc = host->mmc;
62783736352SVenkat Gopalakrishnan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
62883736352SVenkat Gopalakrishnan struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
629415b5a75SGeorgi Djakov int wait_cnt = 50;
6305e6b6651SJorge Ramirez-Ortiz unsigned long flags, xo_clk = 0;
63129301f40SRitesh Harjani u32 config;
632bc99266bSSayali Lokhande const struct sdhci_msm_offset *msm_offset =
633bc99266bSSayali Lokhande msm_host->offset;
634415b5a75SGeorgi Djakov
6355e6b6651SJorge Ramirez-Ortiz if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk))
6365e6b6651SJorge Ramirez-Ortiz xo_clk = clk_get_rate(msm_host->xo_clk);
6375e6b6651SJorge Ramirez-Ortiz
638415b5a75SGeorgi Djakov spin_lock_irqsave(&host->lock, flags);
639415b5a75SGeorgi Djakov
640415b5a75SGeorgi Djakov /*
641415b5a75SGeorgi Djakov * Make sure that clock is always enabled when DLL
642415b5a75SGeorgi Djakov * tuning is in progress. Keeping PWRSAVE ON may
643415b5a75SGeorgi Djakov * turn off the clock.
644415b5a75SGeorgi Djakov */
645bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
64629301f40SRitesh Harjani config &= ~CORE_CLK_PWRSAVE;
647bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
648415b5a75SGeorgi Djakov
6493ec2d511SVeerabhadrarao Badiganti if (msm_host->dll_config)
6503ec2d511SVeerabhadrarao Badiganti writel_relaxed(msm_host->dll_config,
6513ec2d511SVeerabhadrarao Badiganti host->ioaddr + msm_offset->core_dll_config);
65203591160SSarthak Garg
65383736352SVenkat Gopalakrishnan if (msm_host->use_14lpp_dll_reset) {
654bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
655bc99266bSSayali Lokhande msm_offset->core_dll_config);
65683736352SVenkat Gopalakrishnan config &= ~CORE_CK_OUT_EN;
657bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr +
658bc99266bSSayali Lokhande msm_offset->core_dll_config);
65983736352SVenkat Gopalakrishnan
660bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
661bc99266bSSayali Lokhande msm_offset->core_dll_config_2);
66283736352SVenkat Gopalakrishnan config |= CORE_DLL_CLOCK_DISABLE;
663bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr +
664bc99266bSSayali Lokhande msm_offset->core_dll_config_2);
66583736352SVenkat Gopalakrishnan }
66683736352SVenkat Gopalakrishnan
667bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
668bc99266bSSayali Lokhande msm_offset->core_dll_config);
66929301f40SRitesh Harjani config |= CORE_DLL_RST;
670bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr +
671bc99266bSSayali Lokhande msm_offset->core_dll_config);
672415b5a75SGeorgi Djakov
673bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
674bc99266bSSayali Lokhande msm_offset->core_dll_config);
67529301f40SRitesh Harjani config |= CORE_DLL_PDN;
676bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr +
677bc99266bSSayali Lokhande msm_offset->core_dll_config);
67803591160SSarthak Garg
67903591160SSarthak Garg if (!msm_host->dll_config)
680415b5a75SGeorgi Djakov msm_cm_dll_set_freq(host);
681415b5a75SGeorgi Djakov
68283736352SVenkat Gopalakrishnan if (msm_host->use_14lpp_dll_reset &&
68383736352SVenkat Gopalakrishnan !IS_ERR_OR_NULL(msm_host->xo_clk)) {
68483736352SVenkat Gopalakrishnan u32 mclk_freq = 0;
68583736352SVenkat Gopalakrishnan
686bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
687bc99266bSSayali Lokhande msm_offset->core_dll_config_2);
68883736352SVenkat Gopalakrishnan config &= CORE_FLL_CYCLE_CNT;
68983736352SVenkat Gopalakrishnan if (config)
69083736352SVenkat Gopalakrishnan mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
6915e6b6651SJorge Ramirez-Ortiz xo_clk);
69283736352SVenkat Gopalakrishnan else
69383736352SVenkat Gopalakrishnan mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
6945e6b6651SJorge Ramirez-Ortiz xo_clk);
69583736352SVenkat Gopalakrishnan
696bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
697bc99266bSSayali Lokhande msm_offset->core_dll_config_2);
69883736352SVenkat Gopalakrishnan config &= ~(0xFF << 10);
69983736352SVenkat Gopalakrishnan config |= mclk_freq << 10;
70083736352SVenkat Gopalakrishnan
701bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr +
702bc99266bSSayali Lokhande msm_offset->core_dll_config_2);
70383736352SVenkat Gopalakrishnan /* wait for 5us before enabling DLL clock */
70483736352SVenkat Gopalakrishnan udelay(5);
70583736352SVenkat Gopalakrishnan }
70683736352SVenkat Gopalakrishnan
707bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
708bc99266bSSayali Lokhande msm_offset->core_dll_config);
70929301f40SRitesh Harjani config &= ~CORE_DLL_RST;
710bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr +
711bc99266bSSayali Lokhande msm_offset->core_dll_config);
712415b5a75SGeorgi Djakov
713bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
714bc99266bSSayali Lokhande msm_offset->core_dll_config);
71529301f40SRitesh Harjani config &= ~CORE_DLL_PDN;
716bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr +
717bc99266bSSayali Lokhande msm_offset->core_dll_config);
718415b5a75SGeorgi Djakov
71983736352SVenkat Gopalakrishnan if (msm_host->use_14lpp_dll_reset) {
72003591160SSarthak Garg if (!msm_host->dll_config)
72183736352SVenkat Gopalakrishnan msm_cm_dll_set_freq(host);
722bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
723bc99266bSSayali Lokhande msm_offset->core_dll_config_2);
72483736352SVenkat Gopalakrishnan config &= ~CORE_DLL_CLOCK_DISABLE;
725bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr +
726bc99266bSSayali Lokhande msm_offset->core_dll_config_2);
72783736352SVenkat Gopalakrishnan }
72883736352SVenkat Gopalakrishnan
7295c30f340SVeerabhadrarao Badiganti /*
7305c30f340SVeerabhadrarao Badiganti * Configure DLL user control register to enable DLL status.
7315c30f340SVeerabhadrarao Badiganti * This setting is applicable to SDCC v5.1 onwards only.
7325c30f340SVeerabhadrarao Badiganti */
7335c30f340SVeerabhadrarao Badiganti if (msm_host->uses_tassadar_dll) {
7345c30f340SVeerabhadrarao Badiganti config = DLL_USR_CTL_POR_VAL | FINE_TUNE_MODE_EN |
7355c30f340SVeerabhadrarao Badiganti ENABLE_DLL_LOCK_STATUS | BIAS_OK_SIGNAL;
7365c30f340SVeerabhadrarao Badiganti writel_relaxed(config, host->ioaddr +
7375c30f340SVeerabhadrarao Badiganti msm_offset->core_dll_usr_ctl);
73804816e67SSarthak Garg
73904816e67SSarthak Garg config = readl_relaxed(host->ioaddr +
74004816e67SSarthak Garg msm_offset->core_dll_config_3);
74104816e67SSarthak Garg config &= ~0xFF;
74204816e67SSarthak Garg if (msm_host->clk_rate < 150000000)
74304816e67SSarthak Garg config |= DLL_CONFIG_3_LOW_FREQ_VAL;
74404816e67SSarthak Garg else
74504816e67SSarthak Garg config |= DLL_CONFIG_3_HIGH_FREQ_VAL;
74604816e67SSarthak Garg writel_relaxed(config, host->ioaddr +
74704816e67SSarthak Garg msm_offset->core_dll_config_3);
7485c30f340SVeerabhadrarao Badiganti }
7495c30f340SVeerabhadrarao Badiganti
750bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
751bc99266bSSayali Lokhande msm_offset->core_dll_config);
75229301f40SRitesh Harjani config |= CORE_DLL_EN;
753bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr +
754bc99266bSSayali Lokhande msm_offset->core_dll_config);
755415b5a75SGeorgi Djakov
756bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
757bc99266bSSayali Lokhande msm_offset->core_dll_config);
75829301f40SRitesh Harjani config |= CORE_CK_OUT_EN;
759bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr +
760bc99266bSSayali Lokhande msm_offset->core_dll_config);
761415b5a75SGeorgi Djakov
762415b5a75SGeorgi Djakov /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
763bc99266bSSayali Lokhande while (!(readl_relaxed(host->ioaddr + msm_offset->core_dll_status) &
764415b5a75SGeorgi Djakov CORE_DLL_LOCK)) {
765415b5a75SGeorgi Djakov /* max. wait for 50us sec for LOCK bit to be set */
766415b5a75SGeorgi Djakov if (--wait_cnt == 0) {
767415b5a75SGeorgi Djakov dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
768415b5a75SGeorgi Djakov mmc_hostname(mmc));
769415b5a75SGeorgi Djakov spin_unlock_irqrestore(&host->lock, flags);
770415b5a75SGeorgi Djakov return -ETIMEDOUT;
771415b5a75SGeorgi Djakov }
772415b5a75SGeorgi Djakov udelay(1);
773415b5a75SGeorgi Djakov }
774415b5a75SGeorgi Djakov
775415b5a75SGeorgi Djakov spin_unlock_irqrestore(&host->lock, flags);
776415b5a75SGeorgi Djakov return 0;
777415b5a75SGeorgi Djakov }
778415b5a75SGeorgi Djakov
msm_hc_select_default(struct sdhci_host * host)779b54aaa8aSRitesh Harjani static void msm_hc_select_default(struct sdhci_host *host)
780b54aaa8aSRitesh Harjani {
781b54aaa8aSRitesh Harjani struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
782b54aaa8aSRitesh Harjani struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
783b54aaa8aSRitesh Harjani u32 config;
784bc99266bSSayali Lokhande const struct sdhci_msm_offset *msm_offset =
785bc99266bSSayali Lokhande msm_host->offset;
786b54aaa8aSRitesh Harjani
787b54aaa8aSRitesh Harjani if (!msm_host->use_cdclp533) {
788b54aaa8aSRitesh Harjani config = readl_relaxed(host->ioaddr +
789bc99266bSSayali Lokhande msm_offset->core_vendor_spec3);
790b54aaa8aSRitesh Harjani config &= ~CORE_PWRSAVE_DLL;
791b54aaa8aSRitesh Harjani writel_relaxed(config, host->ioaddr +
792bc99266bSSayali Lokhande msm_offset->core_vendor_spec3);
793b54aaa8aSRitesh Harjani }
794b54aaa8aSRitesh Harjani
795bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
796b54aaa8aSRitesh Harjani config &= ~CORE_HC_MCLK_SEL_MASK;
797b54aaa8aSRitesh Harjani config |= CORE_HC_MCLK_SEL_DFLT;
798bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
799b54aaa8aSRitesh Harjani
800b54aaa8aSRitesh Harjani /*
801b54aaa8aSRitesh Harjani * Disable HC_SELECT_IN to be able to use the UHS mode select
802b54aaa8aSRitesh Harjani * configuration from Host Control2 register for all other
803b54aaa8aSRitesh Harjani * modes.
804b54aaa8aSRitesh Harjani * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
805b54aaa8aSRitesh Harjani * in VENDOR_SPEC_FUNC
806b54aaa8aSRitesh Harjani */
807bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
808b54aaa8aSRitesh Harjani config &= ~CORE_HC_SELECT_IN_EN;
809b54aaa8aSRitesh Harjani config &= ~CORE_HC_SELECT_IN_MASK;
810bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
811b54aaa8aSRitesh Harjani
812b54aaa8aSRitesh Harjani /*
813b54aaa8aSRitesh Harjani * Make sure above writes impacting free running MCLK are completed
814b54aaa8aSRitesh Harjani * before changing the clk_rate at GCC.
815b54aaa8aSRitesh Harjani */
816b54aaa8aSRitesh Harjani wmb();
817b54aaa8aSRitesh Harjani }
818b54aaa8aSRitesh Harjani
msm_hc_select_hs400(struct sdhci_host * host)819b54aaa8aSRitesh Harjani static void msm_hc_select_hs400(struct sdhci_host *host)
820b54aaa8aSRitesh Harjani {
821b54aaa8aSRitesh Harjani struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
822b54aaa8aSRitesh Harjani struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
82344bf2312SRitesh Harjani struct mmc_ios ios = host->mmc->ios;
824b54aaa8aSRitesh Harjani u32 config, dll_lock;
825b54aaa8aSRitesh Harjani int rc;
826bc99266bSSayali Lokhande const struct sdhci_msm_offset *msm_offset =
827bc99266bSSayali Lokhande msm_host->offset;
828b54aaa8aSRitesh Harjani
829b54aaa8aSRitesh Harjani /* Select the divided clock (free running MCLK/2) */
830bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec);
831b54aaa8aSRitesh Harjani config &= ~CORE_HC_MCLK_SEL_MASK;
832b54aaa8aSRitesh Harjani config |= CORE_HC_MCLK_SEL_HS400;
833b54aaa8aSRitesh Harjani
834bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec);
835b54aaa8aSRitesh Harjani /*
836b54aaa8aSRitesh Harjani * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
837b54aaa8aSRitesh Harjani * register
838b54aaa8aSRitesh Harjani */
83944bf2312SRitesh Harjani if ((msm_host->tuning_done || ios.enhanced_strobe) &&
84044bf2312SRitesh Harjani !msm_host->calibration_done) {
841bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
842bc99266bSSayali Lokhande msm_offset->core_vendor_spec);
843b54aaa8aSRitesh Harjani config |= CORE_HC_SELECT_IN_HS400;
844b54aaa8aSRitesh Harjani config |= CORE_HC_SELECT_IN_EN;
845bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr +
846bc99266bSSayali Lokhande msm_offset->core_vendor_spec);
847b54aaa8aSRitesh Harjani }
848b54aaa8aSRitesh Harjani if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
849b54aaa8aSRitesh Harjani /*
850b54aaa8aSRitesh Harjani * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
851bc99266bSSayali Lokhande * core_dll_status to be set. This should get set
852b54aaa8aSRitesh Harjani * within 15 us at 200 MHz.
853b54aaa8aSRitesh Harjani */
854b54aaa8aSRitesh Harjani rc = readl_relaxed_poll_timeout(host->ioaddr +
855bc99266bSSayali Lokhande msm_offset->core_dll_status,
856b54aaa8aSRitesh Harjani dll_lock,
857b54aaa8aSRitesh Harjani (dll_lock &
858b54aaa8aSRitesh Harjani (CORE_DLL_LOCK |
859b54aaa8aSRitesh Harjani CORE_DDR_DLL_LOCK)), 10,
860b54aaa8aSRitesh Harjani 1000);
861b54aaa8aSRitesh Harjani if (rc == -ETIMEDOUT)
862b54aaa8aSRitesh Harjani pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
863b54aaa8aSRitesh Harjani mmc_hostname(host->mmc), dll_lock);
864b54aaa8aSRitesh Harjani }
865b54aaa8aSRitesh Harjani /*
866b54aaa8aSRitesh Harjani * Make sure above writes impacting free running MCLK are completed
867b54aaa8aSRitesh Harjani * before changing the clk_rate at GCC.
868b54aaa8aSRitesh Harjani */
869b54aaa8aSRitesh Harjani wmb();
870b54aaa8aSRitesh Harjani }
871b54aaa8aSRitesh Harjani
872b54aaa8aSRitesh Harjani /*
873b54aaa8aSRitesh Harjani * sdhci_msm_hc_select_mode :- In general all timing modes are
874b54aaa8aSRitesh Harjani * controlled via UHS mode select in Host Control2 register.
875b54aaa8aSRitesh Harjani * eMMC specific HS200/HS400 doesn't have their respective modes
876b54aaa8aSRitesh Harjani * defined here, hence we use these values.
877b54aaa8aSRitesh Harjani *
878b54aaa8aSRitesh Harjani * HS200 - SDR104 (Since they both are equivalent in functionality)
879b54aaa8aSRitesh Harjani * HS400 - This involves multiple configurations
880b54aaa8aSRitesh Harjani * Initially SDR104 - when tuning is required as HS200
881b54aaa8aSRitesh Harjani * Then when switching to DDR @ 400MHz (HS400) we use
882b54aaa8aSRitesh Harjani * the vendor specific HC_SELECT_IN to control the mode.
883b54aaa8aSRitesh Harjani *
884b54aaa8aSRitesh Harjani * In addition to controlling the modes we also need to select the
885b54aaa8aSRitesh Harjani * correct input clock for DLL depending on the mode.
886b54aaa8aSRitesh Harjani *
887b54aaa8aSRitesh Harjani * HS400 - divided clock (free running MCLK/2)
888b54aaa8aSRitesh Harjani * All other modes - default (free running MCLK)
889b54aaa8aSRitesh Harjani */
sdhci_msm_hc_select_mode(struct sdhci_host * host)89030de038dSMasahiro Yamada static void sdhci_msm_hc_select_mode(struct sdhci_host *host)
891b54aaa8aSRitesh Harjani {
892b54aaa8aSRitesh Harjani struct mmc_ios ios = host->mmc->ios;
893b54aaa8aSRitesh Harjani
894d7507aa1SRitesh Harjani if (ios.timing == MMC_TIMING_MMC_HS400 ||
895d7507aa1SRitesh Harjani host->flags & SDHCI_HS400_TUNING)
896b54aaa8aSRitesh Harjani msm_hc_select_hs400(host);
897b54aaa8aSRitesh Harjani else
898b54aaa8aSRitesh Harjani msm_hc_select_default(host);
899b54aaa8aSRitesh Harjani }
900b54aaa8aSRitesh Harjani
sdhci_msm_cdclp533_calibration(struct sdhci_host * host)901cc392c58SRitesh Harjani static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
902cc392c58SRitesh Harjani {
903cc392c58SRitesh Harjani struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
904cc392c58SRitesh Harjani struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
905cc392c58SRitesh Harjani u32 config, calib_done;
906cc392c58SRitesh Harjani int ret;
907bc99266bSSayali Lokhande const struct sdhci_msm_offset *msm_offset =
908bc99266bSSayali Lokhande msm_host->offset;
909cc392c58SRitesh Harjani
910cc392c58SRitesh Harjani pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
911cc392c58SRitesh Harjani
912cc392c58SRitesh Harjani /*
913cc392c58SRitesh Harjani * Retuning in HS400 (DDR mode) will fail, just reset the
914cc392c58SRitesh Harjani * tuning block and restore the saved tuning phase.
915cc392c58SRitesh Harjani */
916cc392c58SRitesh Harjani ret = msm_init_cm_dll(host);
917cc392c58SRitesh Harjani if (ret)
918cc392c58SRitesh Harjani goto out;
919cc392c58SRitesh Harjani
920cc392c58SRitesh Harjani /* Set the selected phase in delay line hw block */
921cc392c58SRitesh Harjani ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
922cc392c58SRitesh Harjani if (ret)
923cc392c58SRitesh Harjani goto out;
924cc392c58SRitesh Harjani
925bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config);
926cc392c58SRitesh Harjani config |= CORE_CMD_DAT_TRACK_SEL;
927bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config);
928cc392c58SRitesh Harjani
929bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
930cc392c58SRitesh Harjani config &= ~CORE_CDC_T4_DLY_SEL;
931bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
932cc392c58SRitesh Harjani
933cc392c58SRitesh Harjani config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
934cc392c58SRitesh Harjani config &= ~CORE_CDC_SWITCH_BYPASS_OFF;
935cc392c58SRitesh Harjani writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
936cc392c58SRitesh Harjani
937cc392c58SRitesh Harjani config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_GEN_CFG);
938cc392c58SRitesh Harjani config |= CORE_CDC_SWITCH_RC_EN;
939cc392c58SRitesh Harjani writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_GEN_CFG);
940cc392c58SRitesh Harjani
941bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
942cc392c58SRitesh Harjani config &= ~CORE_START_CDC_TRAFFIC;
943bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
944cc392c58SRitesh Harjani
945543c576dSRitesh Harjani /* Perform CDC Register Initialization Sequence */
946cc392c58SRitesh Harjani
947cc392c58SRitesh Harjani writel_relaxed(0x11800EC, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
948cc392c58SRitesh Harjani writel_relaxed(0x3011111, host->ioaddr + CORE_CSR_CDC_CTLR_CFG1);
949cc392c58SRitesh Harjani writel_relaxed(0x1201000, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
950cc392c58SRitesh Harjani writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
951cc392c58SRitesh Harjani writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
952cc392c58SRitesh Harjani writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
953083c9aa0SSubhash Jadavani writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
954cc392c58SRitesh Harjani writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
955cc392c58SRitesh Harjani writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
956cc392c58SRitesh Harjani
957cc392c58SRitesh Harjani /* CDC HW Calibration */
958cc392c58SRitesh Harjani
959cc392c58SRitesh Harjani config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
960cc392c58SRitesh Harjani config |= CORE_SW_TRIG_FULL_CALIB;
961cc392c58SRitesh Harjani writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
962cc392c58SRitesh Harjani
963cc392c58SRitesh Harjani config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
964cc392c58SRitesh Harjani config &= ~CORE_SW_TRIG_FULL_CALIB;
965cc392c58SRitesh Harjani writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
966cc392c58SRitesh Harjani
967cc392c58SRitesh Harjani config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
968cc392c58SRitesh Harjani config |= CORE_HW_AUTOCAL_ENA;
969cc392c58SRitesh Harjani writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CTLR_CFG0);
970cc392c58SRitesh Harjani
971cc392c58SRitesh Harjani config = readl_relaxed(host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
972cc392c58SRitesh Harjani config |= CORE_TIMER_ENA;
973cc392c58SRitesh Harjani writel_relaxed(config, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG0);
974cc392c58SRitesh Harjani
975cc392c58SRitesh Harjani ret = readl_relaxed_poll_timeout(host->ioaddr + CORE_CSR_CDC_STATUS0,
976cc392c58SRitesh Harjani calib_done,
977cc392c58SRitesh Harjani (calib_done & CORE_CALIBRATION_DONE),
978cc392c58SRitesh Harjani 1, 50);
979cc392c58SRitesh Harjani
980cc392c58SRitesh Harjani if (ret == -ETIMEDOUT) {
981cc392c58SRitesh Harjani pr_err("%s: %s: CDC calibration was not completed\n",
982cc392c58SRitesh Harjani mmc_hostname(host->mmc), __func__);
983cc392c58SRitesh Harjani goto out;
984cc392c58SRitesh Harjani }
985cc392c58SRitesh Harjani
986cc392c58SRitesh Harjani ret = readl_relaxed(host->ioaddr + CORE_CSR_CDC_STATUS0)
987cc392c58SRitesh Harjani & CORE_CDC_ERROR_CODE_MASK;
988cc392c58SRitesh Harjani if (ret) {
989cc392c58SRitesh Harjani pr_err("%s: %s: CDC error code %d\n",
990cc392c58SRitesh Harjani mmc_hostname(host->mmc), __func__, ret);
991cc392c58SRitesh Harjani ret = -EINVAL;
992cc392c58SRitesh Harjani goto out;
993cc392c58SRitesh Harjani }
994cc392c58SRitesh Harjani
995bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr + msm_offset->core_ddr_200_cfg);
996cc392c58SRitesh Harjani config |= CORE_START_CDC_TRAFFIC;
997bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr + msm_offset->core_ddr_200_cfg);
998cc392c58SRitesh Harjani out:
999cc392c58SRitesh Harjani pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
1000cc392c58SRitesh Harjani __func__, ret);
1001cc392c58SRitesh Harjani return ret;
1002cc392c58SRitesh Harjani }
1003cc392c58SRitesh Harjani
sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host * host)100402e4293dSRitesh Harjani static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
100502e4293dSRitesh Harjani {
100644bf2312SRitesh Harjani struct mmc_host *mmc = host->mmc;
1007fa56ac97SVeerabhadrarao Badiganti u32 dll_status, config, ddr_cfg_offset;
100802e4293dSRitesh Harjani int ret;
1009fa56ac97SVeerabhadrarao Badiganti struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1010fa56ac97SVeerabhadrarao Badiganti struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1011bc99266bSSayali Lokhande const struct sdhci_msm_offset *msm_offset =
1012bc99266bSSayali Lokhande sdhci_priv_msm_offset(host);
101302e4293dSRitesh Harjani
101402e4293dSRitesh Harjani pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
101502e4293dSRitesh Harjani
101602e4293dSRitesh Harjani /*
1017bc99266bSSayali Lokhande * Currently the core_ddr_config register defaults to desired
101802e4293dSRitesh Harjani * configuration on reset. Currently reprogramming the power on
101902e4293dSRitesh Harjani * reset (POR) value in case it might have been modified by
102002e4293dSRitesh Harjani * bootloaders. In the future, if this changes, then the desired
102102e4293dSRitesh Harjani * values will need to be programmed appropriately.
102202e4293dSRitesh Harjani */
1023fa56ac97SVeerabhadrarao Badiganti if (msm_host->updated_ddr_cfg)
1024fa56ac97SVeerabhadrarao Badiganti ddr_cfg_offset = msm_offset->core_ddr_config;
1025fa56ac97SVeerabhadrarao Badiganti else
1026fa56ac97SVeerabhadrarao Badiganti ddr_cfg_offset = msm_offset->core_ddr_config_old;
10271dfbe3ffSSarthak Garg writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset);
102802e4293dSRitesh Harjani
102944bf2312SRitesh Harjani if (mmc->ios.enhanced_strobe) {
1030bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
1031bc99266bSSayali Lokhande msm_offset->core_ddr_200_cfg);
103244bf2312SRitesh Harjani config |= CORE_CMDIN_RCLK_EN;
1033bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr +
1034bc99266bSSayali Lokhande msm_offset->core_ddr_200_cfg);
103544bf2312SRitesh Harjani }
103644bf2312SRitesh Harjani
1037bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2);
103802e4293dSRitesh Harjani config |= CORE_DDR_CAL_EN;
1039bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr + msm_offset->core_dll_config_2);
104002e4293dSRitesh Harjani
1041bc99266bSSayali Lokhande ret = readl_relaxed_poll_timeout(host->ioaddr +
1042bc99266bSSayali Lokhande msm_offset->core_dll_status,
104302e4293dSRitesh Harjani dll_status,
104402e4293dSRitesh Harjani (dll_status & CORE_DDR_DLL_LOCK),
104502e4293dSRitesh Harjani 10, 1000);
104602e4293dSRitesh Harjani
104702e4293dSRitesh Harjani if (ret == -ETIMEDOUT) {
104802e4293dSRitesh Harjani pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
104902e4293dSRitesh Harjani mmc_hostname(host->mmc), __func__);
105002e4293dSRitesh Harjani goto out;
105102e4293dSRitesh Harjani }
105202e4293dSRitesh Harjani
1053219c02caSRitesh Harjani /*
1054219c02caSRitesh Harjani * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3.
1055219c02caSRitesh Harjani * When MCLK is gated OFF, it is not gated for less than 0.5us
1056219c02caSRitesh Harjani * and MCLK must be switched on for at-least 1us before DATA
1057219c02caSRitesh Harjani * starts coming. Controllers with 14lpp and later tech DLL cannot
1058219c02caSRitesh Harjani * guarantee above requirement. So PWRSAVE_DLL should not be
1059219c02caSRitesh Harjani * turned on for host controllers using this DLL.
1060219c02caSRitesh Harjani */
1061219c02caSRitesh Harjani if (!msm_host->use_14lpp_dll_reset) {
1062219c02caSRitesh Harjani config = readl_relaxed(host->ioaddr +
1063219c02caSRitesh Harjani msm_offset->core_vendor_spec3);
106402e4293dSRitesh Harjani config |= CORE_PWRSAVE_DLL;
1065219c02caSRitesh Harjani writel_relaxed(config, host->ioaddr +
1066219c02caSRitesh Harjani msm_offset->core_vendor_spec3);
1067219c02caSRitesh Harjani }
106802e4293dSRitesh Harjani
106902e4293dSRitesh Harjani /*
107002e4293dSRitesh Harjani * Drain writebuffer to ensure above DLL calibration
107102e4293dSRitesh Harjani * and PWRSAVE DLL is enabled.
107202e4293dSRitesh Harjani */
107302e4293dSRitesh Harjani wmb();
107402e4293dSRitesh Harjani out:
107502e4293dSRitesh Harjani pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
107602e4293dSRitesh Harjani __func__, ret);
107702e4293dSRitesh Harjani return ret;
107802e4293dSRitesh Harjani }
107902e4293dSRitesh Harjani
sdhci_msm_hs400_dll_calibration(struct sdhci_host * host)108002e4293dSRitesh Harjani static int sdhci_msm_hs400_dll_calibration(struct sdhci_host *host)
108102e4293dSRitesh Harjani {
108202e4293dSRitesh Harjani struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
108302e4293dSRitesh Harjani struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
108444bf2312SRitesh Harjani struct mmc_host *mmc = host->mmc;
108502e4293dSRitesh Harjani int ret;
108602e4293dSRitesh Harjani u32 config;
1087bc99266bSSayali Lokhande const struct sdhci_msm_offset *msm_offset =
1088bc99266bSSayali Lokhande msm_host->offset;
108902e4293dSRitesh Harjani
109002e4293dSRitesh Harjani pr_debug("%s: %s: Enter\n", mmc_hostname(host->mmc), __func__);
109102e4293dSRitesh Harjani
109202e4293dSRitesh Harjani /*
109302e4293dSRitesh Harjani * Retuning in HS400 (DDR mode) will fail, just reset the
109402e4293dSRitesh Harjani * tuning block and restore the saved tuning phase.
109502e4293dSRitesh Harjani */
109602e4293dSRitesh Harjani ret = msm_init_cm_dll(host);
109702e4293dSRitesh Harjani if (ret)
109802e4293dSRitesh Harjani goto out;
109902e4293dSRitesh Harjani
110044bf2312SRitesh Harjani if (!mmc->ios.enhanced_strobe) {
110102e4293dSRitesh Harjani /* Set the selected phase in delay line hw block */
110244bf2312SRitesh Harjani ret = msm_config_cm_dll_phase(host,
110344bf2312SRitesh Harjani msm_host->saved_tuning_phase);
110402e4293dSRitesh Harjani if (ret)
110502e4293dSRitesh Harjani goto out;
1106bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
1107bc99266bSSayali Lokhande msm_offset->core_dll_config);
110802e4293dSRitesh Harjani config |= CORE_CMD_DAT_TRACK_SEL;
1109bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr +
1110bc99266bSSayali Lokhande msm_offset->core_dll_config);
111144bf2312SRitesh Harjani }
111244bf2312SRitesh Harjani
111302e4293dSRitesh Harjani if (msm_host->use_cdclp533)
111402e4293dSRitesh Harjani ret = sdhci_msm_cdclp533_calibration(host);
111502e4293dSRitesh Harjani else
111602e4293dSRitesh Harjani ret = sdhci_msm_cm_dll_sdc4_calibration(host);
111702e4293dSRitesh Harjani out:
111802e4293dSRitesh Harjani pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host->mmc),
111902e4293dSRitesh Harjani __func__, ret);
112002e4293dSRitesh Harjani return ret;
112102e4293dSRitesh Harjani }
112202e4293dSRitesh Harjani
sdhci_msm_is_tuning_needed(struct sdhci_host * host)112321f1e2d4SVeerabhadrarao Badiganti static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host)
112421f1e2d4SVeerabhadrarao Badiganti {
112521f1e2d4SVeerabhadrarao Badiganti struct mmc_ios *ios = &host->mmc->ios;
112621f1e2d4SVeerabhadrarao Badiganti
112721f1e2d4SVeerabhadrarao Badiganti /*
112821f1e2d4SVeerabhadrarao Badiganti * Tuning is required for SDR104, HS200 and HS400 cards and
112921f1e2d4SVeerabhadrarao Badiganti * if clock frequency is greater than 100MHz in these modes.
113021f1e2d4SVeerabhadrarao Badiganti */
113121f1e2d4SVeerabhadrarao Badiganti if (host->clock <= CORE_FREQ_100MHZ ||
113221f1e2d4SVeerabhadrarao Badiganti !(ios->timing == MMC_TIMING_MMC_HS400 ||
113321f1e2d4SVeerabhadrarao Badiganti ios->timing == MMC_TIMING_MMC_HS200 ||
113421f1e2d4SVeerabhadrarao Badiganti ios->timing == MMC_TIMING_UHS_SDR104) ||
113521f1e2d4SVeerabhadrarao Badiganti ios->enhanced_strobe)
113621f1e2d4SVeerabhadrarao Badiganti return false;
113721f1e2d4SVeerabhadrarao Badiganti
113821f1e2d4SVeerabhadrarao Badiganti return true;
113921f1e2d4SVeerabhadrarao Badiganti }
114021f1e2d4SVeerabhadrarao Badiganti
sdhci_msm_restore_sdr_dll_config(struct sdhci_host * host)114121f1e2d4SVeerabhadrarao Badiganti static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host *host)
114221f1e2d4SVeerabhadrarao Badiganti {
114321f1e2d4SVeerabhadrarao Badiganti struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
114421f1e2d4SVeerabhadrarao Badiganti struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
114521f1e2d4SVeerabhadrarao Badiganti int ret;
114621f1e2d4SVeerabhadrarao Badiganti
114721f1e2d4SVeerabhadrarao Badiganti /*
114821f1e2d4SVeerabhadrarao Badiganti * SDR DLL comes into picture only for timing modes which needs
114921f1e2d4SVeerabhadrarao Badiganti * tuning.
115021f1e2d4SVeerabhadrarao Badiganti */
115121f1e2d4SVeerabhadrarao Badiganti if (!sdhci_msm_is_tuning_needed(host))
115221f1e2d4SVeerabhadrarao Badiganti return 0;
115321f1e2d4SVeerabhadrarao Badiganti
115421f1e2d4SVeerabhadrarao Badiganti /* Reset the tuning block */
115521f1e2d4SVeerabhadrarao Badiganti ret = msm_init_cm_dll(host);
115621f1e2d4SVeerabhadrarao Badiganti if (ret)
115721f1e2d4SVeerabhadrarao Badiganti return ret;
115821f1e2d4SVeerabhadrarao Badiganti
115921f1e2d4SVeerabhadrarao Badiganti /* Restore the tuning block */
116021f1e2d4SVeerabhadrarao Badiganti ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase);
116121f1e2d4SVeerabhadrarao Badiganti
116221f1e2d4SVeerabhadrarao Badiganti return ret;
116321f1e2d4SVeerabhadrarao Badiganti }
116421f1e2d4SVeerabhadrarao Badiganti
sdhci_msm_set_cdr(struct sdhci_host * host,bool enable)1165a89e7bcbSLoic Poulain static void sdhci_msm_set_cdr(struct sdhci_host *host, bool enable)
1166a89e7bcbSLoic Poulain {
1167a89e7bcbSLoic Poulain const struct sdhci_msm_offset *msm_offset = sdhci_priv_msm_offset(host);
1168a89e7bcbSLoic Poulain u32 config, oldconfig = readl_relaxed(host->ioaddr +
1169a89e7bcbSLoic Poulain msm_offset->core_dll_config);
1170a89e7bcbSLoic Poulain
1171a89e7bcbSLoic Poulain config = oldconfig;
1172a89e7bcbSLoic Poulain if (enable) {
1173a89e7bcbSLoic Poulain config |= CORE_CDR_EN;
1174a89e7bcbSLoic Poulain config &= ~CORE_CDR_EXT_EN;
1175a89e7bcbSLoic Poulain } else {
1176a89e7bcbSLoic Poulain config &= ~CORE_CDR_EN;
1177a89e7bcbSLoic Poulain config |= CORE_CDR_EXT_EN;
1178a89e7bcbSLoic Poulain }
1179a89e7bcbSLoic Poulain
1180a89e7bcbSLoic Poulain if (config != oldconfig) {
1181a89e7bcbSLoic Poulain writel_relaxed(config, host->ioaddr +
1182a89e7bcbSLoic Poulain msm_offset->core_dll_config);
1183a89e7bcbSLoic Poulain }
1184a89e7bcbSLoic Poulain }
1185a89e7bcbSLoic Poulain
sdhci_msm_execute_tuning(struct mmc_host * mmc,u32 opcode)11864436c535SRitesh Harjani static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode)
11870eb0d9f4SGeorgi Djakov {
11884436c535SRitesh Harjani struct sdhci_host *host = mmc_priv(mmc);
11899d5dcefbSDouglas Anderson int tuning_seq_cnt = 10;
119033d73935SUlf Hansson u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
1191415b5a75SGeorgi Djakov int rc;
1192415b5a75SGeorgi Djakov struct mmc_ios ios = host->mmc->ios;
1193abf270e5SRitesh Harjani struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1194abf270e5SRitesh Harjani struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1195415b5a75SGeorgi Djakov
1196a89e7bcbSLoic Poulain if (!sdhci_msm_is_tuning_needed(host)) {
1197a89e7bcbSLoic Poulain msm_host->use_cdr = false;
1198a89e7bcbSLoic Poulain sdhci_msm_set_cdr(host, false);
11990eb0d9f4SGeorgi Djakov return 0;
1200a89e7bcbSLoic Poulain }
1201a89e7bcbSLoic Poulain
1202a89e7bcbSLoic Poulain /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
1203a89e7bcbSLoic Poulain msm_host->use_cdr = true;
1204415b5a75SGeorgi Djakov
1205d7507aa1SRitesh Harjani /*
12069253d710SVeerabhadrarao Badiganti * Clear tuning_done flag before tuning to ensure proper
12079253d710SVeerabhadrarao Badiganti * HS400 settings.
12089253d710SVeerabhadrarao Badiganti */
12099253d710SVeerabhadrarao Badiganti msm_host->tuning_done = 0;
12109253d710SVeerabhadrarao Badiganti
12119253d710SVeerabhadrarao Badiganti /*
1212d7507aa1SRitesh Harjani * For HS400 tuning in HS200 timing requires:
1213d7507aa1SRitesh Harjani * - select MCLK/2 in VENDOR_SPEC
1214d7507aa1SRitesh Harjani * - program MCLK to 400MHz (or nearest supported) in GCC
1215d7507aa1SRitesh Harjani */
1216d7507aa1SRitesh Harjani if (host->flags & SDHCI_HS400_TUNING) {
1217d7507aa1SRitesh Harjani sdhci_msm_hc_select_mode(host);
1218d7507aa1SRitesh Harjani msm_set_clock_rate_for_bus_mode(host, ios.clock);
12194436c535SRitesh Harjani host->flags &= ~SDHCI_HS400_TUNING;
1220d7507aa1SRitesh Harjani }
1221d7507aa1SRitesh Harjani
1222415b5a75SGeorgi Djakov retry:
1223415b5a75SGeorgi Djakov /* First of all reset the tuning block */
1224415b5a75SGeorgi Djakov rc = msm_init_cm_dll(host);
1225415b5a75SGeorgi Djakov if (rc)
122633d73935SUlf Hansson return rc;
1227415b5a75SGeorgi Djakov
1228415b5a75SGeorgi Djakov phase = 0;
1229415b5a75SGeorgi Djakov do {
1230415b5a75SGeorgi Djakov /* Set the phase in delay line hw block */
1231415b5a75SGeorgi Djakov rc = msm_config_cm_dll_phase(host, phase);
1232415b5a75SGeorgi Djakov if (rc)
123333d73935SUlf Hansson return rc;
1234415b5a75SGeorgi Djakov
12359979dbe5SChaotian Jing rc = mmc_send_tuning(mmc, opcode, NULL);
123633d73935SUlf Hansson if (!rc) {
1237415b5a75SGeorgi Djakov /* Tuning is successful at this tuning point */
1238415b5a75SGeorgi Djakov tuned_phases[tuned_phase_cnt++] = phase;
1239415b5a75SGeorgi Djakov dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
1240415b5a75SGeorgi Djakov mmc_hostname(mmc), phase);
1241415b5a75SGeorgi Djakov }
1242415b5a75SGeorgi Djakov } while (++phase < ARRAY_SIZE(tuned_phases));
1243415b5a75SGeorgi Djakov
1244415b5a75SGeorgi Djakov if (tuned_phase_cnt) {
12459d5dcefbSDouglas Anderson if (tuned_phase_cnt == ARRAY_SIZE(tuned_phases)) {
12469d5dcefbSDouglas Anderson /*
12479d5dcefbSDouglas Anderson * All phases valid is _almost_ as bad as no phases
12489d5dcefbSDouglas Anderson * valid. Probably all phases are not really reliable
12499d5dcefbSDouglas Anderson * but we didn't detect where the unreliable place is.
12509d5dcefbSDouglas Anderson * That means we'll essentially be guessing and hoping
12519d5dcefbSDouglas Anderson * we get a good phase. Better to try a few times.
12529d5dcefbSDouglas Anderson */
12539d5dcefbSDouglas Anderson dev_dbg(mmc_dev(mmc), "%s: All phases valid; try again\n",
12549d5dcefbSDouglas Anderson mmc_hostname(mmc));
12559d5dcefbSDouglas Anderson if (--tuning_seq_cnt) {
12569d5dcefbSDouglas Anderson tuned_phase_cnt = 0;
12579d5dcefbSDouglas Anderson goto retry;
12589d5dcefbSDouglas Anderson }
12599d5dcefbSDouglas Anderson }
12609d5dcefbSDouglas Anderson
1261415b5a75SGeorgi Djakov rc = msm_find_most_appropriate_phase(host, tuned_phases,
1262415b5a75SGeorgi Djakov tuned_phase_cnt);
1263415b5a75SGeorgi Djakov if (rc < 0)
126433d73935SUlf Hansson return rc;
1265415b5a75SGeorgi Djakov else
1266415b5a75SGeorgi Djakov phase = rc;
1267415b5a75SGeorgi Djakov
1268415b5a75SGeorgi Djakov /*
1269415b5a75SGeorgi Djakov * Finally set the selected phase in delay
1270415b5a75SGeorgi Djakov * line hw block.
1271415b5a75SGeorgi Djakov */
1272415b5a75SGeorgi Djakov rc = msm_config_cm_dll_phase(host, phase);
1273415b5a75SGeorgi Djakov if (rc)
127433d73935SUlf Hansson return rc;
127521f1e2d4SVeerabhadrarao Badiganti msm_host->saved_tuning_phase = phase;
1276415b5a75SGeorgi Djakov dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
1277415b5a75SGeorgi Djakov mmc_hostname(mmc), phase);
1278415b5a75SGeorgi Djakov } else {
1279415b5a75SGeorgi Djakov if (--tuning_seq_cnt)
1280415b5a75SGeorgi Djakov goto retry;
1281415b5a75SGeorgi Djakov /* Tuning failed */
1282415b5a75SGeorgi Djakov dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
1283415b5a75SGeorgi Djakov mmc_hostname(mmc));
1284415b5a75SGeorgi Djakov rc = -EIO;
1285415b5a75SGeorgi Djakov }
1286415b5a75SGeorgi Djakov
1287ff06ce41SVenkat Gopalakrishnan if (!rc)
1288ff06ce41SVenkat Gopalakrishnan msm_host->tuning_done = true;
1289415b5a75SGeorgi Djakov return rc;
12900eb0d9f4SGeorgi Djakov }
12910eb0d9f4SGeorgi Djakov
1292db9bd163SRitesh Harjani /*
1293db9bd163SRitesh Harjani * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
129444bf2312SRitesh Harjani * This needs to be done for both tuning and enhanced_strobe mode.
1295db9bd163SRitesh Harjani * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1296db9bd163SRitesh Harjani * fixed feedback clock is used.
1297db9bd163SRitesh Harjani */
sdhci_msm_hs400(struct sdhci_host * host,struct mmc_ios * ios)1298db9bd163SRitesh Harjani static void sdhci_msm_hs400(struct sdhci_host *host, struct mmc_ios *ios)
1299db9bd163SRitesh Harjani {
1300db9bd163SRitesh Harjani struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1301db9bd163SRitesh Harjani struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1302db9bd163SRitesh Harjani int ret;
1303db9bd163SRitesh Harjani
1304db9bd163SRitesh Harjani if (host->clock > CORE_FREQ_100MHZ &&
130544bf2312SRitesh Harjani (msm_host->tuning_done || ios->enhanced_strobe) &&
130644bf2312SRitesh Harjani !msm_host->calibration_done) {
1307db9bd163SRitesh Harjani ret = sdhci_msm_hs400_dll_calibration(host);
1308db9bd163SRitesh Harjani if (!ret)
1309db9bd163SRitesh Harjani msm_host->calibration_done = true;
1310db9bd163SRitesh Harjani else
1311db9bd163SRitesh Harjani pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1312db9bd163SRitesh Harjani mmc_hostname(host->mmc), ret);
1313db9bd163SRitesh Harjani }
1314db9bd163SRitesh Harjani }
1315db9bd163SRitesh Harjani
sdhci_msm_set_uhs_signaling(struct sdhci_host * host,unsigned int uhs)1316ee320674SRitesh Harjani static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
1317ee320674SRitesh Harjani unsigned int uhs)
1318ee320674SRitesh Harjani {
1319ee320674SRitesh Harjani struct mmc_host *mmc = host->mmc;
1320ff06ce41SVenkat Gopalakrishnan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1321ff06ce41SVenkat Gopalakrishnan struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1322ee320674SRitesh Harjani u16 ctrl_2;
1323ff06ce41SVenkat Gopalakrishnan u32 config;
1324bc99266bSSayali Lokhande const struct sdhci_msm_offset *msm_offset =
1325bc99266bSSayali Lokhande msm_host->offset;
1326ee320674SRitesh Harjani
1327ee320674SRitesh Harjani ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1328ee320674SRitesh Harjani /* Select Bus Speed Mode for host */
1329ee320674SRitesh Harjani ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1330ee320674SRitesh Harjani switch (uhs) {
1331ee320674SRitesh Harjani case MMC_TIMING_UHS_SDR12:
1332ee320674SRitesh Harjani ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1333ee320674SRitesh Harjani break;
1334ee320674SRitesh Harjani case MMC_TIMING_UHS_SDR25:
1335ee320674SRitesh Harjani ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1336ee320674SRitesh Harjani break;
1337ee320674SRitesh Harjani case MMC_TIMING_UHS_SDR50:
1338ee320674SRitesh Harjani ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1339ee320674SRitesh Harjani break;
1340ff06ce41SVenkat Gopalakrishnan case MMC_TIMING_MMC_HS400:
1341ee320674SRitesh Harjani case MMC_TIMING_MMC_HS200:
1342ee320674SRitesh Harjani case MMC_TIMING_UHS_SDR104:
1343ee320674SRitesh Harjani ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1344ee320674SRitesh Harjani break;
1345ee320674SRitesh Harjani case MMC_TIMING_UHS_DDR50:
1346ee320674SRitesh Harjani case MMC_TIMING_MMC_DDR52:
1347ee320674SRitesh Harjani ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1348ee320674SRitesh Harjani break;
1349ee320674SRitesh Harjani }
1350ee320674SRitesh Harjani
1351ee320674SRitesh Harjani /*
1352ee320674SRitesh Harjani * When clock frequency is less than 100MHz, the feedback clock must be
1353ee320674SRitesh Harjani * provided and DLL must not be used so that tuning can be skipped. To
1354ee320674SRitesh Harjani * provide feedback clock, the mode selection can be any value less
1355ee320674SRitesh Harjani * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1356ee320674SRitesh Harjani */
1357ff06ce41SVenkat Gopalakrishnan if (host->clock <= CORE_FREQ_100MHZ) {
1358ff06ce41SVenkat Gopalakrishnan if (uhs == MMC_TIMING_MMC_HS400 ||
1359ee320674SRitesh Harjani uhs == MMC_TIMING_MMC_HS200 ||
1360ff06ce41SVenkat Gopalakrishnan uhs == MMC_TIMING_UHS_SDR104)
1361ee320674SRitesh Harjani ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1362ff06ce41SVenkat Gopalakrishnan /*
1363ff06ce41SVenkat Gopalakrishnan * DLL is not required for clock <= 100MHz
1364ff06ce41SVenkat Gopalakrishnan * Thus, make sure DLL it is disabled when not required
1365ff06ce41SVenkat Gopalakrishnan */
1366bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
1367bc99266bSSayali Lokhande msm_offset->core_dll_config);
1368ff06ce41SVenkat Gopalakrishnan config |= CORE_DLL_RST;
1369bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr +
1370bc99266bSSayali Lokhande msm_offset->core_dll_config);
1371ff06ce41SVenkat Gopalakrishnan
1372bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
1373bc99266bSSayali Lokhande msm_offset->core_dll_config);
1374ff06ce41SVenkat Gopalakrishnan config |= CORE_DLL_PDN;
1375bc99266bSSayali Lokhande writel_relaxed(config, host->ioaddr +
1376bc99266bSSayali Lokhande msm_offset->core_dll_config);
1377ff06ce41SVenkat Gopalakrishnan
1378ff06ce41SVenkat Gopalakrishnan /*
1379ff06ce41SVenkat Gopalakrishnan * The DLL needs to be restored and CDCLP533 recalibrated
1380ff06ce41SVenkat Gopalakrishnan * when the clock frequency is set back to 400MHz.
1381ff06ce41SVenkat Gopalakrishnan */
1382ff06ce41SVenkat Gopalakrishnan msm_host->calibration_done = false;
1383ff06ce41SVenkat Gopalakrishnan }
1384ee320674SRitesh Harjani
1385ee320674SRitesh Harjani dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1386ee320674SRitesh Harjani mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1387ee320674SRitesh Harjani sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1388cc392c58SRitesh Harjani
1389db9bd163SRitesh Harjani if (mmc->ios.timing == MMC_TIMING_MMC_HS400)
1390db9bd163SRitesh Harjani sdhci_msm_hs400(host, &mmc->ios);
1391ee320674SRitesh Harjani }
1392ee320674SRitesh Harjani
sdhci_msm_set_pincfg(struct sdhci_msm_host * msm_host,bool level)1393b5c833b7SVeerabhadrarao Badiganti static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level)
1394b5c833b7SVeerabhadrarao Badiganti {
1395b5c833b7SVeerabhadrarao Badiganti struct platform_device *pdev = msm_host->pdev;
1396b5c833b7SVeerabhadrarao Badiganti int ret;
1397b5c833b7SVeerabhadrarao Badiganti
1398b5c833b7SVeerabhadrarao Badiganti if (level)
1399b5c833b7SVeerabhadrarao Badiganti ret = pinctrl_pm_select_default_state(&pdev->dev);
1400b5c833b7SVeerabhadrarao Badiganti else
1401b5c833b7SVeerabhadrarao Badiganti ret = pinctrl_pm_select_sleep_state(&pdev->dev);
1402b5c833b7SVeerabhadrarao Badiganti
1403b5c833b7SVeerabhadrarao Badiganti return ret;
1404b5c833b7SVeerabhadrarao Badiganti }
1405b5c833b7SVeerabhadrarao Badiganti
sdhci_msm_set_vmmc(struct mmc_host * mmc)140692a21738SVeerabhadrarao Badiganti static int sdhci_msm_set_vmmc(struct mmc_host *mmc)
140792a21738SVeerabhadrarao Badiganti {
140892a21738SVeerabhadrarao Badiganti if (IS_ERR(mmc->supply.vmmc))
140992a21738SVeerabhadrarao Badiganti return 0;
141092a21738SVeerabhadrarao Badiganti
141192a21738SVeerabhadrarao Badiganti return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd);
141292a21738SVeerabhadrarao Badiganti }
141392a21738SVeerabhadrarao Badiganti
msm_toggle_vqmmc(struct sdhci_msm_host * msm_host,struct mmc_host * mmc,bool level)141492a21738SVeerabhadrarao Badiganti static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host,
141592a21738SVeerabhadrarao Badiganti struct mmc_host *mmc, bool level)
141692a21738SVeerabhadrarao Badiganti {
141792a21738SVeerabhadrarao Badiganti int ret;
141892a21738SVeerabhadrarao Badiganti struct mmc_ios ios;
141992a21738SVeerabhadrarao Badiganti
142092a21738SVeerabhadrarao Badiganti if (msm_host->vqmmc_enabled == level)
142192a21738SVeerabhadrarao Badiganti return 0;
142292a21738SVeerabhadrarao Badiganti
142392a21738SVeerabhadrarao Badiganti if (level) {
142492a21738SVeerabhadrarao Badiganti /* Set the IO voltage regulator to default voltage level */
142592a21738SVeerabhadrarao Badiganti if (msm_host->caps_0 & CORE_3_0V_SUPPORT)
142692a21738SVeerabhadrarao Badiganti ios.signal_voltage = MMC_SIGNAL_VOLTAGE_330;
142792a21738SVeerabhadrarao Badiganti else if (msm_host->caps_0 & CORE_1_8V_SUPPORT)
142892a21738SVeerabhadrarao Badiganti ios.signal_voltage = MMC_SIGNAL_VOLTAGE_180;
142992a21738SVeerabhadrarao Badiganti
143092a21738SVeerabhadrarao Badiganti if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
143192a21738SVeerabhadrarao Badiganti ret = mmc_regulator_set_vqmmc(mmc, &ios);
143292a21738SVeerabhadrarao Badiganti if (ret < 0) {
143392a21738SVeerabhadrarao Badiganti dev_err(mmc_dev(mmc), "%s: vqmmc set volgate failed: %d\n",
143492a21738SVeerabhadrarao Badiganti mmc_hostname(mmc), ret);
143592a21738SVeerabhadrarao Badiganti goto out;
143692a21738SVeerabhadrarao Badiganti }
143792a21738SVeerabhadrarao Badiganti }
143892a21738SVeerabhadrarao Badiganti ret = regulator_enable(mmc->supply.vqmmc);
143992a21738SVeerabhadrarao Badiganti } else {
144092a21738SVeerabhadrarao Badiganti ret = regulator_disable(mmc->supply.vqmmc);
144192a21738SVeerabhadrarao Badiganti }
144292a21738SVeerabhadrarao Badiganti
144392a21738SVeerabhadrarao Badiganti if (ret)
144492a21738SVeerabhadrarao Badiganti dev_err(mmc_dev(mmc), "%s: vqmm %sable failed: %d\n",
144592a21738SVeerabhadrarao Badiganti mmc_hostname(mmc), level ? "en":"dis", ret);
144692a21738SVeerabhadrarao Badiganti else
144792a21738SVeerabhadrarao Badiganti msm_host->vqmmc_enabled = level;
144892a21738SVeerabhadrarao Badiganti out:
144992a21738SVeerabhadrarao Badiganti return ret;
145092a21738SVeerabhadrarao Badiganti }
145192a21738SVeerabhadrarao Badiganti
msm_config_vqmmc_mode(struct sdhci_msm_host * msm_host,struct mmc_host * mmc,bool hpm)145292a21738SVeerabhadrarao Badiganti static int msm_config_vqmmc_mode(struct sdhci_msm_host *msm_host,
145392a21738SVeerabhadrarao Badiganti struct mmc_host *mmc, bool hpm)
145492a21738SVeerabhadrarao Badiganti {
145592a21738SVeerabhadrarao Badiganti int load, ret;
145692a21738SVeerabhadrarao Badiganti
145792a21738SVeerabhadrarao Badiganti load = hpm ? MMC_VQMMC_MAX_LOAD_UA : 0;
145892a21738SVeerabhadrarao Badiganti ret = regulator_set_load(mmc->supply.vqmmc, load);
145992a21738SVeerabhadrarao Badiganti if (ret)
146092a21738SVeerabhadrarao Badiganti dev_err(mmc_dev(mmc), "%s: vqmmc set load failed: %d\n",
146192a21738SVeerabhadrarao Badiganti mmc_hostname(mmc), ret);
146292a21738SVeerabhadrarao Badiganti return ret;
146392a21738SVeerabhadrarao Badiganti }
146492a21738SVeerabhadrarao Badiganti
sdhci_msm_set_vqmmc(struct sdhci_msm_host * msm_host,struct mmc_host * mmc,bool level)146592a21738SVeerabhadrarao Badiganti static int sdhci_msm_set_vqmmc(struct sdhci_msm_host *msm_host,
146692a21738SVeerabhadrarao Badiganti struct mmc_host *mmc, bool level)
146792a21738SVeerabhadrarao Badiganti {
146892a21738SVeerabhadrarao Badiganti int ret;
146992a21738SVeerabhadrarao Badiganti bool always_on;
147092a21738SVeerabhadrarao Badiganti
147192a21738SVeerabhadrarao Badiganti if (IS_ERR(mmc->supply.vqmmc) ||
147292a21738SVeerabhadrarao Badiganti (mmc->ios.power_mode == MMC_POWER_UNDEFINED))
147392a21738SVeerabhadrarao Badiganti return 0;
147492a21738SVeerabhadrarao Badiganti /*
147592a21738SVeerabhadrarao Badiganti * For eMMC don't turn off Vqmmc, Instead just configure it in LPM
147692a21738SVeerabhadrarao Badiganti * and HPM modes by setting the corresponding load.
147792a21738SVeerabhadrarao Badiganti *
147892a21738SVeerabhadrarao Badiganti * Till eMMC is initialized (i.e. always_on == 0), just turn on/off
147992a21738SVeerabhadrarao Badiganti * Vqmmc. Vqmmc gets turned off only if init fails and mmc_power_off
148092a21738SVeerabhadrarao Badiganti * gets invoked. Once eMMC is initialized (i.e. always_on == 1),
148192a21738SVeerabhadrarao Badiganti * Vqmmc should remain ON, So just set the load instead of turning it
148292a21738SVeerabhadrarao Badiganti * off/on.
148392a21738SVeerabhadrarao Badiganti */
148492a21738SVeerabhadrarao Badiganti always_on = !mmc_card_is_removable(mmc) &&
148592a21738SVeerabhadrarao Badiganti mmc->card && mmc_card_mmc(mmc->card);
148692a21738SVeerabhadrarao Badiganti
148792a21738SVeerabhadrarao Badiganti if (always_on)
148892a21738SVeerabhadrarao Badiganti ret = msm_config_vqmmc_mode(msm_host, mmc, level);
148992a21738SVeerabhadrarao Badiganti else
149092a21738SVeerabhadrarao Badiganti ret = msm_toggle_vqmmc(msm_host, mmc, level);
149192a21738SVeerabhadrarao Badiganti
149292a21738SVeerabhadrarao Badiganti return ret;
149392a21738SVeerabhadrarao Badiganti }
149492a21738SVeerabhadrarao Badiganti
sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host * msm_host)1495c0309b38SVijay Viswanath static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)
1496c0309b38SVijay Viswanath {
1497c0309b38SVijay Viswanath init_waitqueue_head(&msm_host->pwr_irq_wait);
1498c0309b38SVijay Viswanath }
1499c0309b38SVijay Viswanath
sdhci_msm_complete_pwr_irq_wait(struct sdhci_msm_host * msm_host)1500c0309b38SVijay Viswanath static inline void sdhci_msm_complete_pwr_irq_wait(
1501c0309b38SVijay Viswanath struct sdhci_msm_host *msm_host)
1502c0309b38SVijay Viswanath {
1503c0309b38SVijay Viswanath wake_up(&msm_host->pwr_irq_wait);
1504c0309b38SVijay Viswanath }
1505c0309b38SVijay Viswanath
1506c0309b38SVijay Viswanath /*
1507c0309b38SVijay Viswanath * sdhci_msm_check_power_status API should be called when registers writes
1508c0309b38SVijay Viswanath * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1509c0309b38SVijay Viswanath * To what state the register writes will change the IO lines should be passed
1510c0309b38SVijay Viswanath * as the argument req_type. This API will check whether the IO line's state
1511c0309b38SVijay Viswanath * is already the expected state and will wait for power irq only if
151227d8a86aSFlavio Suligoi * power irq is expected to be triggered based on the current IO line state
1513c0309b38SVijay Viswanath * and expected IO line state.
1514c0309b38SVijay Viswanath */
sdhci_msm_check_power_status(struct sdhci_host * host,u32 req_type)1515c0309b38SVijay Viswanath static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
1516c0309b38SVijay Viswanath {
1517c0309b38SVijay Viswanath struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1518c0309b38SVijay Viswanath struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1519c0309b38SVijay Viswanath bool done = false;
1520bc99266bSSayali Lokhande u32 val = SWITCHABLE_SIGNALING_VOLTAGE;
1521bc99266bSSayali Lokhande const struct sdhci_msm_offset *msm_offset =
1522bc99266bSSayali Lokhande msm_host->offset;
1523c0309b38SVijay Viswanath
1524c0309b38SVijay Viswanath pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1525c0309b38SVijay Viswanath mmc_hostname(host->mmc), __func__, req_type,
1526c0309b38SVijay Viswanath msm_host->curr_pwr_state, msm_host->curr_io_level);
1527c0309b38SVijay Viswanath
1528c0309b38SVijay Viswanath /*
152952884f8fSBjorn Andersson * The power interrupt will not be generated for signal voltage
153052884f8fSBjorn Andersson * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1531bc99266bSSayali Lokhande * Since sdhci-msm-v5, this bit has been removed and SW must consider
1532bc99266bSSayali Lokhande * it as always set.
153352884f8fSBjorn Andersson */
1534bc99266bSSayali Lokhande if (!msm_host->mci_removed)
1535bc99266bSSayali Lokhande val = msm_host_readl(msm_host, host,
1536bc99266bSSayali Lokhande msm_offset->core_generics);
153752884f8fSBjorn Andersson if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
153852884f8fSBjorn Andersson !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
153952884f8fSBjorn Andersson return;
154052884f8fSBjorn Andersson }
154152884f8fSBjorn Andersson
154252884f8fSBjorn Andersson /*
1543c0309b38SVijay Viswanath * The IRQ for request type IO High/LOW will be generated when -
1544c0309b38SVijay Viswanath * there is a state change in 1.8V enable bit (bit 3) of
1545c0309b38SVijay Viswanath * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1546c0309b38SVijay Viswanath * which indicates 3.3V IO voltage. So, when MMC core layer tries
1547c0309b38SVijay Viswanath * to set it to 3.3V before card detection happens, the
1548c0309b38SVijay Viswanath * IRQ doesn't get triggered as there is no state change in this bit.
1549c0309b38SVijay Viswanath * The driver already handles this case by changing the IO voltage
1550c0309b38SVijay Viswanath * level to high as part of controller power up sequence. Hence, check
1551c0309b38SVijay Viswanath * for host->pwr to handle a case where IO voltage high request is
1552c0309b38SVijay Viswanath * issued even before controller power up.
1553c0309b38SVijay Viswanath */
1554c0309b38SVijay Viswanath if ((req_type & REQ_IO_HIGH) && !host->pwr) {
1555c0309b38SVijay Viswanath pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1556c0309b38SVijay Viswanath mmc_hostname(host->mmc), req_type);
1557c0309b38SVijay Viswanath return;
1558c0309b38SVijay Viswanath }
1559c0309b38SVijay Viswanath if ((req_type & msm_host->curr_pwr_state) ||
1560c0309b38SVijay Viswanath (req_type & msm_host->curr_io_level))
1561c0309b38SVijay Viswanath done = true;
1562c0309b38SVijay Viswanath /*
1563c0309b38SVijay Viswanath * This is needed here to handle cases where register writes will
1564c0309b38SVijay Viswanath * not change the current bus state or io level of the controller.
1565c0309b38SVijay Viswanath * In this case, no power irq will be triggerred and we should
1566c0309b38SVijay Viswanath * not wait.
1567c0309b38SVijay Viswanath */
1568c0309b38SVijay Viswanath if (!done) {
1569c0309b38SVijay Viswanath if (!wait_event_timeout(msm_host->pwr_irq_wait,
1570c0309b38SVijay Viswanath msm_host->pwr_irq_flag,
1571c0309b38SVijay Viswanath msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))
15729ccfa817SArnd Bergmann dev_warn(&msm_host->pdev->dev,
15739ccfa817SArnd Bergmann "%s: pwr_irq for req: (%d) timed out\n",
1574c0309b38SVijay Viswanath mmc_hostname(host->mmc), req_type);
1575c0309b38SVijay Viswanath }
1576c0309b38SVijay Viswanath pr_debug("%s: %s: request %d done\n", mmc_hostname(host->mmc),
1577c0309b38SVijay Viswanath __func__, req_type);
1578c0309b38SVijay Viswanath }
1579c0309b38SVijay Viswanath
sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host * host)1580401b2d06SSahitya Tummala static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)
1581401b2d06SSahitya Tummala {
1582401b2d06SSahitya Tummala struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1583401b2d06SSahitya Tummala struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1584bc99266bSSayali Lokhande const struct sdhci_msm_offset *msm_offset =
1585bc99266bSSayali Lokhande msm_host->offset;
1586401b2d06SSahitya Tummala
1587401b2d06SSahitya Tummala pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1588401b2d06SSahitya Tummala mmc_hostname(host->mmc),
1589bc99266bSSayali Lokhande msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status),
1590bc99266bSSayali Lokhande msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask),
1591bc99266bSSayali Lokhande msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl));
1592401b2d06SSahitya Tummala }
1593401b2d06SSahitya Tummala
sdhci_msm_handle_pwr_irq(struct sdhci_host * host,int irq)1594401b2d06SSahitya Tummala static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)
1595ad81d387SGeorgi Djakov {
1596ad81d387SGeorgi Djakov struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1597ad81d387SGeorgi Djakov struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
159892a21738SVeerabhadrarao Badiganti struct mmc_host *mmc = host->mmc;
1599ad81d387SGeorgi Djakov u32 irq_status, irq_ack = 0;
160092a21738SVeerabhadrarao Badiganti int retry = 10, ret;
1601ac06fba1SVijay Viswanath u32 pwr_state = 0, io_level = 0;
16025c132323SVijay Viswanath u32 config;
1603bc99266bSSayali Lokhande const struct sdhci_msm_offset *msm_offset = msm_host->offset;
1604ad81d387SGeorgi Djakov
1605bc99266bSSayali Lokhande irq_status = msm_host_readl(msm_host, host,
1606bc99266bSSayali Lokhande msm_offset->core_pwrctl_status);
1607ad81d387SGeorgi Djakov irq_status &= INT_MASK;
1608ad81d387SGeorgi Djakov
1609bc99266bSSayali Lokhande msm_host_writel(msm_host, irq_status, host,
1610bc99266bSSayali Lokhande msm_offset->core_pwrctl_clear);
1611ad81d387SGeorgi Djakov
1612401b2d06SSahitya Tummala /*
1613401b2d06SSahitya Tummala * There is a rare HW scenario where the first clear pulse could be
1614401b2d06SSahitya Tummala * lost when actual reset and clear/read of status register is
1615401b2d06SSahitya Tummala * happening at a time. Hence, retry for at least 10 times to make
1616401b2d06SSahitya Tummala * sure status register is cleared. Otherwise, this will result in
1617401b2d06SSahitya Tummala * a spurious power IRQ resulting in system instability.
1618401b2d06SSahitya Tummala */
1619bc99266bSSayali Lokhande while (irq_status & msm_host_readl(msm_host, host,
1620bc99266bSSayali Lokhande msm_offset->core_pwrctl_status)) {
1621401b2d06SSahitya Tummala if (retry == 0) {
1622401b2d06SSahitya Tummala pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1623401b2d06SSahitya Tummala mmc_hostname(host->mmc), irq_status);
1624401b2d06SSahitya Tummala sdhci_msm_dump_pwr_ctrl_regs(host);
1625401b2d06SSahitya Tummala WARN_ON(1);
1626401b2d06SSahitya Tummala break;
1627401b2d06SSahitya Tummala }
1628bc99266bSSayali Lokhande msm_host_writel(msm_host, irq_status, host,
1629bc99266bSSayali Lokhande msm_offset->core_pwrctl_clear);
1630401b2d06SSahitya Tummala retry--;
1631401b2d06SSahitya Tummala udelay(10);
1632401b2d06SSahitya Tummala }
1633401b2d06SSahitya Tummala
1634c0309b38SVijay Viswanath /* Handle BUS ON/OFF*/
1635c0309b38SVijay Viswanath if (irq_status & CORE_PWRCTL_BUS_ON) {
1636c0309b38SVijay Viswanath pwr_state = REQ_BUS_ON;
1637c0309b38SVijay Viswanath io_level = REQ_IO_HIGH;
1638c0309b38SVijay Viswanath }
1639c0309b38SVijay Viswanath if (irq_status & CORE_PWRCTL_BUS_OFF) {
1640c0309b38SVijay Viswanath pwr_state = REQ_BUS_OFF;
1641c0309b38SVijay Viswanath io_level = REQ_IO_LOW;
164292a21738SVeerabhadrarao Badiganti }
164392a21738SVeerabhadrarao Badiganti
164492a21738SVeerabhadrarao Badiganti if (pwr_state) {
164592a21738SVeerabhadrarao Badiganti ret = sdhci_msm_set_vmmc(mmc);
164692a21738SVeerabhadrarao Badiganti if (!ret)
164792a21738SVeerabhadrarao Badiganti ret = sdhci_msm_set_vqmmc(msm_host, mmc,
164892a21738SVeerabhadrarao Badiganti pwr_state & REQ_BUS_ON);
164992a21738SVeerabhadrarao Badiganti if (!ret)
1650b5c833b7SVeerabhadrarao Badiganti ret = sdhci_msm_set_pincfg(msm_host,
1651b5c833b7SVeerabhadrarao Badiganti pwr_state & REQ_BUS_ON);
1652b5c833b7SVeerabhadrarao Badiganti if (!ret)
1653c0309b38SVijay Viswanath irq_ack |= CORE_PWRCTL_BUS_SUCCESS;
165492a21738SVeerabhadrarao Badiganti else
165592a21738SVeerabhadrarao Badiganti irq_ack |= CORE_PWRCTL_BUS_FAIL;
1656c0309b38SVijay Viswanath }
165792a21738SVeerabhadrarao Badiganti
1658c0309b38SVijay Viswanath /* Handle IO LOW/HIGH */
165992a21738SVeerabhadrarao Badiganti if (irq_status & CORE_PWRCTL_IO_LOW)
1660c0309b38SVijay Viswanath io_level = REQ_IO_LOW;
166192a21738SVeerabhadrarao Badiganti
166292a21738SVeerabhadrarao Badiganti if (irq_status & CORE_PWRCTL_IO_HIGH)
1663c0309b38SVijay Viswanath io_level = REQ_IO_HIGH;
166492a21738SVeerabhadrarao Badiganti
166592a21738SVeerabhadrarao Badiganti if (io_level)
1666c0309b38SVijay Viswanath irq_ack |= CORE_PWRCTL_IO_SUCCESS;
166792a21738SVeerabhadrarao Badiganti
166892a21738SVeerabhadrarao Badiganti if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) {
166992a21738SVeerabhadrarao Badiganti ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios);
167092a21738SVeerabhadrarao Badiganti if (ret < 0) {
167192a21738SVeerabhadrarao Badiganti dev_err(mmc_dev(mmc), "%s: IO_level setting failed(%d). signal_voltage: %d, vdd: %d irq_status: 0x%08x\n",
167292a21738SVeerabhadrarao Badiganti mmc_hostname(mmc), ret,
167392a21738SVeerabhadrarao Badiganti mmc->ios.signal_voltage, mmc->ios.vdd,
167492a21738SVeerabhadrarao Badiganti irq_status);
167592a21738SVeerabhadrarao Badiganti irq_ack |= CORE_PWRCTL_IO_FAIL;
167692a21738SVeerabhadrarao Badiganti }
1677c0309b38SVijay Viswanath }
1678ad81d387SGeorgi Djakov
1679ad81d387SGeorgi Djakov /*
1680ad81d387SGeorgi Djakov * The driver has to acknowledge the interrupt, switch voltages and
1681ad81d387SGeorgi Djakov * report back if it succeded or not to this register. The voltage
1682ad81d387SGeorgi Djakov * switches are handled by the sdhci core, so just report success.
1683ad81d387SGeorgi Djakov */
1684bc99266bSSayali Lokhande msm_host_writel(msm_host, irq_ack, host,
1685bc99266bSSayali Lokhande msm_offset->core_pwrctl_ctl);
1686401b2d06SSahitya Tummala
16875c132323SVijay Viswanath /*
16885c132323SVijay Viswanath * If we don't have info regarding the voltage levels supported by
16895c132323SVijay Viswanath * regulators, don't change the IO PAD PWR SWITCH.
16905c132323SVijay Viswanath */
16915c132323SVijay Viswanath if (msm_host->caps_0 & CORE_VOLT_SUPPORT) {
16925c132323SVijay Viswanath u32 new_config;
16935c132323SVijay Viswanath /*
16945c132323SVijay Viswanath * We should unset IO PAD PWR switch only if the register write
16955c132323SVijay Viswanath * can set IO lines high and the regulator also switches to 3 V.
16965c132323SVijay Viswanath * Else, we should keep the IO PAD PWR switch set.
16975c132323SVijay Viswanath * This is applicable to certain targets where eMMC vccq supply
16985c132323SVijay Viswanath * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
16995c132323SVijay Viswanath * IO PAD PWR switch must be kept set to reflect actual
17005c132323SVijay Viswanath * regulator voltage. This way, during initialization of
17015c132323SVijay Viswanath * controllers with only 1.8V, we will set the IO PAD bit
17025c132323SVijay Viswanath * without waiting for a REQ_IO_LOW.
17035c132323SVijay Viswanath */
1704bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
1705bc99266bSSayali Lokhande msm_offset->core_vendor_spec);
17065c132323SVijay Viswanath new_config = config;
17075c132323SVijay Viswanath
17085c132323SVijay Viswanath if ((io_level & REQ_IO_HIGH) &&
17095c132323SVijay Viswanath (msm_host->caps_0 & CORE_3_0V_SUPPORT))
17105c132323SVijay Viswanath new_config &= ~CORE_IO_PAD_PWR_SWITCH;
17115c132323SVijay Viswanath else if ((io_level & REQ_IO_LOW) ||
17125c132323SVijay Viswanath (msm_host->caps_0 & CORE_1_8V_SUPPORT))
17135c132323SVijay Viswanath new_config |= CORE_IO_PAD_PWR_SWITCH;
17145c132323SVijay Viswanath
17155c132323SVijay Viswanath if (config ^ new_config)
1716bc99266bSSayali Lokhande writel_relaxed(new_config, host->ioaddr +
1717bc99266bSSayali Lokhande msm_offset->core_vendor_spec);
17185c132323SVijay Viswanath }
17195c132323SVijay Viswanath
1720c0309b38SVijay Viswanath if (pwr_state)
1721c0309b38SVijay Viswanath msm_host->curr_pwr_state = pwr_state;
1722c0309b38SVijay Viswanath if (io_level)
1723c0309b38SVijay Viswanath msm_host->curr_io_level = io_level;
1724c0309b38SVijay Viswanath
172592a21738SVeerabhadrarao Badiganti dev_dbg(mmc_dev(mmc), "%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1726401b2d06SSahitya Tummala mmc_hostname(msm_host->mmc), __func__, irq, irq_status,
1727401b2d06SSahitya Tummala irq_ack);
1728ad81d387SGeorgi Djakov }
1729ad81d387SGeorgi Djakov
sdhci_msm_pwr_irq(int irq,void * data)1730ad81d387SGeorgi Djakov static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)
1731ad81d387SGeorgi Djakov {
1732ad81d387SGeorgi Djakov struct sdhci_host *host = (struct sdhci_host *)data;
1733c0309b38SVijay Viswanath struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1734c0309b38SVijay Viswanath struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1735ad81d387SGeorgi Djakov
1736401b2d06SSahitya Tummala sdhci_msm_handle_pwr_irq(host, irq);
1737c0309b38SVijay Viswanath msm_host->pwr_irq_flag = 1;
1738c0309b38SVijay Viswanath sdhci_msm_complete_pwr_irq_wait(msm_host);
1739c0309b38SVijay Viswanath
1740ad81d387SGeorgi Djakov
1741ad81d387SGeorgi Djakov return IRQ_HANDLED;
1742ad81d387SGeorgi Djakov }
1743ad81d387SGeorgi Djakov
sdhci_msm_get_max_clock(struct sdhci_host * host)174480031bdeSRitesh Harjani static unsigned int sdhci_msm_get_max_clock(struct sdhci_host *host)
174580031bdeSRitesh Harjani {
174680031bdeSRitesh Harjani struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
174780031bdeSRitesh Harjani struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1748e4bf91f6SBjorn Andersson struct clk *core_clk = msm_host->bulk_clks[0].clk;
174980031bdeSRitesh Harjani
1750e4bf91f6SBjorn Andersson return clk_round_rate(core_clk, ULONG_MAX);
175180031bdeSRitesh Harjani }
175280031bdeSRitesh Harjani
sdhci_msm_get_min_clock(struct sdhci_host * host)175380031bdeSRitesh Harjani static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
175480031bdeSRitesh Harjani {
175580031bdeSRitesh Harjani return SDHCI_MSM_MIN_CLOCK;
175680031bdeSRitesh Harjani }
175780031bdeSRitesh Harjani
1758abf4633aSLee Jones /*
1759edc609fdSRitesh Harjani * __sdhci_msm_set_clock - sdhci_msm clock control.
1760edc609fdSRitesh Harjani *
1761edc609fdSRitesh Harjani * Description:
1762edc609fdSRitesh Harjani * MSM controller does not use internal divider and
1763edc609fdSRitesh Harjani * instead directly control the GCC clock as per
1764edc609fdSRitesh Harjani * HW recommendation.
1765edc609fdSRitesh Harjani **/
__sdhci_msm_set_clock(struct sdhci_host * host,unsigned int clock)176630de038dSMasahiro Yamada static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1767edc609fdSRitesh Harjani {
1768edc609fdSRitesh Harjani u16 clk;
1769edc609fdSRitesh Harjani
1770edc609fdSRitesh Harjani sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1771edc609fdSRitesh Harjani
1772edc609fdSRitesh Harjani if (clock == 0)
1773edc609fdSRitesh Harjani return;
1774edc609fdSRitesh Harjani
1775edc609fdSRitesh Harjani /*
1776edc609fdSRitesh Harjani * MSM controller do not use clock divider.
1777edc609fdSRitesh Harjani * Thus read SDHCI_CLOCK_CONTROL and only enable
1778edc609fdSRitesh Harjani * clock with no divider value programmed.
1779edc609fdSRitesh Harjani */
1780edc609fdSRitesh Harjani clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1781edc609fdSRitesh Harjani sdhci_enable_clk(host, clk);
1782edc609fdSRitesh Harjani }
1783edc609fdSRitesh Harjani
1784edc609fdSRitesh Harjani /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
sdhci_msm_set_clock(struct sdhci_host * host,unsigned int clock)1785edc609fdSRitesh Harjani static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1786edc609fdSRitesh Harjani {
1787edc609fdSRitesh Harjani struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1788edc609fdSRitesh Harjani struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1789edc609fdSRitesh Harjani
1790edc609fdSRitesh Harjani if (!clock) {
1791f16c8fd4SDouglas Anderson host->mmc->actual_clock = msm_host->clk_rate = 0;
1792edc609fdSRitesh Harjani goto out;
1793edc609fdSRitesh Harjani }
1794edc609fdSRitesh Harjani
1795b54aaa8aSRitesh Harjani sdhci_msm_hc_select_mode(host);
1796edc609fdSRitesh Harjani
17970fb8a3d4SRitesh Harjani msm_set_clock_rate_for_bus_mode(host, clock);
1798edc609fdSRitesh Harjani out:
1799edc609fdSRitesh Harjani __sdhci_msm_set_clock(host, clock);
1800edc609fdSRitesh Harjani }
1801edc609fdSRitesh Harjani
180287a8df0dSRitesh Harjani /*****************************************************************************\
180387a8df0dSRitesh Harjani * *
1804c93767cfSEric Biggers * Inline Crypto Engine (ICE) support *
1805c93767cfSEric Biggers * *
1806c93767cfSEric Biggers \*****************************************************************************/
1807c93767cfSEric Biggers
1808c93767cfSEric Biggers #ifdef CONFIG_MMC_CRYPTO
1809c93767cfSEric Biggers
sdhci_msm_ice_init(struct sdhci_msm_host * msm_host,struct cqhci_host * cq_host)1810c93767cfSEric Biggers static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
1811c93767cfSEric Biggers struct cqhci_host *cq_host)
1812c93767cfSEric Biggers {
1813c93767cfSEric Biggers struct mmc_host *mmc = msm_host->mmc;
1814c93767cfSEric Biggers struct device *dev = mmc_dev(mmc);
1815c7eed31eSAbel Vesa struct qcom_ice *ice;
1816c93767cfSEric Biggers
1817c93767cfSEric Biggers if (!(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
1818c93767cfSEric Biggers return 0;
1819c93767cfSEric Biggers
1820c7eed31eSAbel Vesa ice = of_qcom_ice_get(dev);
1821c7eed31eSAbel Vesa if (ice == ERR_PTR(-EOPNOTSUPP)) {
1822c93767cfSEric Biggers dev_warn(dev, "Disabling inline encryption support\n");
1823c7eed31eSAbel Vesa ice = NULL;
1824c7eed31eSAbel Vesa }
1825c7eed31eSAbel Vesa
1826c7eed31eSAbel Vesa if (IS_ERR_OR_NULL(ice))
1827c7eed31eSAbel Vesa return PTR_ERR_OR_ZERO(ice);
1828c7eed31eSAbel Vesa
1829c7eed31eSAbel Vesa msm_host->ice = ice;
1830c7eed31eSAbel Vesa mmc->caps2 |= MMC_CAP2_CRYPTO;
1831c7eed31eSAbel Vesa
1832c93767cfSEric Biggers return 0;
1833c93767cfSEric Biggers }
1834c93767cfSEric Biggers
sdhci_msm_ice_enable(struct sdhci_msm_host * msm_host)1835c93767cfSEric Biggers static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
1836c93767cfSEric Biggers {
1837c7eed31eSAbel Vesa if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
1838c7eed31eSAbel Vesa qcom_ice_enable(msm_host->ice);
1839c93767cfSEric Biggers }
1840c93767cfSEric Biggers
sdhci_msm_ice_resume(struct sdhci_msm_host * msm_host)1841c7eed31eSAbel Vesa static __maybe_unused int sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
1842c93767cfSEric Biggers {
1843c7eed31eSAbel Vesa if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
1844c7eed31eSAbel Vesa return qcom_ice_resume(msm_host->ice);
1845c7eed31eSAbel Vesa
1846c93767cfSEric Biggers return 0;
1847c7eed31eSAbel Vesa }
1848c7eed31eSAbel Vesa
sdhci_msm_ice_suspend(struct sdhci_msm_host * msm_host)1849c7eed31eSAbel Vesa static __maybe_unused int sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
1850c7eed31eSAbel Vesa {
1851c7eed31eSAbel Vesa if (msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)
1852c7eed31eSAbel Vesa return qcom_ice_suspend(msm_host->ice);
1853c7eed31eSAbel Vesa
1854c7eed31eSAbel Vesa return 0;
1855c93767cfSEric Biggers }
1856c93767cfSEric Biggers
1857c93767cfSEric Biggers /*
1858c93767cfSEric Biggers * Program a key into a QC ICE keyslot, or evict a keyslot. QC ICE requires
1859c93767cfSEric Biggers * vendor-specific SCM calls for this; it doesn't support the standard way.
1860c93767cfSEric Biggers */
sdhci_msm_program_key(struct cqhci_host * cq_host,const union cqhci_crypto_cfg_entry * cfg,int slot)1861c93767cfSEric Biggers static int sdhci_msm_program_key(struct cqhci_host *cq_host,
1862c93767cfSEric Biggers const union cqhci_crypto_cfg_entry *cfg,
1863c93767cfSEric Biggers int slot)
1864c93767cfSEric Biggers {
1865c7eed31eSAbel Vesa struct sdhci_host *host = mmc_priv(cq_host->mmc);
1866c7eed31eSAbel Vesa struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1867c7eed31eSAbel Vesa struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1868c93767cfSEric Biggers union cqhci_crypto_cap_entry cap;
1869c93767cfSEric Biggers
1870c93767cfSEric Biggers /* Only AES-256-XTS has been tested so far. */
1871c93767cfSEric Biggers cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx];
1872c93767cfSEric Biggers if (cap.algorithm_id != CQHCI_CRYPTO_ALG_AES_XTS ||
1873c7eed31eSAbel Vesa cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256)
1874c93767cfSEric Biggers return -EINVAL;
1875c7eed31eSAbel Vesa
1876c7eed31eSAbel Vesa if (cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE)
1877c7eed31eSAbel Vesa return qcom_ice_program_key(msm_host->ice,
1878c7eed31eSAbel Vesa QCOM_ICE_CRYPTO_ALG_AES_XTS,
1879c7eed31eSAbel Vesa QCOM_ICE_CRYPTO_KEY_SIZE_256,
1880c7eed31eSAbel Vesa cfg->crypto_key,
1881c7eed31eSAbel Vesa cfg->data_unit_size, slot);
1882c7eed31eSAbel Vesa else
1883c7eed31eSAbel Vesa return qcom_ice_evict_key(msm_host->ice, slot);
1884c93767cfSEric Biggers }
1885c93767cfSEric Biggers
1886c93767cfSEric Biggers #else /* CONFIG_MMC_CRYPTO */
1887c93767cfSEric Biggers
sdhci_msm_ice_init(struct sdhci_msm_host * msm_host,struct cqhci_host * cq_host)1888c93767cfSEric Biggers static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host,
1889c93767cfSEric Biggers struct cqhci_host *cq_host)
1890c93767cfSEric Biggers {
1891c93767cfSEric Biggers return 0;
1892c93767cfSEric Biggers }
1893c93767cfSEric Biggers
sdhci_msm_ice_enable(struct sdhci_msm_host * msm_host)1894c93767cfSEric Biggers static inline void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host)
1895c93767cfSEric Biggers {
1896c93767cfSEric Biggers }
1897c93767cfSEric Biggers
1898c7eed31eSAbel Vesa static inline __maybe_unused int
sdhci_msm_ice_resume(struct sdhci_msm_host * msm_host)1899c93767cfSEric Biggers sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host)
1900c93767cfSEric Biggers {
1901c93767cfSEric Biggers return 0;
1902c93767cfSEric Biggers }
1903c7eed31eSAbel Vesa
1904c7eed31eSAbel Vesa static inline __maybe_unused int
sdhci_msm_ice_suspend(struct sdhci_msm_host * msm_host)1905c7eed31eSAbel Vesa sdhci_msm_ice_suspend(struct sdhci_msm_host *msm_host)
1906c7eed31eSAbel Vesa {
1907c7eed31eSAbel Vesa return 0;
1908c7eed31eSAbel Vesa }
1909c93767cfSEric Biggers #endif /* !CONFIG_MMC_CRYPTO */
1910c93767cfSEric Biggers
1911c93767cfSEric Biggers /*****************************************************************************\
1912c93767cfSEric Biggers * *
191387a8df0dSRitesh Harjani * MSM Command Queue Engine (CQE) *
191487a8df0dSRitesh Harjani * *
191587a8df0dSRitesh Harjani \*****************************************************************************/
191687a8df0dSRitesh Harjani
sdhci_msm_cqe_irq(struct sdhci_host * host,u32 intmask)191787a8df0dSRitesh Harjani static u32 sdhci_msm_cqe_irq(struct sdhci_host *host, u32 intmask)
191887a8df0dSRitesh Harjani {
191987a8df0dSRitesh Harjani int cmd_error = 0;
192087a8df0dSRitesh Harjani int data_error = 0;
192187a8df0dSRitesh Harjani
192287a8df0dSRitesh Harjani if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
192387a8df0dSRitesh Harjani return intmask;
192487a8df0dSRitesh Harjani
192587a8df0dSRitesh Harjani cqhci_irq(host->mmc, intmask, cmd_error, data_error);
192687a8df0dSRitesh Harjani return 0;
192787a8df0dSRitesh Harjani }
192887a8df0dSRitesh Harjani
sdhci_msm_cqe_enable(struct mmc_host * mmc)1929c93767cfSEric Biggers static void sdhci_msm_cqe_enable(struct mmc_host *mmc)
1930c93767cfSEric Biggers {
1931c93767cfSEric Biggers struct sdhci_host *host = mmc_priv(mmc);
1932c93767cfSEric Biggers struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1933c93767cfSEric Biggers struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
1934c93767cfSEric Biggers
1935c93767cfSEric Biggers sdhci_cqe_enable(mmc);
1936c93767cfSEric Biggers sdhci_msm_ice_enable(msm_host);
1937c93767cfSEric Biggers }
1938c93767cfSEric Biggers
sdhci_msm_cqe_disable(struct mmc_host * mmc,bool recovery)19399051db38SStephen Boyd static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
194087a8df0dSRitesh Harjani {
194187a8df0dSRitesh Harjani struct sdhci_host *host = mmc_priv(mmc);
194287a8df0dSRitesh Harjani unsigned long flags;
194387a8df0dSRitesh Harjani u32 ctrl;
194487a8df0dSRitesh Harjani
194587a8df0dSRitesh Harjani /*
194687a8df0dSRitesh Harjani * When CQE is halted, the legacy SDHCI path operates only
194787a8df0dSRitesh Harjani * on 16-byte descriptors in 64bit mode.
194887a8df0dSRitesh Harjani */
194987a8df0dSRitesh Harjani if (host->flags & SDHCI_USE_64_BIT_DMA)
195087a8df0dSRitesh Harjani host->desc_sz = 16;
195187a8df0dSRitesh Harjani
195287a8df0dSRitesh Harjani spin_lock_irqsave(&host->lock, flags);
195387a8df0dSRitesh Harjani
195487a8df0dSRitesh Harjani /*
195587a8df0dSRitesh Harjani * During CQE command transfers, command complete bit gets latched.
195687a8df0dSRitesh Harjani * So s/w should clear command complete interrupt status when CQE is
195787a8df0dSRitesh Harjani * either halted or disabled. Otherwise unexpected SDCHI legacy
195887a8df0dSRitesh Harjani * interrupt gets triggered when CQE is halted/disabled.
195987a8df0dSRitesh Harjani */
196087a8df0dSRitesh Harjani ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);
196187a8df0dSRitesh Harjani ctrl |= SDHCI_INT_RESPONSE;
196287a8df0dSRitesh Harjani sdhci_writel(host, ctrl, SDHCI_INT_ENABLE);
196387a8df0dSRitesh Harjani sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
196487a8df0dSRitesh Harjani
196587a8df0dSRitesh Harjani spin_unlock_irqrestore(&host->lock, flags);
196687a8df0dSRitesh Harjani
196787a8df0dSRitesh Harjani sdhci_cqe_disable(mmc, recovery);
196887a8df0dSRitesh Harjani }
196987a8df0dSRitesh Harjani
sdhci_msm_set_timeout(struct sdhci_host * host,struct mmc_command * cmd)197067b13f3eSShaik Sajida Bhanu static void sdhci_msm_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
197167b13f3eSShaik Sajida Bhanu {
197267b13f3eSShaik Sajida Bhanu u32 count, start = 15;
197367b13f3eSShaik Sajida Bhanu
197467b13f3eSShaik Sajida Bhanu __sdhci_set_timeout(host, cmd);
197567b13f3eSShaik Sajida Bhanu count = sdhci_readb(host, SDHCI_TIMEOUT_CONTROL);
197667b13f3eSShaik Sajida Bhanu /*
197767b13f3eSShaik Sajida Bhanu * Update software timeout value if its value is less than hardware data
197867b13f3eSShaik Sajida Bhanu * timeout value. Qcom SoC hardware data timeout value was calculated
197967b13f3eSShaik Sajida Bhanu * using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock.
198067b13f3eSShaik Sajida Bhanu */
198167b13f3eSShaik Sajida Bhanu if (cmd && cmd->data && host->clock > 400000 &&
198267b13f3eSShaik Sajida Bhanu host->clock <= 50000000 &&
198367b13f3eSShaik Sajida Bhanu ((1 << (count + start)) > (10 * host->clock)))
198467b13f3eSShaik Sajida Bhanu host->data_timeout = 22LL * NSEC_PER_SEC;
198567b13f3eSShaik Sajida Bhanu }
198667b13f3eSShaik Sajida Bhanu
198787a8df0dSRitesh Harjani static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
1988c93767cfSEric Biggers .enable = sdhci_msm_cqe_enable,
198987a8df0dSRitesh Harjani .disable = sdhci_msm_cqe_disable,
1990c93767cfSEric Biggers #ifdef CONFIG_MMC_CRYPTO
1991c93767cfSEric Biggers .program_key = sdhci_msm_program_key,
1992c93767cfSEric Biggers #endif
199387a8df0dSRitesh Harjani };
199487a8df0dSRitesh Harjani
sdhci_msm_cqe_add_host(struct sdhci_host * host,struct platform_device * pdev)199587a8df0dSRitesh Harjani static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
199687a8df0dSRitesh Harjani struct platform_device *pdev)
199787a8df0dSRitesh Harjani {
199887a8df0dSRitesh Harjani struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
199987a8df0dSRitesh Harjani struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
200087a8df0dSRitesh Harjani struct cqhci_host *cq_host;
200187a8df0dSRitesh Harjani bool dma64;
200287a8df0dSRitesh Harjani u32 cqcfg;
200387a8df0dSRitesh Harjani int ret;
200487a8df0dSRitesh Harjani
200587a8df0dSRitesh Harjani /*
200687a8df0dSRitesh Harjani * When CQE is halted, SDHC operates only on 16byte ADMA descriptors.
200787a8df0dSRitesh Harjani * So ensure ADMA table is allocated for 16byte descriptors.
200887a8df0dSRitesh Harjani */
200987a8df0dSRitesh Harjani if (host->caps & SDHCI_CAN_64BIT)
201087a8df0dSRitesh Harjani host->alloc_desc_sz = 16;
201187a8df0dSRitesh Harjani
201287a8df0dSRitesh Harjani ret = sdhci_setup_host(host);
201387a8df0dSRitesh Harjani if (ret)
201487a8df0dSRitesh Harjani return ret;
201587a8df0dSRitesh Harjani
201687a8df0dSRitesh Harjani cq_host = cqhci_pltfm_init(pdev);
201787a8df0dSRitesh Harjani if (IS_ERR(cq_host)) {
201887a8df0dSRitesh Harjani ret = PTR_ERR(cq_host);
201987a8df0dSRitesh Harjani dev_err(&pdev->dev, "cqhci-pltfm init: failed: %d\n", ret);
202087a8df0dSRitesh Harjani goto cleanup;
202187a8df0dSRitesh Harjani }
202287a8df0dSRitesh Harjani
202387a8df0dSRitesh Harjani msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
202487a8df0dSRitesh Harjani cq_host->ops = &sdhci_msm_cqhci_ops;
202587a8df0dSRitesh Harjani
202687a8df0dSRitesh Harjani dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
202787a8df0dSRitesh Harjani
2028c93767cfSEric Biggers ret = sdhci_msm_ice_init(msm_host, cq_host);
2029c93767cfSEric Biggers if (ret)
2030c93767cfSEric Biggers goto cleanup;
2031c93767cfSEric Biggers
203287a8df0dSRitesh Harjani ret = cqhci_init(cq_host, host->mmc, dma64);
203387a8df0dSRitesh Harjani if (ret) {
203487a8df0dSRitesh Harjani dev_err(&pdev->dev, "%s: CQE init: failed (%d)\n",
203587a8df0dSRitesh Harjani mmc_hostname(host->mmc), ret);
203687a8df0dSRitesh Harjani goto cleanup;
203787a8df0dSRitesh Harjani }
203887a8df0dSRitesh Harjani
203987a8df0dSRitesh Harjani /* Disable cqe reset due to cqe enable signal */
204087a8df0dSRitesh Harjani cqcfg = cqhci_readl(cq_host, CQHCI_VENDOR_CFG1);
204187a8df0dSRitesh Harjani cqcfg |= CQHCI_VENDOR_DIS_RST_ON_CQ_EN;
204287a8df0dSRitesh Harjani cqhci_writel(cq_host, cqcfg, CQHCI_VENDOR_CFG1);
204387a8df0dSRitesh Harjani
204487a8df0dSRitesh Harjani /*
204587a8df0dSRitesh Harjani * SDHC expects 12byte ADMA descriptors till CQE is enabled.
204687a8df0dSRitesh Harjani * So limit desc_sz to 12 so that the data commands that are sent
204787a8df0dSRitesh Harjani * during card initialization (before CQE gets enabled) would
204887a8df0dSRitesh Harjani * get executed without any issues.
204987a8df0dSRitesh Harjani */
205087a8df0dSRitesh Harjani if (host->flags & SDHCI_USE_64_BIT_DMA)
205187a8df0dSRitesh Harjani host->desc_sz = 12;
205287a8df0dSRitesh Harjani
205387a8df0dSRitesh Harjani ret = __sdhci_add_host(host);
205487a8df0dSRitesh Harjani if (ret)
205587a8df0dSRitesh Harjani goto cleanup;
205687a8df0dSRitesh Harjani
205787a8df0dSRitesh Harjani dev_info(&pdev->dev, "%s: CQE init: success\n",
205887a8df0dSRitesh Harjani mmc_hostname(host->mmc));
205987a8df0dSRitesh Harjani return ret;
206087a8df0dSRitesh Harjani
206187a8df0dSRitesh Harjani cleanup:
206287a8df0dSRitesh Harjani sdhci_cleanup_host(host);
206387a8df0dSRitesh Harjani return ret;
206487a8df0dSRitesh Harjani }
206587a8df0dSRitesh Harjani
2066c0309b38SVijay Viswanath /*
2067c0309b38SVijay Viswanath * Platform specific register write functions. This is so that, if any
2068c0309b38SVijay Viswanath * register write needs to be followed up by platform specific actions,
2069c0309b38SVijay Viswanath * they can be added here. These functions can go to sleep when writes
2070c0309b38SVijay Viswanath * to certain registers are done.
2071c0309b38SVijay Viswanath * These functions are relying on sdhci_set_ios not using spinlock.
2072c0309b38SVijay Viswanath */
__sdhci_msm_check_write(struct sdhci_host * host,u16 val,int reg)2073c0309b38SVijay Viswanath static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)
2074c0309b38SVijay Viswanath {
2075c0309b38SVijay Viswanath struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
2076c0309b38SVijay Viswanath struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
2077c0309b38SVijay Viswanath u32 req_type = 0;
2078c0309b38SVijay Viswanath
2079c0309b38SVijay Viswanath switch (reg) {
2080c0309b38SVijay Viswanath case SDHCI_HOST_CONTROL2:
2081c0309b38SVijay Viswanath req_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :
2082c0309b38SVijay Viswanath REQ_IO_HIGH;
2083c0309b38SVijay Viswanath break;
2084c0309b38SVijay Viswanath case SDHCI_SOFTWARE_RESET:
2085c0309b38SVijay Viswanath if (host->pwr && (val & SDHCI_RESET_ALL))
2086c0309b38SVijay Viswanath req_type = REQ_BUS_OFF;
2087c0309b38SVijay Viswanath break;
2088c0309b38SVijay Viswanath case SDHCI_POWER_CONTROL:
2089c0309b38SVijay Viswanath req_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;
2090c0309b38SVijay Viswanath break;
2091a89e7bcbSLoic Poulain case SDHCI_TRANSFER_MODE:
2092a89e7bcbSLoic Poulain msm_host->transfer_mode = val;
2093a89e7bcbSLoic Poulain break;
2094a89e7bcbSLoic Poulain case SDHCI_COMMAND:
2095a89e7bcbSLoic Poulain if (!msm_host->use_cdr)
2096a89e7bcbSLoic Poulain break;
2097a89e7bcbSLoic Poulain if ((msm_host->transfer_mode & SDHCI_TRNS_READ) &&
2098b98e7e8dSChanWoo Lee !mmc_op_tuning(SDHCI_GET_CMD(val)))
2099a89e7bcbSLoic Poulain sdhci_msm_set_cdr(host, true);
2100a89e7bcbSLoic Poulain else
2101a89e7bcbSLoic Poulain sdhci_msm_set_cdr(host, false);
2102a89e7bcbSLoic Poulain break;
2103c0309b38SVijay Viswanath }
2104c0309b38SVijay Viswanath
2105c0309b38SVijay Viswanath if (req_type) {
2106c0309b38SVijay Viswanath msm_host->pwr_irq_flag = 0;
2107c0309b38SVijay Viswanath /*
2108c0309b38SVijay Viswanath * Since this register write may trigger a power irq, ensure
2109c0309b38SVijay Viswanath * all previous register writes are complete by this point.
2110c0309b38SVijay Viswanath */
2111c0309b38SVijay Viswanath mb();
2112c0309b38SVijay Viswanath }
2113c0309b38SVijay Viswanath return req_type;
2114c0309b38SVijay Viswanath }
2115c0309b38SVijay Viswanath
2116c0309b38SVijay Viswanath /* This function may sleep*/
sdhci_msm_writew(struct sdhci_host * host,u16 val,int reg)2117c0309b38SVijay Viswanath static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)
2118c0309b38SVijay Viswanath {
2119c0309b38SVijay Viswanath u32 req_type = 0;
2120c0309b38SVijay Viswanath
2121c0309b38SVijay Viswanath req_type = __sdhci_msm_check_write(host, val, reg);
2122c0309b38SVijay Viswanath writew_relaxed(val, host->ioaddr + reg);
2123c0309b38SVijay Viswanath
2124c0309b38SVijay Viswanath if (req_type)
2125c0309b38SVijay Viswanath sdhci_msm_check_power_status(host, req_type);
2126c0309b38SVijay Viswanath }
2127c0309b38SVijay Viswanath
2128c0309b38SVijay Viswanath /* This function may sleep*/
sdhci_msm_writeb(struct sdhci_host * host,u8 val,int reg)2129c0309b38SVijay Viswanath static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)
2130c0309b38SVijay Viswanath {
2131c0309b38SVijay Viswanath u32 req_type = 0;
2132c0309b38SVijay Viswanath
2133c0309b38SVijay Viswanath req_type = __sdhci_msm_check_write(host, val, reg);
2134c0309b38SVijay Viswanath
2135c0309b38SVijay Viswanath writeb_relaxed(val, host->ioaddr + reg);
2136c0309b38SVijay Viswanath
2137c0309b38SVijay Viswanath if (req_type)
2138c0309b38SVijay Viswanath sdhci_msm_check_power_status(host, req_type);
2139c0309b38SVijay Viswanath }
2140c0309b38SVijay Viswanath
sdhci_msm_set_regulator_caps(struct sdhci_msm_host * msm_host)2141ac06fba1SVijay Viswanath static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host)
2142ac06fba1SVijay Viswanath {
2143ac06fba1SVijay Viswanath struct mmc_host *mmc = msm_host->mmc;
2144ac06fba1SVijay Viswanath struct regulator *supply = mmc->supply.vqmmc;
21455c132323SVijay Viswanath u32 caps = 0, config;
21465c132323SVijay Viswanath struct sdhci_host *host = mmc_priv(mmc);
2147bc99266bSSayali Lokhande const struct sdhci_msm_offset *msm_offset = msm_host->offset;
2148ac06fba1SVijay Viswanath
2149ac06fba1SVijay Viswanath if (!IS_ERR(mmc->supply.vqmmc)) {
2150ac06fba1SVijay Viswanath if (regulator_is_supported_voltage(supply, 1700000, 1950000))
2151ac06fba1SVijay Viswanath caps |= CORE_1_8V_SUPPORT;
2152ac06fba1SVijay Viswanath if (regulator_is_supported_voltage(supply, 2700000, 3600000))
2153ac06fba1SVijay Viswanath caps |= CORE_3_0V_SUPPORT;
2154ac06fba1SVijay Viswanath
2155ac06fba1SVijay Viswanath if (!caps)
2156ac06fba1SVijay Viswanath pr_warn("%s: 1.8/3V not supported for vqmmc\n",
2157ac06fba1SVijay Viswanath mmc_hostname(mmc));
2158ac06fba1SVijay Viswanath }
2159ac06fba1SVijay Viswanath
21605c132323SVijay Viswanath if (caps) {
21615c132323SVijay Viswanath /*
21625c132323SVijay Viswanath * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
21635c132323SVijay Viswanath * bit can be used as required later on.
21645c132323SVijay Viswanath */
21655c132323SVijay Viswanath u32 io_level = msm_host->curr_io_level;
21665c132323SVijay Viswanath
2167bc99266bSSayali Lokhande config = readl_relaxed(host->ioaddr +
2168bc99266bSSayali Lokhande msm_offset->core_vendor_spec);
21695c132323SVijay Viswanath config |= CORE_IO_PAD_PWR_SWITCH_EN;
21705c132323SVijay Viswanath
21715c132323SVijay Viswanath if ((io_level & REQ_IO_HIGH) && (caps & CORE_3_0V_SUPPORT))
21725c132323SVijay Viswanath config &= ~CORE_IO_PAD_PWR_SWITCH;
21735c132323SVijay Viswanath else if ((io_level & REQ_IO_LOW) || (caps & CORE_1_8V_SUPPORT))
21745c132323SVijay Viswanath config |= CORE_IO_PAD_PWR_SWITCH;
21755c132323SVijay Viswanath
2176bc99266bSSayali Lokhande writel_relaxed(config,
2177bc99266bSSayali Lokhande host->ioaddr + msm_offset->core_vendor_spec);
21785c132323SVijay Viswanath }
2179ac06fba1SVijay Viswanath msm_host->caps_0 |= caps;
2180ac06fba1SVijay Viswanath pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc), caps);
2181ac06fba1SVijay Viswanath }
2182ac06fba1SVijay Viswanath
sdhci_msm_register_vreg(struct sdhci_msm_host * msm_host)218392a21738SVeerabhadrarao Badiganti static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host)
218492a21738SVeerabhadrarao Badiganti {
218592a21738SVeerabhadrarao Badiganti int ret;
218692a21738SVeerabhadrarao Badiganti
218792a21738SVeerabhadrarao Badiganti ret = mmc_regulator_get_supply(msm_host->mmc);
218892a21738SVeerabhadrarao Badiganti if (ret)
218992a21738SVeerabhadrarao Badiganti return ret;
219092a21738SVeerabhadrarao Badiganti
219192a21738SVeerabhadrarao Badiganti sdhci_msm_set_regulator_caps(msm_host);
219292a21738SVeerabhadrarao Badiganti
219392a21738SVeerabhadrarao Badiganti return 0;
219492a21738SVeerabhadrarao Badiganti }
219592a21738SVeerabhadrarao Badiganti
sdhci_msm_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)219692a21738SVeerabhadrarao Badiganti static int sdhci_msm_start_signal_voltage_switch(struct mmc_host *mmc,
219792a21738SVeerabhadrarao Badiganti struct mmc_ios *ios)
219892a21738SVeerabhadrarao Badiganti {
219992a21738SVeerabhadrarao Badiganti struct sdhci_host *host = mmc_priv(mmc);
220092a21738SVeerabhadrarao Badiganti u16 ctrl, status;
220192a21738SVeerabhadrarao Badiganti
220292a21738SVeerabhadrarao Badiganti /*
220392a21738SVeerabhadrarao Badiganti * Signal Voltage Switching is only applicable for Host Controllers
220492a21738SVeerabhadrarao Badiganti * v3.00 and above.
220592a21738SVeerabhadrarao Badiganti */
220692a21738SVeerabhadrarao Badiganti if (host->version < SDHCI_SPEC_300)
220792a21738SVeerabhadrarao Badiganti return 0;
220892a21738SVeerabhadrarao Badiganti
220992a21738SVeerabhadrarao Badiganti ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
221092a21738SVeerabhadrarao Badiganti
221192a21738SVeerabhadrarao Badiganti switch (ios->signal_voltage) {
221292a21738SVeerabhadrarao Badiganti case MMC_SIGNAL_VOLTAGE_330:
221392a21738SVeerabhadrarao Badiganti if (!(host->flags & SDHCI_SIGNALING_330))
221492a21738SVeerabhadrarao Badiganti return -EINVAL;
221592a21738SVeerabhadrarao Badiganti
221692a21738SVeerabhadrarao Badiganti /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
221792a21738SVeerabhadrarao Badiganti ctrl &= ~SDHCI_CTRL_VDD_180;
221892a21738SVeerabhadrarao Badiganti break;
221992a21738SVeerabhadrarao Badiganti case MMC_SIGNAL_VOLTAGE_180:
222092a21738SVeerabhadrarao Badiganti if (!(host->flags & SDHCI_SIGNALING_180))
222192a21738SVeerabhadrarao Badiganti return -EINVAL;
222292a21738SVeerabhadrarao Badiganti
222392a21738SVeerabhadrarao Badiganti /* Enable 1.8V Signal Enable in the Host Control2 register */
222492a21738SVeerabhadrarao Badiganti ctrl |= SDHCI_CTRL_VDD_180;
222592a21738SVeerabhadrarao Badiganti break;
222692a21738SVeerabhadrarao Badiganti
222792a21738SVeerabhadrarao Badiganti default:
222892a21738SVeerabhadrarao Badiganti return -EINVAL;
222992a21738SVeerabhadrarao Badiganti }
223092a21738SVeerabhadrarao Badiganti
223192a21738SVeerabhadrarao Badiganti sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
223292a21738SVeerabhadrarao Badiganti
223392a21738SVeerabhadrarao Badiganti /* Wait for 5ms */
223492a21738SVeerabhadrarao Badiganti usleep_range(5000, 5500);
223592a21738SVeerabhadrarao Badiganti
223692a21738SVeerabhadrarao Badiganti /* regulator output should be stable within 5 ms */
223792a21738SVeerabhadrarao Badiganti status = ctrl & SDHCI_CTRL_VDD_180;
223892a21738SVeerabhadrarao Badiganti ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
223992a21738SVeerabhadrarao Badiganti if ((ctrl & SDHCI_CTRL_VDD_180) == status)
224092a21738SVeerabhadrarao Badiganti return 0;
224192a21738SVeerabhadrarao Badiganti
224292a21738SVeerabhadrarao Badiganti dev_warn(mmc_dev(mmc), "%s: Regulator output did not became stable\n",
224392a21738SVeerabhadrarao Badiganti mmc_hostname(mmc));
224492a21738SVeerabhadrarao Badiganti
224592a21738SVeerabhadrarao Badiganti return -EAGAIN;
224692a21738SVeerabhadrarao Badiganti }
224792a21738SVeerabhadrarao Badiganti
224816d18d89SSarthak Garg #define DRIVER_NAME "sdhci_msm"
224916d18d89SSarthak Garg #define SDHCI_MSM_DUMP(f, x...) \
225016d18d89SSarthak Garg pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
225116d18d89SSarthak Garg
sdhci_msm_dump_vendor_regs(struct sdhci_host * host)225253e888d1SHulk Robot static void sdhci_msm_dump_vendor_regs(struct sdhci_host *host)
225316d18d89SSarthak Garg {
225416d18d89SSarthak Garg struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
225516d18d89SSarthak Garg struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
225616d18d89SSarthak Garg const struct sdhci_msm_offset *msm_offset = msm_host->offset;
225716d18d89SSarthak Garg
225816d18d89SSarthak Garg SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n");
225916d18d89SSarthak Garg
226016d18d89SSarthak Garg SDHCI_MSM_DUMP(
226116d18d89SSarthak Garg "DLL sts: 0x%08x | DLL cfg: 0x%08x | DLL cfg2: 0x%08x\n",
226216d18d89SSarthak Garg readl_relaxed(host->ioaddr + msm_offset->core_dll_status),
226316d18d89SSarthak Garg readl_relaxed(host->ioaddr + msm_offset->core_dll_config),
226416d18d89SSarthak Garg readl_relaxed(host->ioaddr + msm_offset->core_dll_config_2));
226516d18d89SSarthak Garg SDHCI_MSM_DUMP(
226616d18d89SSarthak Garg "DLL cfg3: 0x%08x | DLL usr ctl: 0x%08x | DDR cfg: 0x%08x\n",
226716d18d89SSarthak Garg readl_relaxed(host->ioaddr + msm_offset->core_dll_config_3),
226816d18d89SSarthak Garg readl_relaxed(host->ioaddr + msm_offset->core_dll_usr_ctl),
226916d18d89SSarthak Garg readl_relaxed(host->ioaddr + msm_offset->core_ddr_config));
227016d18d89SSarthak Garg SDHCI_MSM_DUMP(
227116d18d89SSarthak Garg "Vndr func: 0x%08x | Vndr func2 : 0x%08x Vndr func3: 0x%08x\n",
227216d18d89SSarthak Garg readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec),
227316d18d89SSarthak Garg readl_relaxed(host->ioaddr +
227416d18d89SSarthak Garg msm_offset->core_vendor_spec_func2),
227516d18d89SSarthak Garg readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3));
227616d18d89SSarthak Garg }
227716d18d89SSarthak Garg
22786ed4bb43SVijay Viswanath static const struct sdhci_msm_variant_ops mci_var_ops = {
22796ed4bb43SVijay Viswanath .msm_readl_relaxed = sdhci_msm_mci_variant_readl_relaxed,
22806ed4bb43SVijay Viswanath .msm_writel_relaxed = sdhci_msm_mci_variant_writel_relaxed,
22816ed4bb43SVijay Viswanath };
22826ed4bb43SVijay Viswanath
22836ed4bb43SVijay Viswanath static const struct sdhci_msm_variant_ops v5_var_ops = {
22846ed4bb43SVijay Viswanath .msm_readl_relaxed = sdhci_msm_v5_variant_readl_relaxed,
22856ed4bb43SVijay Viswanath .msm_writel_relaxed = sdhci_msm_v5_variant_writel_relaxed,
22866ed4bb43SVijay Viswanath };
22876ed4bb43SVijay Viswanath
22886ed4bb43SVijay Viswanath static const struct sdhci_msm_variant_info sdhci_msm_mci_var = {
22896ed4bb43SVijay Viswanath .var_ops = &mci_var_ops,
22906ed4bb43SVijay Viswanath .offset = &sdhci_msm_mci_offset,
22916ed4bb43SVijay Viswanath };
22926ed4bb43SVijay Viswanath
22936ed4bb43SVijay Viswanath static const struct sdhci_msm_variant_info sdhci_msm_v5_var = {
22946ed4bb43SVijay Viswanath .mci_removed = true,
22956ed4bb43SVijay Viswanath .var_ops = &v5_var_ops,
22966ed4bb43SVijay Viswanath .offset = &sdhci_msm_v5_offset,
22976ed4bb43SVijay Viswanath };
22986ed4bb43SVijay Viswanath
229921f1e2d4SVeerabhadrarao Badiganti static const struct sdhci_msm_variant_info sdm845_sdhci_var = {
230021f1e2d4SVeerabhadrarao Badiganti .mci_removed = true,
230121f1e2d4SVeerabhadrarao Badiganti .restore_dll_config = true,
230221f1e2d4SVeerabhadrarao Badiganti .var_ops = &v5_var_ops,
230321f1e2d4SVeerabhadrarao Badiganti .offset = &sdhci_msm_v5_offset,
230421f1e2d4SVeerabhadrarao Badiganti };
230521f1e2d4SVeerabhadrarao Badiganti
23060eb0d9f4SGeorgi Djakov static const struct of_device_id sdhci_msm_dt_match[] = {
2307b05cd716SKrzysztof Kozlowski /*
2308b05cd716SKrzysztof Kozlowski * Do not add new variants to the driver which are compatible with
2309b05cd716SKrzysztof Kozlowski * generic ones, unless they need customization.
2310b05cd716SKrzysztof Kozlowski */
2311bc99266bSSayali Lokhande {.compatible = "qcom,sdhci-msm-v4", .data = &sdhci_msm_mci_var},
2312bc99266bSSayali Lokhande {.compatible = "qcom,sdhci-msm-v5", .data = &sdhci_msm_v5_var},
23134de95950SRichard Acayan {.compatible = "qcom,sdm670-sdhci", .data = &sdm845_sdhci_var},
231421f1e2d4SVeerabhadrarao Badiganti {.compatible = "qcom,sdm845-sdhci", .data = &sdm845_sdhci_var},
23154dac686bSVeerabhadrarao Badiganti {.compatible = "qcom,sc7180-sdhci", .data = &sdm845_sdhci_var},
23160eb0d9f4SGeorgi Djakov {},
23170eb0d9f4SGeorgi Djakov };
23180eb0d9f4SGeorgi Djakov
23190eb0d9f4SGeorgi Djakov MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
23200eb0d9f4SGeorgi Djakov
2321a50396a4SJisheng Zhang static const struct sdhci_ops sdhci_msm_ops = {
232208b863bbSBrian Norris .reset = sdhci_and_cqhci_reset,
2323edc609fdSRitesh Harjani .set_clock = sdhci_msm_set_clock,
232480031bdeSRitesh Harjani .get_min_clock = sdhci_msm_get_min_clock,
232580031bdeSRitesh Harjani .get_max_clock = sdhci_msm_get_max_clock,
2326ed1761d7SStephen Boyd .set_bus_width = sdhci_set_bus_width,
2327ee320674SRitesh Harjani .set_uhs_signaling = sdhci_msm_set_uhs_signaling,
2328c0309b38SVijay Viswanath .write_w = sdhci_msm_writew,
2329c0309b38SVijay Viswanath .write_b = sdhci_msm_writeb,
233087a8df0dSRitesh Harjani .irq = sdhci_msm_cqe_irq,
233116d18d89SSarthak Garg .dump_vendor_regs = sdhci_msm_dump_vendor_regs,
233292a21738SVeerabhadrarao Badiganti .set_power = sdhci_set_power_noreg,
233367b13f3eSShaik Sajida Bhanu .set_timeout = sdhci_msm_set_timeout,
23340eb0d9f4SGeorgi Djakov };
23350eb0d9f4SGeorgi Djakov
2336a50396a4SJisheng Zhang static const struct sdhci_pltfm_data sdhci_msm_pdata = {
2337a50396a4SJisheng Zhang .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
2338a0e31428SRitesh Harjani SDHCI_QUIRK_SINGLE_POWER_WRITE |
2339d863cb03SVeerabhadrarao Badiganti SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
2340d863cb03SVeerabhadrarao Badiganti SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
2341d863cb03SVeerabhadrarao Badiganti
2342a0e31428SRitesh Harjani .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
2343a50396a4SJisheng Zhang .ops = &sdhci_msm_ops,
2344a50396a4SJisheng Zhang };
2345a50396a4SJisheng Zhang
sdhci_msm_get_of_property(struct platform_device * pdev,struct sdhci_host * host)23461dfbe3ffSSarthak Garg static inline void sdhci_msm_get_of_property(struct platform_device *pdev,
23471dfbe3ffSSarthak Garg struct sdhci_host *host)
23481dfbe3ffSSarthak Garg {
23491dfbe3ffSSarthak Garg struct device_node *node = pdev->dev.of_node;
23501dfbe3ffSSarthak Garg struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
23511dfbe3ffSSarthak Garg struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
23521dfbe3ffSSarthak Garg
23531dfbe3ffSSarthak Garg if (of_property_read_u32(node, "qcom,ddr-config",
23541dfbe3ffSSarthak Garg &msm_host->ddr_config))
23551dfbe3ffSSarthak Garg msm_host->ddr_config = DDR_CONFIG_POR_VAL;
235603591160SSarthak Garg
235703591160SSarthak Garg of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config);
2358e6f9e590SStephan Gerhold
2359e6f9e590SStephan Gerhold if (of_device_is_compatible(node, "qcom,msm8916-sdhci"))
2360e6f9e590SStephan Gerhold host->quirks2 |= SDHCI_QUIRK2_BROKEN_64_BIT_DMA;
23611dfbe3ffSSarthak Garg }
23621dfbe3ffSSarthak Garg
sdhci_msm_gcc_reset(struct device * dev,struct sdhci_host * host)23633e5a8e84SShaik Sajida Bhanu static int sdhci_msm_gcc_reset(struct device *dev, struct sdhci_host *host)
23643e5a8e84SShaik Sajida Bhanu {
23653e5a8e84SShaik Sajida Bhanu struct reset_control *reset;
23663e5a8e84SShaik Sajida Bhanu int ret = 0;
23673e5a8e84SShaik Sajida Bhanu
23683e5a8e84SShaik Sajida Bhanu reset = reset_control_get_optional_exclusive(dev, NULL);
23693e5a8e84SShaik Sajida Bhanu if (IS_ERR(reset))
23703e5a8e84SShaik Sajida Bhanu return dev_err_probe(dev, PTR_ERR(reset),
23713e5a8e84SShaik Sajida Bhanu "unable to acquire core_reset\n");
23723e5a8e84SShaik Sajida Bhanu
23733e5a8e84SShaik Sajida Bhanu if (!reset)
23743e5a8e84SShaik Sajida Bhanu return ret;
23753e5a8e84SShaik Sajida Bhanu
23763e5a8e84SShaik Sajida Bhanu ret = reset_control_assert(reset);
23773e5a8e84SShaik Sajida Bhanu if (ret) {
23783e5a8e84SShaik Sajida Bhanu reset_control_put(reset);
23793e5a8e84SShaik Sajida Bhanu return dev_err_probe(dev, ret, "core_reset assert failed\n");
23803e5a8e84SShaik Sajida Bhanu }
23813e5a8e84SShaik Sajida Bhanu
23823e5a8e84SShaik Sajida Bhanu /*
23833e5a8e84SShaik Sajida Bhanu * The hardware requirement for delay between assert/deassert
23843e5a8e84SShaik Sajida Bhanu * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
23853e5a8e84SShaik Sajida Bhanu * ~125us (4/32768). To be on the safe side add 200us delay.
23863e5a8e84SShaik Sajida Bhanu */
23873e5a8e84SShaik Sajida Bhanu usleep_range(200, 210);
23883e5a8e84SShaik Sajida Bhanu
23893e5a8e84SShaik Sajida Bhanu ret = reset_control_deassert(reset);
23903e5a8e84SShaik Sajida Bhanu if (ret) {
23913e5a8e84SShaik Sajida Bhanu reset_control_put(reset);
23923e5a8e84SShaik Sajida Bhanu return dev_err_probe(dev, ret, "core_reset deassert failed\n");
23933e5a8e84SShaik Sajida Bhanu }
23943e5a8e84SShaik Sajida Bhanu
23953e5a8e84SShaik Sajida Bhanu usleep_range(200, 210);
23963e5a8e84SShaik Sajida Bhanu reset_control_put(reset);
23973e5a8e84SShaik Sajida Bhanu
23983e5a8e84SShaik Sajida Bhanu return ret;
23993e5a8e84SShaik Sajida Bhanu }
24001dfbe3ffSSarthak Garg
sdhci_msm_probe(struct platform_device * pdev)24010eb0d9f4SGeorgi Djakov static int sdhci_msm_probe(struct platform_device *pdev)
24020eb0d9f4SGeorgi Djakov {
24030eb0d9f4SGeorgi Djakov struct sdhci_host *host;
24040eb0d9f4SGeorgi Djakov struct sdhci_pltfm_host *pltfm_host;
24050eb0d9f4SGeorgi Djakov struct sdhci_msm_host *msm_host;
2406e4bf91f6SBjorn Andersson struct clk *clk;
24070eb0d9f4SGeorgi Djakov int ret;
24083a3ad3e9SGeorgi Djakov u16 host_version, core_minor;
240929301f40SRitesh Harjani u32 core_version, config;
24103a3ad3e9SGeorgi Djakov u8 core_major;
2411bc99266bSSayali Lokhande const struct sdhci_msm_offset *msm_offset;
2412bc99266bSSayali Lokhande const struct sdhci_msm_variant_info *var_info;
241387a8df0dSRitesh Harjani struct device_node *node = pdev->dev.of_node;
24140eb0d9f4SGeorgi Djakov
24156f699531SJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
24160eb0d9f4SGeorgi Djakov if (IS_ERR(host))
24170eb0d9f4SGeorgi Djakov return PTR_ERR(host);
24180eb0d9f4SGeorgi Djakov
24192a641e53SSrinivas Kandagatla host->sdma_boundary = 0;
24200eb0d9f4SGeorgi Djakov pltfm_host = sdhci_priv(host);
24216f699531SJisheng Zhang msm_host = sdhci_pltfm_priv(pltfm_host);
24220eb0d9f4SGeorgi Djakov msm_host->mmc = host->mmc;
24230eb0d9f4SGeorgi Djakov msm_host->pdev = pdev;
24240eb0d9f4SGeorgi Djakov
24250eb0d9f4SGeorgi Djakov ret = mmc_of_parse(host->mmc);
24260eb0d9f4SGeorgi Djakov if (ret)
24270eb0d9f4SGeorgi Djakov goto pltfm_free;
24280eb0d9f4SGeorgi Djakov
2429bc99266bSSayali Lokhande /*
2430bc99266bSSayali Lokhande * Based on the compatible string, load the required msm host info from
2431bc99266bSSayali Lokhande * the data associated with the version info.
2432bc99266bSSayali Lokhande */
2433bc99266bSSayali Lokhande var_info = of_device_get_match_data(&pdev->dev);
2434bc99266bSSayali Lokhande
2435bc99266bSSayali Lokhande msm_host->mci_removed = var_info->mci_removed;
243621f1e2d4SVeerabhadrarao Badiganti msm_host->restore_dll_config = var_info->restore_dll_config;
2437bc99266bSSayali Lokhande msm_host->var_ops = var_info->var_ops;
2438bc99266bSSayali Lokhande msm_host->offset = var_info->offset;
2439bc99266bSSayali Lokhande
2440bc99266bSSayali Lokhande msm_offset = msm_host->offset;
2441bc99266bSSayali Lokhande
24420eb0d9f4SGeorgi Djakov sdhci_get_of_property(pdev);
24431dfbe3ffSSarthak Garg sdhci_msm_get_of_property(pdev, host);
24440eb0d9f4SGeorgi Djakov
2445abf270e5SRitesh Harjani msm_host->saved_tuning_phase = INVALID_TUNING_PHASE;
2446abf270e5SRitesh Harjani
24473e5a8e84SShaik Sajida Bhanu ret = sdhci_msm_gcc_reset(&pdev->dev, host);
24483e5a8e84SShaik Sajida Bhanu if (ret)
24493e5a8e84SShaik Sajida Bhanu goto pltfm_free;
24503e5a8e84SShaik Sajida Bhanu
24510eb0d9f4SGeorgi Djakov /* Setup SDCC bus voter clock. */
24520eb0d9f4SGeorgi Djakov msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
24530eb0d9f4SGeorgi Djakov if (!IS_ERR(msm_host->bus_clk)) {
24540eb0d9f4SGeorgi Djakov /* Vote for max. clk rate for max. performance */
24550eb0d9f4SGeorgi Djakov ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
24560eb0d9f4SGeorgi Djakov if (ret)
24570eb0d9f4SGeorgi Djakov goto pltfm_free;
24580eb0d9f4SGeorgi Djakov ret = clk_prepare_enable(msm_host->bus_clk);
24590eb0d9f4SGeorgi Djakov if (ret)
24600eb0d9f4SGeorgi Djakov goto pltfm_free;
24610eb0d9f4SGeorgi Djakov }
24620eb0d9f4SGeorgi Djakov
24630eb0d9f4SGeorgi Djakov /* Setup main peripheral bus clock */
2464e4bf91f6SBjorn Andersson clk = devm_clk_get(&pdev->dev, "iface");
2465e4bf91f6SBjorn Andersson if (IS_ERR(clk)) {
2466e4bf91f6SBjorn Andersson ret = PTR_ERR(clk);
24672801b95eSColin Ian King dev_err(&pdev->dev, "Peripheral clk setup failed (%d)\n", ret);
24680eb0d9f4SGeorgi Djakov goto bus_clk_disable;
24690eb0d9f4SGeorgi Djakov }
2470e4bf91f6SBjorn Andersson msm_host->bulk_clks[1].clk = clk;
24710eb0d9f4SGeorgi Djakov
24720eb0d9f4SGeorgi Djakov /* Setup SDC MMC clock */
2473e4bf91f6SBjorn Andersson clk = devm_clk_get(&pdev->dev, "core");
2474e4bf91f6SBjorn Andersson if (IS_ERR(clk)) {
2475e4bf91f6SBjorn Andersson ret = PTR_ERR(clk);
24760eb0d9f4SGeorgi Djakov dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
2477e4bf91f6SBjorn Andersson goto bus_clk_disable;
24780eb0d9f4SGeorgi Djakov }
2479e4bf91f6SBjorn Andersson msm_host->bulk_clks[0].clk = clk;
2480e4bf91f6SBjorn Andersson
2481b4fc8278SPradeep P V K /* Check for optional interconnect paths */
2482b4fc8278SPradeep P V K ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL);
2483b4fc8278SPradeep P V K if (ret)
2484b4fc8278SPradeep P V K goto bus_clk_disable;
2485b4fc8278SPradeep P V K
2486411281d2SYangtao Li ret = devm_pm_opp_set_clkname(&pdev->dev, "core");
2487411281d2SYangtao Li if (ret)
24880472f8d3SRajendra Nayak goto bus_clk_disable;
24890472f8d3SRajendra Nayak
24900472f8d3SRajendra Nayak /* OPP table is optional */
2491411281d2SYangtao Li ret = devm_pm_opp_of_add_table(&pdev->dev);
249291ca244bSViresh Kumar if (ret && ret != -ENODEV) {
2493c2b613d0SRajendra Nayak dev_err(&pdev->dev, "Invalid OPP table in Device tree\n");
2494411281d2SYangtao Li goto bus_clk_disable;
2495c2b613d0SRajendra Nayak }
24960472f8d3SRajendra Nayak
2497e4bf91f6SBjorn Andersson /* Vote for maximum clock rate for maximum performance */
24980472f8d3SRajendra Nayak ret = dev_pm_opp_set_rate(&pdev->dev, INT_MAX);
2499e4bf91f6SBjorn Andersson if (ret)
2500e4bf91f6SBjorn Andersson dev_warn(&pdev->dev, "core clock boost failed\n");
2501e4bf91f6SBjorn Andersson
25024946b3afSBjorn Andersson clk = devm_clk_get(&pdev->dev, "cal");
25034946b3afSBjorn Andersson if (IS_ERR(clk))
25044946b3afSBjorn Andersson clk = NULL;
25054946b3afSBjorn Andersson msm_host->bulk_clks[2].clk = clk;
25064946b3afSBjorn Andersson
25074946b3afSBjorn Andersson clk = devm_clk_get(&pdev->dev, "sleep");
25084946b3afSBjorn Andersson if (IS_ERR(clk))
25094946b3afSBjorn Andersson clk = NULL;
25104946b3afSBjorn Andersson msm_host->bulk_clks[3].clk = clk;
25114946b3afSBjorn Andersson
2512e4bf91f6SBjorn Andersson ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2513e4bf91f6SBjorn Andersson msm_host->bulk_clks);
2514e4bf91f6SBjorn Andersson if (ret)
2515411281d2SYangtao Li goto bus_clk_disable;
25160eb0d9f4SGeorgi Djakov
251783736352SVenkat Gopalakrishnan /*
251883736352SVenkat Gopalakrishnan * xo clock is needed for FLL feature of cm_dll.
251983736352SVenkat Gopalakrishnan * In case if xo clock is not mentioned in DT, warn and proceed.
252083736352SVenkat Gopalakrishnan */
252183736352SVenkat Gopalakrishnan msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo");
252283736352SVenkat Gopalakrishnan if (IS_ERR(msm_host->xo_clk)) {
252383736352SVenkat Gopalakrishnan ret = PTR_ERR(msm_host->xo_clk);
252483736352SVenkat Gopalakrishnan dev_warn(&pdev->dev, "TCXO clk not present (%d)\n", ret);
252583736352SVenkat Gopalakrishnan }
252683736352SVenkat Gopalakrishnan
2527bc99266bSSayali Lokhande if (!msm_host->mci_removed) {
2528cb064b50SYangtao Li msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1);
25290eb0d9f4SGeorgi Djakov if (IS_ERR(msm_host->core_mem)) {
25300eb0d9f4SGeorgi Djakov ret = PTR_ERR(msm_host->core_mem);
25310eb0d9f4SGeorgi Djakov goto clk_disable;
25320eb0d9f4SGeorgi Djakov }
2533bc99266bSSayali Lokhande }
25340eb0d9f4SGeorgi Djakov
25355574ddccSVenkat Gopalakrishnan /* Reset the vendor spec register to power on reset state */
25365574ddccSVenkat Gopalakrishnan writel_relaxed(CORE_VENDOR_SPEC_POR_VAL,
2537bc99266bSSayali Lokhande host->ioaddr + msm_offset->core_vendor_spec);
25380eb0d9f4SGeorgi Djakov
2539bc99266bSSayali Lokhande if (!msm_host->mci_removed) {
25400eb0d9f4SGeorgi Djakov /* Set HC_MODE_EN bit in HC_MODE register */
2541bc99266bSSayali Lokhande msm_host_writel(msm_host, HC_MODE_EN, host,
2542bc99266bSSayali Lokhande msm_offset->core_hc_mode);
2543bc99266bSSayali Lokhande config = msm_host_readl(msm_host, host,
2544bc99266bSSayali Lokhande msm_offset->core_hc_mode);
2545ff06ce41SVenkat Gopalakrishnan config |= FF_CLK_SW_RST_DIS;
2546bc99266bSSayali Lokhande msm_host_writel(msm_host, config, host,
2547bc99266bSSayali Lokhande msm_offset->core_hc_mode);
2548bc99266bSSayali Lokhande }
2549ff06ce41SVenkat Gopalakrishnan
25500eb0d9f4SGeorgi Djakov host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
25510eb0d9f4SGeorgi Djakov dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
25520eb0d9f4SGeorgi Djakov host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
25530eb0d9f4SGeorgi Djakov SDHCI_VENDOR_VER_SHIFT));
25540eb0d9f4SGeorgi Djakov
2555bc99266bSSayali Lokhande core_version = msm_host_readl(msm_host, host,
2556bc99266bSSayali Lokhande msm_offset->core_mci_version);
25573a3ad3e9SGeorgi Djakov core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
25583a3ad3e9SGeorgi Djakov CORE_VERSION_MAJOR_SHIFT;
25593a3ad3e9SGeorgi Djakov core_minor = core_version & CORE_VERSION_MINOR_MASK;
25603a3ad3e9SGeorgi Djakov dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
25613a3ad3e9SGeorgi Djakov core_version, core_major, core_minor);
25623a3ad3e9SGeorgi Djakov
256383736352SVenkat Gopalakrishnan if (core_major == 1 && core_minor >= 0x42)
256483736352SVenkat Gopalakrishnan msm_host->use_14lpp_dll_reset = true;
256583736352SVenkat Gopalakrishnan
25663a3ad3e9SGeorgi Djakov /*
256702e4293dSRitesh Harjani * SDCC 5 controller with major version 1, minor version 0x34 and later
256802e4293dSRitesh Harjani * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
256902e4293dSRitesh Harjani */
257002e4293dSRitesh Harjani if (core_major == 1 && core_minor < 0x34)
257102e4293dSRitesh Harjani msm_host->use_cdclp533 = true;
257202e4293dSRitesh Harjani
257302e4293dSRitesh Harjani /*
25743a3ad3e9SGeorgi Djakov * Support for some capabilities is not advertised by newer
25753a3ad3e9SGeorgi Djakov * controller versions and must be explicitly enabled.
25763a3ad3e9SGeorgi Djakov */
25773a3ad3e9SGeorgi Djakov if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
257829301f40SRitesh Harjani config = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
257929301f40SRitesh Harjani config |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
258029301f40SRitesh Harjani writel_relaxed(config, host->ioaddr +
2581bc99266bSSayali Lokhande msm_offset->core_vendor_spec_capabilities0);
25823a3ad3e9SGeorgi Djakov }
25833a3ad3e9SGeorgi Djakov
2584fa56ac97SVeerabhadrarao Badiganti if (core_major == 1 && core_minor >= 0x49)
2585fa56ac97SVeerabhadrarao Badiganti msm_host->updated_ddr_cfg = true;
2586fa56ac97SVeerabhadrarao Badiganti
25878ffbfe43SDmitry Baryshkov if (core_major == 1 && core_minor >= 0x71)
25888ffbfe43SDmitry Baryshkov msm_host->uses_tassadar_dll = true;
25898ffbfe43SDmitry Baryshkov
259092a21738SVeerabhadrarao Badiganti ret = sdhci_msm_register_vreg(msm_host);
259192a21738SVeerabhadrarao Badiganti if (ret)
259292a21738SVeerabhadrarao Badiganti goto clk_disable;
259392a21738SVeerabhadrarao Badiganti
2594c7ccee22SSubhash Jadavani /*
2595c7ccee22SSubhash Jadavani * Power on reset state may trigger power irq if previous status of
2596c7ccee22SSubhash Jadavani * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
2597c7ccee22SSubhash Jadavani * interrupt in GIC, any pending power irq interrupt should be
2598c7ccee22SSubhash Jadavani * acknowledged. Otherwise power irq interrupt handler would be
2599c7ccee22SSubhash Jadavani * fired prematurely.
2600c7ccee22SSubhash Jadavani */
2601401b2d06SSahitya Tummala sdhci_msm_handle_pwr_irq(host, 0);
2602c7ccee22SSubhash Jadavani
2603c7ccee22SSubhash Jadavani /*
2604c7ccee22SSubhash Jadavani * Ensure that above writes are propogated before interrupt enablement
2605c7ccee22SSubhash Jadavani * in GIC.
2606c7ccee22SSubhash Jadavani */
2607c7ccee22SSubhash Jadavani mb();
2608c7ccee22SSubhash Jadavani
2609ad81d387SGeorgi Djakov /* Setup IRQ for handling power/voltage tasks with PMIC */
2610ad81d387SGeorgi Djakov msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
2611ad81d387SGeorgi Djakov if (msm_host->pwr_irq < 0) {
2612d1f63f0cSWei Yongjun ret = msm_host->pwr_irq;
2613ad81d387SGeorgi Djakov goto clk_disable;
2614ad81d387SGeorgi Djakov }
2615ad81d387SGeorgi Djakov
2616c0309b38SVijay Viswanath sdhci_msm_init_pwr_irq_wait(msm_host);
2617c7ccee22SSubhash Jadavani /* Enable pwr irq interrupts */
2618bc99266bSSayali Lokhande msm_host_writel(msm_host, INT_MASK, host,
2619bc99266bSSayali Lokhande msm_offset->core_pwrctl_mask);
2620c7ccee22SSubhash Jadavani
2621ad81d387SGeorgi Djakov ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,
2622ad81d387SGeorgi Djakov sdhci_msm_pwr_irq, IRQF_ONESHOT,
2623ad81d387SGeorgi Djakov dev_name(&pdev->dev), host);
2624ad81d387SGeorgi Djakov if (ret) {
2625ad81d387SGeorgi Djakov dev_err(&pdev->dev, "Request IRQ failed (%d)\n", ret);
2626ad81d387SGeorgi Djakov goto clk_disable;
2627ad81d387SGeorgi Djakov }
2628ad81d387SGeorgi Djakov
26299d8cb586SVeerabhadrarao Badiganti msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
26309d8cb586SVeerabhadrarao Badiganti
2631ed78a03dSSahitya Tummala /* Set the timeout value to max possible */
2632ed78a03dSSahitya Tummala host->max_timeout_count = 0xF;
2633ed78a03dSSahitya Tummala
263467e6db11SPramod Gurav pm_runtime_get_noresume(&pdev->dev);
263567e6db11SPramod Gurav pm_runtime_set_active(&pdev->dev);
263667e6db11SPramod Gurav pm_runtime_enable(&pdev->dev);
263767e6db11SPramod Gurav pm_runtime_set_autosuspend_delay(&pdev->dev,
263867e6db11SPramod Gurav MSM_MMC_AUTOSUSPEND_DELAY_MS);
263967e6db11SPramod Gurav pm_runtime_use_autosuspend(&pdev->dev);
264067e6db11SPramod Gurav
264192a21738SVeerabhadrarao Badiganti host->mmc_host_ops.start_signal_voltage_switch =
264292a21738SVeerabhadrarao Badiganti sdhci_msm_start_signal_voltage_switch;
26434436c535SRitesh Harjani host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
264487a8df0dSRitesh Harjani if (of_property_read_bool(node, "supports-cqe"))
264587a8df0dSRitesh Harjani ret = sdhci_msm_cqe_add_host(host, pdev);
264687a8df0dSRitesh Harjani else
26470eb0d9f4SGeorgi Djakov ret = sdhci_add_host(host);
26480eb0d9f4SGeorgi Djakov if (ret)
264967e6db11SPramod Gurav goto pm_runtime_disable;
265067e6db11SPramod Gurav
265167e6db11SPramod Gurav pm_runtime_mark_last_busy(&pdev->dev);
265267e6db11SPramod Gurav pm_runtime_put_autosuspend(&pdev->dev);
26530eb0d9f4SGeorgi Djakov
26540eb0d9f4SGeorgi Djakov return 0;
26550eb0d9f4SGeorgi Djakov
265667e6db11SPramod Gurav pm_runtime_disable:
265767e6db11SPramod Gurav pm_runtime_disable(&pdev->dev);
265867e6db11SPramod Gurav pm_runtime_set_suspended(&pdev->dev);
265967e6db11SPramod Gurav pm_runtime_put_noidle(&pdev->dev);
26600eb0d9f4SGeorgi Djakov clk_disable:
2661e4bf91f6SBjorn Andersson clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2662e4bf91f6SBjorn Andersson msm_host->bulk_clks);
26630eb0d9f4SGeorgi Djakov bus_clk_disable:
26640eb0d9f4SGeorgi Djakov if (!IS_ERR(msm_host->bus_clk))
26650eb0d9f4SGeorgi Djakov clk_disable_unprepare(msm_host->bus_clk);
26660eb0d9f4SGeorgi Djakov pltfm_free:
26670eb0d9f4SGeorgi Djakov sdhci_pltfm_free(pdev);
26680eb0d9f4SGeorgi Djakov return ret;
26690eb0d9f4SGeorgi Djakov }
26700eb0d9f4SGeorgi Djakov
sdhci_msm_remove(struct platform_device * pdev)2671a7dde463SYangtao Li static void sdhci_msm_remove(struct platform_device *pdev)
26720eb0d9f4SGeorgi Djakov {
26730eb0d9f4SGeorgi Djakov struct sdhci_host *host = platform_get_drvdata(pdev);
26740eb0d9f4SGeorgi Djakov struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
26756f699531SJisheng Zhang struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
26760eb0d9f4SGeorgi Djakov int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
26770eb0d9f4SGeorgi Djakov 0xffffffff);
26780eb0d9f4SGeorgi Djakov
26790eb0d9f4SGeorgi Djakov sdhci_remove_host(host, dead);
268067e6db11SPramod Gurav
268167e6db11SPramod Gurav pm_runtime_get_sync(&pdev->dev);
268267e6db11SPramod Gurav pm_runtime_disable(&pdev->dev);
268367e6db11SPramod Gurav pm_runtime_put_noidle(&pdev->dev);
268467e6db11SPramod Gurav
2685e4bf91f6SBjorn Andersson clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2686e4bf91f6SBjorn Andersson msm_host->bulk_clks);
26870eb0d9f4SGeorgi Djakov if (!IS_ERR(msm_host->bus_clk))
26880eb0d9f4SGeorgi Djakov clk_disable_unprepare(msm_host->bus_clk);
26896f699531SJisheng Zhang sdhci_pltfm_free(pdev);
26900eb0d9f4SGeorgi Djakov }
26910eb0d9f4SGeorgi Djakov
sdhci_msm_runtime_suspend(struct device * dev)26926809a5f7SArnd Bergmann static __maybe_unused int sdhci_msm_runtime_suspend(struct device *dev)
269367e6db11SPramod Gurav {
269467e6db11SPramod Gurav struct sdhci_host *host = dev_get_drvdata(dev);
269567e6db11SPramod Gurav struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
269667e6db11SPramod Gurav struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
269756b99a52SMantas Pucka unsigned long flags;
269856b99a52SMantas Pucka
269956b99a52SMantas Pucka spin_lock_irqsave(&host->lock, flags);
270056b99a52SMantas Pucka host->runtime_suspended = true;
270156b99a52SMantas Pucka spin_unlock_irqrestore(&host->lock, flags);
270267e6db11SPramod Gurav
27030472f8d3SRajendra Nayak /* Drop the performance vote */
27040472f8d3SRajendra Nayak dev_pm_opp_set_rate(dev, 0);
2705e4bf91f6SBjorn Andersson clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks),
2706e4bf91f6SBjorn Andersson msm_host->bulk_clks);
270767e6db11SPramod Gurav
2708c7eed31eSAbel Vesa return sdhci_msm_ice_suspend(msm_host);
270967e6db11SPramod Gurav }
271067e6db11SPramod Gurav
sdhci_msm_runtime_resume(struct device * dev)27116809a5f7SArnd Bergmann static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
271267e6db11SPramod Gurav {
271367e6db11SPramod Gurav struct sdhci_host *host = dev_get_drvdata(dev);
271467e6db11SPramod Gurav struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
271567e6db11SPramod Gurav struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
271656b99a52SMantas Pucka unsigned long flags;
271721f1e2d4SVeerabhadrarao Badiganti int ret;
271867e6db11SPramod Gurav
271921f1e2d4SVeerabhadrarao Badiganti ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks),
2720e4bf91f6SBjorn Andersson msm_host->bulk_clks);
272121f1e2d4SVeerabhadrarao Badiganti if (ret)
272221f1e2d4SVeerabhadrarao Badiganti return ret;
272321f1e2d4SVeerabhadrarao Badiganti /*
272421f1e2d4SVeerabhadrarao Badiganti * Whenever core-clock is gated dynamically, it's needed to
272521f1e2d4SVeerabhadrarao Badiganti * restore the SDR DLL settings when the clock is ungated.
272621f1e2d4SVeerabhadrarao Badiganti */
2727c93767cfSEric Biggers if (msm_host->restore_dll_config && msm_host->clk_rate) {
27280472f8d3SRajendra Nayak ret = sdhci_msm_restore_sdr_dll_config(host);
2729c93767cfSEric Biggers if (ret)
2730c93767cfSEric Biggers return ret;
2731c93767cfSEric Biggers }
273221f1e2d4SVeerabhadrarao Badiganti
27330472f8d3SRajendra Nayak dev_pm_opp_set_rate(dev, msm_host->clk_rate);
27340472f8d3SRajendra Nayak
273556b99a52SMantas Pucka ret = sdhci_msm_ice_resume(msm_host);
273656b99a52SMantas Pucka if (ret)
273756b99a52SMantas Pucka return ret;
273856b99a52SMantas Pucka
273956b99a52SMantas Pucka spin_lock_irqsave(&host->lock, flags);
274056b99a52SMantas Pucka host->runtime_suspended = false;
274156b99a52SMantas Pucka spin_unlock_irqrestore(&host->lock, flags);
274256b99a52SMantas Pucka
274356b99a52SMantas Pucka return ret;
274467e6db11SPramod Gurav }
274567e6db11SPramod Gurav
274667e6db11SPramod Gurav static const struct dev_pm_ops sdhci_msm_pm_ops = {
274767e6db11SPramod Gurav SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
274867e6db11SPramod Gurav pm_runtime_force_resume)
274967e6db11SPramod Gurav SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend,
275067e6db11SPramod Gurav sdhci_msm_runtime_resume,
275167e6db11SPramod Gurav NULL)
275267e6db11SPramod Gurav };
275367e6db11SPramod Gurav
27540eb0d9f4SGeorgi Djakov static struct platform_driver sdhci_msm_driver = {
27550eb0d9f4SGeorgi Djakov .probe = sdhci_msm_probe,
2756a7dde463SYangtao Li .remove_new = sdhci_msm_remove,
27570eb0d9f4SGeorgi Djakov .driver = {
27580eb0d9f4SGeorgi Djakov .name = "sdhci_msm",
27590eb0d9f4SGeorgi Djakov .of_match_table = sdhci_msm_dt_match,
276067e6db11SPramod Gurav .pm = &sdhci_msm_pm_ops,
27618c98644bSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
27620eb0d9f4SGeorgi Djakov },
27630eb0d9f4SGeorgi Djakov };
27640eb0d9f4SGeorgi Djakov
27650eb0d9f4SGeorgi Djakov module_platform_driver(sdhci_msm_driver);
27660eb0d9f4SGeorgi Djakov
27670eb0d9f4SGeorgi Djakov MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
27680eb0d9f4SGeorgi Djakov MODULE_LICENSE("GPL v2");
2769