29 #include "hw/misc/mps2-scc.h"
31 #include "hw/qdev-properties.h"
53 REG32(DLL, 0x100)
60     return extract32(s->id, 4, 8);  in scc_partno()
116     if (function != 1 || device >= s->num_oscclk) {  in scc_cfg_write()
118                       "MPS2 SCC config write: bad function %d device %d\n",  in scc_cfg_write()
123     s->oscclk[device] = value;  in scc_cfg_write()
134     if (function != 1 || device >= s->num_oscclk) {  in scc_cfg_read()
136                       "MPS2 SCC config read: bad function %d device %d\n",  in scc_cfg_read()
141     *value = s->oscclk[device];  in scc_cfg_read()
154         r = s->cfg0;  in mps2_scc_read()
157         r = s->cfg1;  in mps2_scc_read()
163         r = s->cfg2;  in mps2_scc_read()
170          * These are user-settable DIP switches on the board. We don't  in mps2_scc_read()
177          * bits are not interesting to us; read-as-zero is as good as anything  in mps2_scc_read()
183         r = s->cfg4;  in mps2_scc_read()
189         r = s->cfg5;  in mps2_scc_read()
195         r = s->cfg6;  in mps2_scc_read()
201         r = s->cfg7;  in mps2_scc_read()
204         r = s->cfgdata_rtn;  in mps2_scc_read()
207         r = s->cfgdata_out;  in mps2_scc_read()
210         r = s->cfgctrl;  in mps2_scc_read()
213         r = s->cfgstat;  in mps2_scc_read()
216         r = s->dll;  in mps2_scc_read()
219         r = s->aid;  in mps2_scc_read()
222         r = s->id;  in mps2_scc_read()
246          * On some boards bit 0 controls board-specific remapping;  in mps2_scc_write()
255         s->cfg0 = value;  in mps2_scc_write()
257             qemu_set_irq(s->remap, s->cfg0 & 1);  in mps2_scc_write()
261         s->cfg1 = value;  in mps2_scc_write()
270             for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {  in mps2_scc_write()
271                 led_set_state(s->led[i], extract32(value, i, 1));  in mps2_scc_write()
280         s->cfg2 = value;  in mps2_scc_write()
287         s->cfg5 = value;  in mps2_scc_write()
295         s->cfg6 = value;  in mps2_scc_write()
302         s->cfg6 = value;  in mps2_scc_write()
305         s->cfgdata_out = value;  in mps2_scc_write()
309         s->cfgstat = 0;  in mps2_scc_write()
310         s->cfgctrl = value & ~(R_CFGCTRL_RES1_MASK |  in mps2_scc_write()
315             /* Start bit set -- do a read or write (instantaneously) */  in mps2_scc_write()
316             int device = extract32(s->cfgctrl, R_CFGCTRL_DEVICE_SHIFT,  in mps2_scc_write()
318             int function = extract32(s->cfgctrl, R_CFGCTRL_FUNCTION_SHIFT,  in mps2_scc_write()
321             s->cfgstat = R_CFGSTAT_DONE_MASK;  in mps2_scc_write()
322             if (s->cfgctrl & R_CFGCTRL_WRITE_MASK) {  in mps2_scc_write()
323                 if (!scc_cfg_write(s, function, device, s->cfgdata_out)) {  in mps2_scc_write()
324                     s->cfgstat |= R_CFGSTAT_ERROR_MASK;  in mps2_scc_write()
329                     s->cfgstat |= R_CFGSTAT_ERROR_MASK;  in mps2_scc_write()
331                     s->cfgdata_rtn = result;  in mps2_scc_write()
337         /* DLL stands for Digital Locked Loop.  in mps2_scc_write()
344         s->dll = deposit32(s->dll, 24, 8, extract32(value, 24, 8));  in mps2_scc_write()
366     s->cfg0 = s->cfg0_reset;  in mps2_scc_reset()
367     s->cfg1 = 0;  in mps2_scc_reset()
368     s->cfg2 = 0;  in mps2_scc_reset()
369     s->cfg5 = 0;  in mps2_scc_reset()
370     s->cfg6 = 0;  in mps2_scc_reset()
371     s->cfgdata_rtn = 0;  in mps2_scc_reset()
372     s->cfgdata_out = 0;  in mps2_scc_reset()
373     s->cfgctrl = 0x100000;  in mps2_scc_reset()
374     s->cfgstat = 0;  in mps2_scc_reset()
375     s->dll = 0xffff0001;  in mps2_scc_reset()
376     for (i = 0; i < s->num_oscclk; i++) {  in mps2_scc_reset()
377         s->oscclk[i] = s->oscclk_reset[i];  in mps2_scc_reset()
379     for (i = 0; i < ARRAY_SIZE(s->led); i++) {  in mps2_scc_reset()
380         device_cold_reset(DEVICE(s->led[i]));  in mps2_scc_reset()
389     memory_region_init_io(&s->iomem, obj, &mps2_scc_ops, s, "mps2-scc", 0x1000);  in mps2_scc_init()
390     sysbus_init_mmio(sbd, &s->iomem);  in mps2_scc_init()
391     qdev_init_gpio_out_named(DEVICE(obj), &s->remap, "remap", 1);  in mps2_scc_init()
398     for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {  in mps2_scc_realize()
400         s->led[i] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH,  in mps2_scc_realize()
405     s->oscclk = g_new0(uint32_t, s->num_oscclk);  in mps2_scc_realize()
412     g_free(s->oscclk_reset);  in mps2_scc_finalize()
423     .name = "mps2-scc/cfg7",
434     .name = "mps2-scc",
441         /* cfg3, cfg4 are read-only so need not be migrated */
448         VMSTATE_UINT32(dll, MPS2SCC),
460     /* Values for various read-only ID registers (which are specific
463     DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0),
464     DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0),
465     DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0),
467     DEFINE_PROP_UINT32("scc-cfg0", MPS2SCC, cfg0_reset, 0),
470      * In hardware they can be configured via a config file read by the
482     dc->realize = mps2_scc_realize;  in mps2_scc_class_init()
483     dc->vmsd = &mps2_scc_vmstate;  in mps2_scc_class_init()