Lines Matching +full:dll +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
29 * Rtt(nominal) - DDR2:
34 * Rtt(nominal) - DDR3:
49 * if (popts->dimmslot[i].num_valid_cs
50 * && (popts->cs_local_opts[2*i].odt_rd_cfg
51 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
155 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ in set_csn_config()
174 if (!popts->memctl_interleaving) in set_csn_config()
176 switch (popts->memctl_interleaving_mode) { in set_csn_config()
182 intlv_en = popts->memctl_interleaving; in set_csn_config()
183 intlv_ctl = popts->memctl_interleaving_mode; in set_csn_config()
211 ap_n_en = popts->cs_local_opts[i].auto_precharge; in set_csn_config()
212 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; in set_csn_config()
213 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; in set_csn_config()
220 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2; in set_csn_config()
222 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12; in set_csn_config()
223 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8; in set_csn_config()
225 ddr->cs[i].config = (0 in set_csn_config()
244 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); in set_csn_config()
251 unsigned int pasr_cfg = 0; /* Partial array self refresh config */ in set_csn_config_2()
253 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); in set_csn_config_2()
254 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); in set_csn_config_2()
257 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
261 * Check DIMM configuration, return 2 if quad-rank or two dual-rank
292 * dreams up non-zero default values to be backwards compatible.
299 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ in set_timing_cfg_0()
300 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ in set_timing_cfg_0()
301 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */ in set_timing_cfg_0()
302 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */ in set_timing_cfg_0()
303 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */ in set_timing_cfg_0()
326 * for single quad-rank DIMM and two-slot DIMMs in set_timing_cfg_0()
358 * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066 in set_timing_cfg_0()
359 * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133 in set_timing_cfg_0()
379 if (popts->registered_dimm_en) in set_timing_cfg_0()
388 * for single quad-rank DIMM and two-slot DIMMs in set_timing_cfg_0()
408 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving)) in set_timing_cfg_0()
411 if (popts->dynamic_power == 0) { /* powerdown is not used */ in set_timing_cfg_0()
418 /* Mode register MR0[A12] is '1' - fast exit */ in set_timing_cfg_0()
435 if (popts->trwt_override) in set_timing_cfg_0()
436 trwt_mclk = popts->trwt; in set_timing_cfg_0()
438 ddr->timing_cfg_0 = (0 in set_timing_cfg_0()
448 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); in set_timing_cfg_0()
477 ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4; in set_timing_cfg_3()
478 ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4; in set_timing_cfg_3()
479 ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4; in set_timing_cfg_3()
480 ext_caslat = (2 * cas_latency - 1) >> 4; in set_timing_cfg_3()
483 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4; in set_timing_cfg_3()
485 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4; in set_timing_cfg_3()
488 ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) + in set_timing_cfg_3()
489 (popts->otf_burst_chop_en ? 2 : 0)) >> 4; in set_timing_cfg_3()
491 ddr->timing_cfg_3 = (0 in set_timing_cfg_3()
501 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); in set_timing_cfg_3()
511 /* Precharge-to-activate interval (tRP) */ in set_timing_cfg_1()
523 /* Activate-to-activate interval (tRRD) */ in set_timing_cfg_1()
541 pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps); in set_timing_cfg_1()
542 acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps); in set_timing_cfg_1()
543 acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps); in set_timing_cfg_1()
550 * ------- ------- ------- ----- in set_timing_cfg_1()
564 caslat_ctrl = 2 * cas_latency - 1; in set_timing_cfg_1()
572 caslat_ctrl = 2 * cas_latency - 1; in set_timing_cfg_1()
574 caslat_ctrl = (cas_latency - 1) << 1; in set_timing_cfg_1()
578 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8; in set_timing_cfg_1()
579 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); in set_timing_cfg_1()
580 acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U); in set_timing_cfg_1()
585 wrrec_mclk = wrrec_table[wrrec_mclk - 1]; in set_timing_cfg_1()
587 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8; in set_timing_cfg_1()
588 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); in set_timing_cfg_1()
589 acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps); in set_timing_cfg_1()
590 wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps); in set_timing_cfg_1()
594 wrrec_mclk = wrrec_table[wrrec_mclk - 1]; in set_timing_cfg_1()
596 if (popts->otf_burst_chop_en) in set_timing_cfg_1()
616 if (popts->otf_burst_chop_en) in set_timing_cfg_1()
619 ddr->timing_cfg_1 = (0 in set_timing_cfg_1()
629 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); in set_timing_cfg_1()
642 /* CAS-to-preamble override */ in set_timing_cfg_2()
660 cpo = popts->cpo_override; in set_timing_cfg_2()
671 wr_lat = cas_latency - 1; in set_timing_cfg_2()
679 rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps); in set_timing_cfg_2()
691 if (popts->otf_burst_chop_en) in set_timing_cfg_2()
694 wr_data_delay = popts->write_data_delay; in set_timing_cfg_2()
700 * cke pulse = max(3nCK, 7.5ns) for DDR3-800 in set_timing_cfg_2()
701 * max(3nCK, 5.625ns) for DDR3-1066, 1333 in set_timing_cfg_2()
702 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133 in set_timing_cfg_2()
710 popts->tfaw_window_four_activates_ps); in set_timing_cfg_2()
712 ddr->timing_cfg_2 = (0 in set_timing_cfg_2()
722 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); in set_timing_cfg_2()
734 if (common_dimm->all_dimms_registered && in set_ddr_sdram_rcw()
735 !common_dimm->all_dimms_unbuffered) { in set_ddr_sdram_rcw()
736 if (popts->rcw_override) { in set_ddr_sdram_rcw()
737 ddr->ddr_sdram_rcw_1 = popts->rcw_1; in set_ddr_sdram_rcw()
738 ddr->ddr_sdram_rcw_2 = popts->rcw_2; in set_ddr_sdram_rcw()
739 ddr->ddr_sdram_rcw_3 = popts->rcw_3; in set_ddr_sdram_rcw()
751 ddr->ddr_sdram_rcw_1 = in set_ddr_sdram_rcw()
752 common_dimm->rcw[0] << 28 | \ in set_ddr_sdram_rcw()
753 common_dimm->rcw[1] << 24 | \ in set_ddr_sdram_rcw()
754 common_dimm->rcw[2] << 20 | \ in set_ddr_sdram_rcw()
755 common_dimm->rcw[3] << 16 | \ in set_ddr_sdram_rcw()
756 common_dimm->rcw[4] << 12 | \ in set_ddr_sdram_rcw()
757 common_dimm->rcw[5] << 8 | \ in set_ddr_sdram_rcw()
758 common_dimm->rcw[6] << 4 | \ in set_ddr_sdram_rcw()
759 common_dimm->rcw[7]; in set_ddr_sdram_rcw()
760 ddr->ddr_sdram_rcw_2 = in set_ddr_sdram_rcw()
761 common_dimm->rcw[8] << 28 | \ in set_ddr_sdram_rcw()
762 common_dimm->rcw[9] << 24 | \ in set_ddr_sdram_rcw()
764 common_dimm->rcw[11] << 16 | \ in set_ddr_sdram_rcw()
765 common_dimm->rcw[12] << 12 | \ in set_ddr_sdram_rcw()
766 common_dimm->rcw[13] << 8 | \ in set_ddr_sdram_rcw()
767 common_dimm->rcw[14] << 4 | \ in set_ddr_sdram_rcw()
769 ddr->ddr_sdram_rcw_3 = in set_ddr_sdram_rcw()
770 ((ddr_freq - 1260 + 19) / 20) << 8; in set_ddr_sdram_rcw()
773 ddr->ddr_sdram_rcw_1); in set_ddr_sdram_rcw()
775 ddr->ddr_sdram_rcw_2); in set_ddr_sdram_rcw()
777 ddr->ddr_sdram_rcw_3); in set_ddr_sdram_rcw()
793 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ in set_ddr_sdram_cfg()
794 unsigned int ncap = 0; /* Non-concurrent auto-precharge */ in set_ddr_sdram_cfg()
806 sren = popts->self_refresh_in_sleep; in set_ddr_sdram_cfg()
807 if (common_dimm->all_dimms_ecc_capable) { in set_ddr_sdram_cfg()
809 ecc_en = popts->ecc_mode; in set_ddr_sdram_cfg()
814 if (common_dimm->all_dimms_registered && in set_ddr_sdram_cfg()
815 !common_dimm->all_dimms_unbuffered) { in set_ddr_sdram_cfg()
820 twot_en = popts->twot_en; in set_ddr_sdram_cfg()
825 dyn_pwr = popts->dynamic_power; in set_ddr_sdram_cfg()
826 dbw = popts->data_bus_width; in set_ddr_sdram_cfg()
827 /* 8-beat burst enable DDR-III case in set_ddr_sdram_cfg()
828 * we must clear it when use the on-the-fly mode, in set_ddr_sdram_cfg()
829 * must set it when use the 32-bits bus mode. in set_ddr_sdram_cfg()
833 if (popts->burst_length == DDR_BL8) in set_ddr_sdram_cfg()
835 if (popts->burst_length == DDR_OTF) in set_ddr_sdram_cfg()
841 threet_en = popts->threet_en; in set_ddr_sdram_cfg()
842 ba_intlv_ctl = popts->ba_intlv_ctl; in set_ddr_sdram_cfg()
843 hse = popts->half_strength_driver_enable; in set_ddr_sdram_cfg()
848 ddr->ddr_sdram_cfg = (0 in set_ddr_sdram_cfg()
868 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); in set_ddr_sdram_cfg()
878 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ in set_ddr_sdram_cfg_2()
883 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ in set_ddr_sdram_cfg_2()
888 unsigned int qd_en = 0; /* quad-rank DIMM Enable */ in set_ddr_sdram_cfg_2()
891 unsigned int dll_rst_dis = 1; /* DLL reset disable */ in set_ddr_sdram_cfg_2()
894 dqs_cfg = popts->dqs_config; in set_ddr_sdram_cfg_2()
897 if (popts->cs_local_opts[i].odt_rd_cfg in set_ddr_sdram_cfg_2()
898 || popts->cs_local_opts[i].odt_wr_cfg) { in set_ddr_sdram_cfg_2()
903 sr_ie = popts->self_refresh_interrupt_en; in set_ddr_sdram_cfg_2()
904 num_pr = popts->package_3ds + 1; in set_ddr_sdram_cfg_2()
914 obc_cfg = popts->otf_burst_chop_en; in set_ddr_sdram_cfg_2()
923 if (popts->registered_dimm_en) in set_ddr_sdram_cfg_2()
928 (!popts->registered_dimm_en)) { in set_ddr_sdram_cfg_2()
931 ap_en = popts->ap_en; in set_ddr_sdram_cfg_2()
934 x4_en = popts->x4_en ? 1 : 0; in set_ddr_sdram_cfg_2()
938 d_init = popts->ecc_init_using_memctl; in set_ddr_sdram_cfg_2()
939 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; in set_ddr_sdram_cfg_2()
940 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); in set_ddr_sdram_cfg_2()
947 md_en = popts->mirrored_dimm; in set_ddr_sdram_cfg_2()
949 qd_en = popts->quad_rank_present ? 1 : 0; in set_ddr_sdram_cfg_2()
950 ddr->ddr_sdram_cfg_2 = (0 in set_ddr_sdram_cfg_2()
969 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); in set_ddr_sdram_cfg_2()
984 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ in set_ddr_sdram_mode_2()
985 unsigned int srt = 0; /* self-refresh temerature, normal range */ in set_ddr_sdram_mode_2()
986 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9; in set_ddr_sdram_mode_2()
991 if (popts->rtt_override) in set_ddr_sdram_mode_2()
992 rtt_wr = popts->rtt_wr_override_value; in set_ddr_sdram_mode_2()
994 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; in set_ddr_sdram_mode_2()
996 if (common_dimm->extended_op_srt) in set_ddr_sdram_mode_2()
997 srt = common_dimm->extended_op_srt; in set_ddr_sdram_mode_2()
1016 ddr->ddr_sdram_mode_2 = (0 in set_ddr_sdram_mode_2()
1020 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); in set_ddr_sdram_mode_2()
1024 if (popts->rtt_override) in set_ddr_sdram_mode_2()
1025 rtt_wr = popts->rtt_wr_override_value; in set_ddr_sdram_mode_2()
1027 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; in set_ddr_sdram_mode_2()
1033 ddr->ddr_sdram_mode_4 = (0 in set_ddr_sdram_mode_2()
1039 ddr->ddr_sdram_mode_6 = (0 in set_ddr_sdram_mode_2()
1045 ddr->ddr_sdram_mode_8 = (0 in set_ddr_sdram_mode_2()
1053 ddr->ddr_sdram_mode_4); in set_ddr_sdram_mode_2()
1055 ddr->ddr_sdram_mode_6); in set_ddr_sdram_mode_2()
1057 ddr->ddr_sdram_mode_8); in set_ddr_sdram_mode_2()
1071 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ in set_ddr_sdram_mode_2()
1072 unsigned int srt = 0; /* self-refresh temerature, normal range */ in set_ddr_sdram_mode_2()
1073 unsigned int asr = 0; /* auto self-refresh disable */ in set_ddr_sdram_mode_2()
1074 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5; in set_ddr_sdram_mode_2()
1077 if (popts->rtt_override) in set_ddr_sdram_mode_2()
1078 rtt_wr = popts->rtt_wr_override_value; in set_ddr_sdram_mode_2()
1080 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; in set_ddr_sdram_mode_2()
1082 if (common_dimm->extended_op_srt) in set_ddr_sdram_mode_2()
1083 srt = common_dimm->extended_op_srt; in set_ddr_sdram_mode_2()
1091 ddr->ddr_sdram_mode_2 = (0 in set_ddr_sdram_mode_2()
1095 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); in set_ddr_sdram_mode_2()
1099 if (popts->rtt_override) in set_ddr_sdram_mode_2()
1100 rtt_wr = popts->rtt_wr_override_value; in set_ddr_sdram_mode_2()
1102 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; in set_ddr_sdram_mode_2()
1108 ddr->ddr_sdram_mode_4 = (0 in set_ddr_sdram_mode_2()
1114 ddr->ddr_sdram_mode_6 = (0 in set_ddr_sdram_mode_2()
1120 ddr->ddr_sdram_mode_8 = (0 in set_ddr_sdram_mode_2()
1128 ddr->ddr_sdram_mode_4); in set_ddr_sdram_mode_2()
1130 ddr->ddr_sdram_mode_6); in set_ddr_sdram_mode_2()
1132 ddr->ddr_sdram_mode_8); in set_ddr_sdram_mode_2()
1147 ddr->ddr_sdram_mode_2 = (0 in set_ddr_sdram_mode_2()
1151 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); in set_ddr_sdram_mode_2()
1170 if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) && in set_ddr_sdram_mode_9()
1171 (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) && in set_ddr_sdram_mode_9()
1172 (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) && in set_ddr_sdram_mode_9()
1173 (ddr->cs[3].config & SDRAM_CS_CONFIG_EN)) in set_ddr_sdram_mode_9()
1176 if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) { in set_ddr_sdram_mode_9()
1188 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) && in set_ddr_sdram_mode_9()
1190 !popts->registered_dimm_en)) { in set_ddr_sdram_mode_9()
1192 /* for DDR4-1600/1866/2133 */ in set_ddr_sdram_mode_9()
1195 /* for DDR4-2400 */ in set_ddr_sdram_mode_9()
1202 ddr->ddr_sdram_mode_9 = (0 in set_ddr_sdram_mode_9()
1208 * But when four chip-selects are all enabled, all mode registers in set_ddr_sdram_mode_9()
1212 debug("FSLDDR: ddr_sdram_mode_9 = 0x%08x\n", ddr->ddr_sdram_mode_9); in set_ddr_sdram_mode_9()
1216 (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) { in set_ddr_sdram_mode_9()
1223 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) && in set_ddr_sdram_mode_9()
1225 !popts->registered_dimm_en)) { in set_ddr_sdram_mode_9()
1227 /* for DDR4-1600/1866/2133 */ in set_ddr_sdram_mode_9()
1230 /* for DDR4-2400 */ in set_ddr_sdram_mode_9()
1240 ddr->ddr_sdram_mode_11 = (0 in set_ddr_sdram_mode_9()
1246 ddr->ddr_sdram_mode_13 = (0 in set_ddr_sdram_mode_9()
1252 ddr->ddr_sdram_mode_15 = (0 in set_ddr_sdram_mode_9()
1260 ddr->ddr_sdram_mode_11); in set_ddr_sdram_mode_9()
1262 ddr->ddr_sdram_mode_13); in set_ddr_sdram_mode_9()
1264 ddr->ddr_sdram_mode_15); in set_ddr_sdram_mode_9()
1278 unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); in set_ddr_sdram_mode_10()
1280 esdmode6 = ((tccdl_min - 4) & 0x7) << 10; in set_ddr_sdram_mode_10()
1282 if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) in set_ddr_sdram_mode_10()
1285 ddr->ddr_sdram_mode_10 = (0 in set_ddr_sdram_mode_10()
1289 debug("FSLDDR: ddr_sdram_mode_10 = 0x%08x\n", ddr->ddr_sdram_mode_10); in set_ddr_sdram_mode_10()
1294 ddr->ddr_sdram_mode_12 = (0 in set_ddr_sdram_mode_10()
1300 ddr->ddr_sdram_mode_14 = (0 in set_ddr_sdram_mode_10()
1306 ddr->ddr_sdram_mode_16 = (0 in set_ddr_sdram_mode_10()
1314 ddr->ddr_sdram_mode_12); in set_ddr_sdram_mode_10()
1316 ddr->ddr_sdram_mode_14); in set_ddr_sdram_mode_10()
1318 ddr->ddr_sdram_mode_16); in set_ddr_sdram_mode_10()
1333 refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps); in set_ddr_sdram_interval()
1335 bstopre = popts->bstopre; in set_ddr_sdram_interval()
1338 ddr->ddr_sdram_interval = (0 in set_ddr_sdram_interval()
1342 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); in set_ddr_sdram_interval()
1359 /* Mode Register - MR1 */ in set_ddr_sdram_mode()
1366 unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal), in set_ddr_sdram_mode()
1369 /* Mode Register - MR0 */ in set_ddr_sdram_mode()
1371 unsigned int dll_rst; /* DLL Reset */ in set_ddr_sdram_mode()
1387 if (popts->rtt_override) in set_ddr_sdram_mode()
1388 rtt = popts->rtt_override_value; in set_ddr_sdram_mode()
1390 rtt = popts->cs_local_opts[0].odt_rtt_norm; in set_ddr_sdram_mode()
1392 if (additive_latency == (cas_latency - 1)) in set_ddr_sdram_mode()
1394 if (additive_latency == (cas_latency - 2)) in set_ddr_sdram_mode()
1397 if (popts->quad_rank_present) in set_ddr_sdram_mode()
1418 * DLL control for precharge PD in set_ddr_sdram_mode()
1419 * 0=slow exit DLL off (tXPDLL) in set_ddr_sdram_mode()
1420 * 1=fast exit DLL on (tXP) in set_ddr_sdram_mode()
1423 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); in set_ddr_sdram_mode()
1425 wr = wr_table[wr_mclk - 10]; in set_ddr_sdram_mode()
1431 dll_rst = 0; /* dll no reset */ in set_ddr_sdram_mode()
1436 caslat = cas_latency_table[cas_latency - 9]; in set_ddr_sdram_mode()
1442 switch (popts->burst_length) { in set_ddr_sdram_mode()
1454 popts->burst_length); in set_ddr_sdram_mode()
1455 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n"); in set_ddr_sdram_mode()
1470 ddr->ddr_sdram_mode = (0 in set_ddr_sdram_mode()
1475 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); in set_ddr_sdram_mode()
1479 if (popts->rtt_override) in set_ddr_sdram_mode()
1480 rtt = popts->rtt_override_value; in set_ddr_sdram_mode()
1482 rtt = popts->cs_local_opts[i].odt_rtt_norm; in set_ddr_sdram_mode()
1488 ddr->ddr_sdram_mode_3 = (0 in set_ddr_sdram_mode()
1494 ddr->ddr_sdram_mode_5 = (0 in set_ddr_sdram_mode()
1500 ddr->ddr_sdram_mode_7 = (0 in set_ddr_sdram_mode()
1508 ddr->ddr_sdram_mode_3); in set_ddr_sdram_mode()
1510 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1512 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1530 /* Mode Register - MR1 */ in set_ddr_sdram_mode()
1537 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), in set_ddr_sdram_mode()
1540 /* Mode Register - MR0 */ in set_ddr_sdram_mode()
1541 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */ in set_ddr_sdram_mode()
1543 unsigned int dll_rst; /* DLL Reset */ in set_ddr_sdram_mode()
1553 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0 in set_ddr_sdram_mode()
1558 if (popts->rtt_override) in set_ddr_sdram_mode()
1559 rtt = popts->rtt_override_value; in set_ddr_sdram_mode()
1561 rtt = popts->cs_local_opts[0].odt_rtt_norm; in set_ddr_sdram_mode()
1563 if (additive_latency == (cas_latency - 1)) in set_ddr_sdram_mode()
1565 if (additive_latency == (cas_latency - 2)) in set_ddr_sdram_mode()
1568 if (popts->quad_rank_present) in set_ddr_sdram_mode()
1592 * DLL control for precharge PD in set_ddr_sdram_mode()
1593 * 0=slow exit DLL off (tXPDLL) in set_ddr_sdram_mode()
1594 * 1=fast exit DLL on (tXP) in set_ddr_sdram_mode()
1598 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); in set_ddr_sdram_mode()
1600 wr = wr_table[wr_mclk - 5]; in set_ddr_sdram_mode()
1606 dll_rst = 0; /* dll no reset */ in set_ddr_sdram_mode()
1625 caslat = cas_latency_table[cas_latency - 5]; in set_ddr_sdram_mode()
1632 switch (popts->burst_length) { in set_ddr_sdram_mode()
1644 " Defaulting to on-the-fly BC4 or BL8 beats.\n", in set_ddr_sdram_mode()
1645 popts->burst_length); in set_ddr_sdram_mode()
1661 ddr->ddr_sdram_mode = (0 in set_ddr_sdram_mode()
1666 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); in set_ddr_sdram_mode()
1670 if (popts->rtt_override) in set_ddr_sdram_mode()
1671 rtt = popts->rtt_override_value; in set_ddr_sdram_mode()
1673 rtt = popts->cs_local_opts[i].odt_rtt_norm; in set_ddr_sdram_mode()
1683 ddr->ddr_sdram_mode_3 = (0 in set_ddr_sdram_mode()
1689 ddr->ddr_sdram_mode_5 = (0 in set_ddr_sdram_mode()
1695 ddr->ddr_sdram_mode_7 = (0 in set_ddr_sdram_mode()
1703 ddr->ddr_sdram_mode_3); in set_ddr_sdram_mode()
1705 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1707 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1726 * FIXME: This ought to be pre-calculated in a in set_ddr_sdram_mode()
1727 * technology-specific routine, in set_ddr_sdram_mode()
1744 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), in set_ddr_sdram_mode()
1749 unsigned int pd; /* Power-Down Mode */ in set_ddr_sdram_mode()
1751 unsigned int dll_res; /* DLL Reset */ in set_ddr_sdram_mode()
1758 dqs_en = !popts->dqs_config; in set_ddr_sdram_mode()
1787 wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps); in set_ddr_sdram_mode()
1800 caslat = mode_caslat_table[cas_latency - 1]; in set_ddr_sdram_mode()
1809 switch (popts->burst_length) { in set_ddr_sdram_mode()
1819 popts->burst_length); in set_ddr_sdram_mode()
1835 ddr->ddr_sdram_mode = (0 in set_ddr_sdram_mode()
1839 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); in set_ddr_sdram_mode()
1853 ddr->ddr_data_init = init_value; in set_ddr_data_init()
1872 /* clk_adjust in 5-bits on T-series and LS-series */ in set_ddr_sdram_clk_cntl()
1873 clk_adjust = (popts->clk_adjust & 0x1F) << 22; in set_ddr_sdram_clk_cntl()
1875 /* clk_adjust in 4-bits on earlier MPC85xx and P-series */ in set_ddr_sdram_clk_cntl()
1876 clk_adjust = (popts->clk_adjust & 0xF) << 23; in set_ddr_sdram_clk_cntl()
1879 ddr->ddr_sdram_clk_cntl = (0 in set_ddr_sdram_clk_cntl()
1883 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); in set_ddr_sdram_clk_cntl()
1891 ddr->ddr_init_addr = init_addr; in set_ddr_init_addr()
1900 ddr->ddr_init_ext_addr = (0 in set_ddr_init_ext_addr()
1910 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ in set_timing_cfg_4()
1911 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ in set_timing_cfg_4()
1912 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */ in set_timing_cfg_4()
1913 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */ in set_timing_cfg_4()
1915 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ in set_timing_cfg_4()
1918 if (popts->burst_length == DDR_BL8) { in set_timing_cfg_4()
1934 if (popts->trwt_override) in set_timing_cfg_4()
1935 trwt_mclk = popts->trwt; in set_timing_cfg_4()
1937 ddr->timing_cfg_4 = (0 in set_timing_cfg_4()
1945 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); in set_timing_cfg_4()
1957 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + in set_timing_cfg_5()
1958 ((ddr->timing_cfg_2 & 0x00040000) >> 14); in set_timing_cfg_5()
1959 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */ in set_timing_cfg_5()
1961 rodt_on = cas_latency - wr_lat + 1; in set_timing_cfg_5()
1967 ddr->timing_cfg_5 = (0 in set_timing_cfg_5()
1973 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); in set_timing_cfg_5()
1985 ddr->timing_cfg_6 = (0 in set_timing_cfg_6()
1992 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6); in set_timing_cfg_6()
2004 txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000)); in set_timing_cfg_7()
2008 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN && in set_timing_cfg_7()
2011 par_lat = (ddr->ddr_sdram_rcw_2 & 0xf) + 1; in set_timing_cfg_7()
2027 cksre = tcksre - 5; in set_timing_cfg_7()
2032 cksrx = tcksrx - 5; in set_timing_cfg_7()
2036 ddr->timing_cfg_7 = (0 in set_timing_cfg_7()
2043 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7); in set_timing_cfg_7()
2054 int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); in set_timing_cfg_8()
2055 int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + in set_timing_cfg_8()
2056 ((ddr->timing_cfg_2 & 0x00040000) >> 14); in set_timing_cfg_8()
2058 rwt_bg = cas_latency + 2 + 4 - wr_lat; in set_timing_cfg_8()
2060 rwt_bg = tccdl - rwt_bg; in set_timing_cfg_8()
2064 wrt_bg = wr_lat + 4 + 1 - cas_latency; in set_timing_cfg_8()
2066 wrt_bg = tccdl - wrt_bg; in set_timing_cfg_8()
2070 if (popts->burst_length == DDR_BL8) { in set_timing_cfg_8()
2071 rrt_bg = tccdl - 4; in set_timing_cfg_8()
2072 wwt_bg = tccdl - 4; in set_timing_cfg_8()
2074 rrt_bg = tccdl - 2; in set_timing_cfg_8()
2075 wwt_bg = tccdl - 2; in set_timing_cfg_8()
2078 acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps); in set_timing_cfg_8()
2080 if (popts->otf_burst_chop_en) in set_timing_cfg_8()
2085 ddr->timing_cfg_8 = (0 in set_timing_cfg_8()
2095 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8); in set_timing_cfg_8()
2106 if (popts->package_3ds) { in set_timing_cfg_9()
2108 picos_to_mclk(ctrl_num, common_dimm->trfc_slr_ps); in set_timing_cfg_9()
2112 ddr->timing_cfg_9 = (refrec_cid_mclk & 0x3ff) << 16 | in set_timing_cfg_9()
2115 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9); in set_timing_cfg_9()
2122 unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1; in set_ddr_dq_mapping()
2134 ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) | in set_ddr_dq_mapping()
2140 ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) | in set_ddr_dq_mapping()
2146 ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) | in set_ddr_dq_mapping()
2153 ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) | in set_ddr_dq_mapping()
2159 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0); in set_ddr_dq_mapping()
2160 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1); in set_ddr_dq_mapping()
2161 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2); in set_ddr_dq_mapping()
2162 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3); in set_ddr_dq_mapping()
2169 rd_pre = popts->quad_rank_present ? 1 : 0; in set_ddr_sdram_cfg_3()
2171 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16; in set_ddr_sdram_cfg_3()
2173 ddr->ddr_sdram_cfg_3 |= popts->registered_dimm_en ? 1 : 0; in set_ddr_sdram_cfg_3()
2175 if (popts->package_3ds) { /* only 2,4,8 are supported */ in set_ddr_sdram_cfg_3()
2176 if ((popts->package_3ds + 1) & 0x1) { in set_ddr_sdram_cfg_3()
2178 popts->package_3ds + 1); in set_ddr_sdram_cfg_3()
2180 ddr->ddr_sdram_cfg_3 |= ((popts->package_3ds + 1) >> 1) in set_ddr_sdram_cfg_3()
2185 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3); in set_ddr_sdram_cfg_3()
2214 ddr->ddr_zq_cntl = (0 in set_ddr_zq_cntl()
2223 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); in set_ddr_zq_cntl()
2246 /* suggest enable write leveling for DDR3 due to fly-by topology */ in set_ddr_wrlvl_cntl()
2277 if (popts->wrlvl_override) { in set_ddr_wrlvl_cntl()
2278 wrlvl_smpl = popts->wrlvl_sample; in set_ddr_wrlvl_cntl()
2279 wrlvl_start = popts->wrlvl_start; in set_ddr_wrlvl_cntl()
2283 ddr->ddr_wrlvl_cntl = (0 in set_ddr_wrlvl_cntl()
2292 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); in set_ddr_wrlvl_cntl()
2293 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2; in set_ddr_wrlvl_cntl()
2294 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2); in set_ddr_wrlvl_cntl()
2295 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3; in set_ddr_wrlvl_cntl()
2296 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3); in set_ddr_wrlvl_cntl()
2304 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; in set_ddr_sr_cntr()
2309 if (popts->addr_hash) { in set_ddr_eor()
2310 ddr->ddr_eor = 0x40000000; /* address hash enable */ in set_ddr_eor()
2317 ddr->ddr_cdr1 = popts->ddr_cdr1; in set_ddr_cdr1()
2318 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); in set_ddr_cdr1()
2323 ddr->ddr_cdr2 = popts->ddr_cdr2; in set_ddr_cdr2()
2324 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2); in set_ddr_cdr2()
2336 if (ddr->ddr_sdram_cfg & 0x10000000 in check_fsl_memctl_config_regs()
2337 && ddr->ddr_sdram_cfg & 0x00008000) { in check_fsl_memctl_config_regs()
2409 cas_latency = (popts->cas_latency_override) in compute_fsl_memctl_config_regs()
2410 ? popts->cas_latency_override_value in compute_fsl_memctl_config_regs()
2411 : common_dimm->lowest_common_spd_caslat; in compute_fsl_memctl_config_regs()
2413 additive_latency = (popts->additive_latency_override) in compute_fsl_memctl_config_regs()
2414 ? popts->additive_latency_override_value in compute_fsl_memctl_config_regs()
2415 : common_dimm->additive_latency; in compute_fsl_memctl_config_regs()
2417 sr_it = (popts->auto_self_refresh_en) in compute_fsl_memctl_config_regs()
2418 ? popts->sr_it in compute_fsl_memctl_config_regs()
2421 zq_en = (popts->zq_en) ? 1 : 0; in compute_fsl_memctl_config_regs()
2423 wrlvl_en = (popts->wrlvl_en) ? 1 : 0; in compute_fsl_memctl_config_regs()
2440 if (popts->memctl_interleaving) { in compute_fsl_memctl_config_regs()
2441 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { in compute_fsl_memctl_config_regs()
2455 sa = common_dimm->base_address; in compute_fsl_memctl_config_regs()
2456 ea = sa + common_dimm->total_mem - 1; in compute_fsl_memctl_config_regs()
2457 } else if (!popts->memctl_interleaving) { in compute_fsl_memctl_config_regs()
2467 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { in compute_fsl_memctl_config_regs()
2469 sa = common_dimm->base_address; in compute_fsl_memctl_config_regs()
2470 ea = sa + common_dimm->total_mem - 1; in compute_fsl_memctl_config_regs()
2476 ea = sa + 2 * rank_density - 1; in compute_fsl_memctl_config_regs()
2479 ea = sa + 2 * rank_density - 1; in compute_fsl_memctl_config_regs()
2485 ea = sa + rank_density - 1; in compute_fsl_memctl_config_regs()
2499 ea = sa + rank_density - 1; in compute_fsl_memctl_config_regs()
2510 default: /* No bank(chip-select) interleaving */ in compute_fsl_memctl_config_regs()
2512 ea = sa + rank_density - 1; in compute_fsl_memctl_config_regs()
2528 ddr->cs[i].bnds = (0 in compute_fsl_memctl_config_regs()
2534 ddr->cs[i].bnds = 0xffffffff; in compute_fsl_memctl_config_regs()
2537 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); in compute_fsl_memctl_config_regs()
2568 if ((ip_rev > 0x40700) && (popts->cswl_override != 0)) in compute_fsl_memctl_config_regs()
2569 ddr->debug[18] = popts->cswl_override; in compute_fsl_memctl_config_regs()
2604 ddr->debug[2] = 0x00000400; in compute_fsl_memctl_config_regs()
2605 ddr->debug[4] = 0xff800800; in compute_fsl_memctl_config_regs()
2606 ddr->debug[5] = 0x08000800; in compute_fsl_memctl_config_regs()
2607 ddr->debug[6] = 0x08000800; in compute_fsl_memctl_config_regs()
2608 ddr->debug[7] = 0x08000800; in compute_fsl_memctl_config_regs()
2609 ddr->debug[8] = 0x08000800; in compute_fsl_memctl_config_regs()
2613 ddr->debug[2] |= 0x00000200; /* set bit 22 */ in compute_fsl_memctl_config_regs()
2621 if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) || in compute_fsl_memctl_config_regs()
2622 IS_DBI(ddr->ddr_sdram_cfg_3)) { in compute_fsl_memctl_config_regs()
2623 ddr->debug[28] = ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
2624 ddr->debug[28] |= (0x9 << 20); in compute_fsl_memctl_config_regs()
2631 ddr->debug[28] |= ddr_in32(&ddrc->debug[28]); in compute_fsl_memctl_config_regs()
2632 ddr->debug[28] &= 0xff0fff00; in compute_fsl_memctl_config_regs()
2634 ddr->debug[28] |= 0x0080006a; in compute_fsl_memctl_config_regs()
2636 ddr->debug[28] |= 0x0070006f; in compute_fsl_memctl_config_regs()
2638 ddr->debug[28] |= 0x00700076; in compute_fsl_memctl_config_regs()
2640 ddr->debug[28] |= 0x0060007b; in compute_fsl_memctl_config_regs()
2641 if (popts->cpo_sample) in compute_fsl_memctl_config_regs()
2642 ddr->debug[28] = (ddr->debug[28] & 0xffffff00) | in compute_fsl_memctl_config_regs()
2643 popts->cpo_sample; in compute_fsl_memctl_config_regs()
2661 u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24; in erratum_a009942_check_cpo()
2666 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in erratum_a009942_check_cpo()
2679 cpo = ddr_in32(&ddr->debug[i]); in erratum_a009942_check_cpo()
2691 cpo = ddr_in32(&ddr->debug[13]); in erratum_a009942_check_cpo()
2699 cpo_target = ddr_in32(&ddr->debug[28]) & 0xff; in erratum_a009942_check_cpo()
2713 printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal); in erratum_a009942_check_cpo()