Lines Matching +full:dll +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0
72 /* Poll - Wait for Refresh operation completion */ in wait_refresh_op_complete()
82 * Args: target_freq - target frequency
84 * Returns: freq_par - the ratio parameter
95 /* Find the ratio between PLL frequency and ddr-clk */ in ddr3_get_freq_parameter()
108 * Args: freq - target frequency
110 * Returns: MV_OK - success, MV_FAIL - fail
119 DEBUG_DFS_C("DDR3 - DFS - High To Low - Starting DFS procedure to Frequency - ", in ddr3_dfs_high_2_low()
122 /* target frequency - 100MHz */ in ddr3_dfs_high_2_low()
131 /* Configure - DRAM DLL final state after DFS is complete - Enable */ in ddr3_dfs_high_2_low()
133 /* [0] - DfsDllNextState - Disable */ in ddr3_dfs_high_2_low()
135 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
138 * Configure - XBAR Retry response during Block to enable internal in ddr3_dfs_high_2_low()
139 * access - Disable in ddr3_dfs_high_2_low()
142 /* [0] - RetryMask - Disable */ in ddr3_dfs_high_2_low()
144 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_high_2_low()
147 /* Configure - Block new external transactions - Enable */ in ddr3_dfs_high_2_low()
149 reg |= (1 << REG_DFS_BLOCK_OFFS); /* [1] - DfsBlock - Enable */ in ddr3_dfs_high_2_low()
150 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
153 if (dram_info->reg_dimm) { in ddr3_dfs_high_2_low()
155 * Configure - Disable Register DIMM CKE Power in ddr3_dfs_high_2_low()
156 * Down mode - CWA_RC in ddr3_dfs_high_2_low()
161 * Configure - Disable Register DIMM CKE Power in ddr3_dfs_high_2_low()
162 * Down mode - CWA_DATA in ddr3_dfs_high_2_low()
168 * Configure - Disable Register DIMM CKE Power in ddr3_dfs_high_2_low()
169 * Down mode - Set Delay - tMRD in ddr3_dfs_high_2_low()
173 /* Configure - Issue CWA command with the above parameters */ in ddr3_dfs_high_2_low()
177 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_high_2_low()
180 /* Poll - Wait for CWA operation completion */ in ddr3_dfs_high_2_low()
186 /* Configure - Disable outputs floating during Self Refresh */ in ddr3_dfs_high_2_low()
188 /* [15] - SRFloatEn - Disable */ in ddr3_dfs_high_2_low()
190 /* 0x16D0 - DDR3 Registered DRAM Control */ in ddr3_dfs_high_2_low()
194 /* Optional - Configure - DDR3_Rtt_nom_CS# */ in ddr3_dfs_high_2_low()
196 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
205 /* Configure - Move DRAM into Self Refresh */ in ddr3_dfs_high_2_low()
207 reg |= (1 << REG_DFS_SR_OFFS); /* [2] - DfsSR - Enable */ in ddr3_dfs_high_2_low()
208 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
210 /* Poll - Wait for Self Refresh indication */ in ddr3_dfs_high_2_low()
213 } while (reg == 0x0); /* 0x1528 [3] - DfsAtSR - Wait for '1' */ in ddr3_dfs_high_2_low()
245 reg |= (freq_par << 8); /* full Integer ratio from PLL-out to ddr-clk */ in ddr3_dfs_high_2_low()
267 * Initial Setup - assure that the "load new ratio" is clear (bit 24) in ddr3_dfs_high_2_low()
272 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_high_2_low()
280 /* 0x18704 - CPU Div CLK control 0 */ in ddr3_dfs_high_2_low()
286 /* full Integer ratio from PLL-out to ddr-clk */ in ddr3_dfs_high_2_low()
288 /* 0x1870C - CPU Div CLK control 3 register */ in ddr3_dfs_high_2_low()
293 * All the rest are kept as is (forced, but could be read-modify-write). in ddr3_dfs_high_2_low()
297 /* Clock is not shut off gracefully - keep it running */ in ddr3_dfs_high_2_low()
314 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_high_2_low()
320 * Poll Div CLK status 0 register - indication that the clocks in ddr3_dfs_high_2_low()
321 * are active - 0x18718 [8] in ddr3_dfs_high_2_low()
333 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_high_2_low()
340 /* Configure - Select normal clock for the DDR PHY - Enable */ in ddr3_dfs_high_2_low()
342 /* [16] - ddr_phy_trn_clk_sel - Enable */ in ddr3_dfs_high_2_low()
344 /* 0x18488 - DRAM Init control status register */ in ddr3_dfs_high_2_low()
347 /* Configure - Set Correct Ratio - 1:1 */ in ddr3_dfs_high_2_low()
348 /* [15] - Phy2UnitClkRatio = 0 - Set 1:1 Ratio between Dunit and Phy */ in ddr3_dfs_high_2_low()
351 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Register */ in ddr3_dfs_high_2_low()
353 /* Configure - 2T Mode - Restore original configuration */ in ddr3_dfs_high_2_low()
355 /* [3:4] 2T - 1T Mode - low freq */ in ddr3_dfs_high_2_low()
357 /* 0x1404 - DDR Controller Control Low Register */ in ddr3_dfs_high_2_low()
360 /* Configure - Restore CL and CWL - MRS Commands */ in ddr3_dfs_high_2_low()
364 /* [8] - DfsCLNextState - MRS CL=6 after DFS (due to DLL-off mode) */ in ddr3_dfs_high_2_low()
366 /* [12] - DfsCWLNextState - MRS CWL=6 after DFS (due to DLL-off mode) */ in ddr3_dfs_high_2_low()
368 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
370 /* Poll - Wait for APLL + ADLLs lock on new frequency */ in ddr3_dfs_high_2_low()
374 /* 0x1674 [10:0] - Phy lock status Register */ in ddr3_dfs_high_2_low()
377 /* Configure - Reset the PHY Read FIFO and Write channels - Set Reset */ in ddr3_dfs_high_2_low()
379 /* [30:29] = 0 - Data Pup R/W path reset */ in ddr3_dfs_high_2_low()
380 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_high_2_low()
384 * Configure - DRAM Data PHY Read [30], Write [29] path in ddr3_dfs_high_2_low()
385 * reset - Release Reset in ddr3_dfs_high_2_low()
388 /* [30:29] = '11' - Data Pup R/W path reset */ in ddr3_dfs_high_2_low()
389 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_high_2_low()
393 if (dram_info->reg_dimm) { in ddr3_dfs_high_2_low()
395 * Configure - Change register DRAM operating speed in ddr3_dfs_high_2_low()
396 * (below 400MHz) - CWA_RC in ddr3_dfs_high_2_low()
402 * Configure - Change register DRAM operating speed in ddr3_dfs_high_2_low()
403 * (below 400MHz) - CWA_DATA in ddr3_dfs_high_2_low()
408 /* Configure - Set Delay - tSTAB */ in ddr3_dfs_high_2_low()
411 /* Configure - Issue CWA command with the above parameters */ in ddr3_dfs_high_2_low()
415 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_high_2_low()
418 /* Poll - Wait for CWA operation completion */ in ddr3_dfs_high_2_low()
425 /* Configure - Exit Self Refresh */ in ddr3_dfs_high_2_low()
426 /* [2] - DfsSR */ in ddr3_dfs_high_2_low()
428 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
431 * Poll - DFS Register - 0x1528 [3] - DfsAtSR - All DRAM devices in ddr3_dfs_high_2_low()
438 /* Configure - Issue Refresh command */ in ddr3_dfs_high_2_low()
439 /* [3-0] = 0x2 - Refresh Command, [11-8] - enabled Cs */ in ddr3_dfs_high_2_low()
442 if (dram_info->cs_ena & (1 << cs)) in ddr3_dfs_high_2_low()
446 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_high_2_low()
449 /* Poll - Wait for Refresh operation completion */ in ddr3_dfs_high_2_low()
452 /* Configure - Block new external transactions - Disable */ in ddr3_dfs_high_2_low()
454 reg &= ~(1 << REG_DFS_BLOCK_OFFS); /* [1] - DfsBlock - Disable */ in ddr3_dfs_high_2_low()
455 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
458 * Configure - XBAR Retry response during Block to enable in ddr3_dfs_high_2_low()
459 * internal access - Disable in ddr3_dfs_high_2_low()
462 /* [0] - RetryMask - Enable */ in ddr3_dfs_high_2_low()
464 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_high_2_low()
468 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
469 /* Configure - Set CL */ in ddr3_dfs_high_2_low()
473 tmp = 0x4; /* CL=6 - 0x4 */ in ddr3_dfs_high_2_low()
479 /* Configure - Set CWL */ in ddr3_dfs_high_2_low()
483 /* CWL=6 - 0x1 */ in ddr3_dfs_high_2_low()
490 DEBUG_DFS_C("DDR3 - DFS - High To Low - Ended successfuly - new Frequency - ", in ddr3_dfs_high_2_low()
500 DEBUG_DFS_C("DDR3 - DFS - High To Low - Starting DFS procedure to Frequency - ", in ddr3_dfs_high_2_low()
503 /* target frequency - 100MHz */ in ddr3_dfs_high_2_low()
507 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_high_2_low()
510 /* 0x1600 - ODPG_CNTRL_Control */ in ddr3_dfs_high_2_low()
512 /* [21] = 1 - auto refresh disable */ in ddr3_dfs_high_2_low()
516 /* 0x1670 - PHY lock mask register */ in ddr3_dfs_high_2_low()
521 reg = reg_read(REG_DFS_ADDR); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
524 reg &= ~0x10; /* [4] - Enable reconfig MR registers after DFS_ERG */ in ddr3_dfs_high_2_low()
525 reg |= 0x1; /* [0] - DRAM DLL disabled after DFS */ in ddr3_dfs_high_2_low()
527 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
529 reg = reg_read(REG_METAL_MASK_ADDR) & ~(1 << 0); /* [0] - disable */ in ddr3_dfs_high_2_low()
530 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_high_2_low()
533 /* [1] - DFS Block enable */ in ddr3_dfs_high_2_low()
535 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
537 /* [2] - DFS Self refresh enable */ in ddr3_dfs_high_2_low()
539 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
542 * Poll DFS Register - 0x1528 [3] - DfsAtSR - in ddr3_dfs_high_2_low()
543 * All DRAM devices on all ranks are in self refresh mode - in ddr3_dfs_high_2_low()
550 /* Disable ODT on DLL-off mode */ in ddr3_dfs_high_2_low()
556 /* 0x1670 - PHY lock mask register */ in ddr3_dfs_high_2_low()
563 * Initial Setup - assure that the "load new ratio" is clear (bit 24) in ddr3_dfs_high_2_low()
568 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_high_2_low()
575 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_high_2_low()
580 /* Full Integer ratio from PLL-out to ddr-clk */ in ddr3_dfs_high_2_low()
582 /* 0x1870C - CPU Div CLK control 3 register */ in ddr3_dfs_high_2_low()
587 * All the rest are kept as is (forced, but could be read-modify-write). in ddr3_dfs_high_2_low()
591 /* Clock is not shut off gracefully - keep it running */ in ddr3_dfs_high_2_low()
608 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_high_2_low()
614 * Poll Div CLK status 0 register - indication that the clocks in ddr3_dfs_high_2_low()
615 * are active - 0x18718 [8] in ddr3_dfs_high_2_low()
627 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_high_2_low()
634 /* 0x18488 - DRAM Init control status register */ in ddr3_dfs_high_2_low()
638 /* [15] = 0 - Set 1:1 Ratio between Dunit and Phy */ in ddr3_dfs_high_2_low()
639 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Regist */ in ddr3_dfs_high_2_low()
642 /* [31:30]] - reset pup data ctrl ADLL */ in ddr3_dfs_high_2_low()
643 /* 0x15EC - DRAM PHY Config register */ in ddr3_dfs_high_2_low()
647 /* [31:30] - normal pup data ctrl ADLL */ in ddr3_dfs_high_2_low()
648 /* 0x15EC - DRAM PHY Config register */ in ddr3_dfs_high_2_low()
657 /* Poll Phy lock status register - APLL lock indication - 0x1674 */ in ddr3_dfs_high_2_low()
664 /* [30:29] = 0 - Data Pup R/W path reset */ in ddr3_dfs_high_2_low()
665 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_high_2_low()
669 /* [30:29] = '11' - Data Pup R/W path reset */ in ddr3_dfs_high_2_low()
670 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_high_2_low()
676 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_high_2_low()
677 /* Poll - Wait for Refresh operation completion */ in ddr3_dfs_high_2_low()
680 /* Config CL and CWL with MR0 and MR2 registers */ in ddr3_dfs_high_2_low()
687 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_high_2_low()
690 /* Poll - Wait for Refresh operation completion */ in ddr3_dfs_high_2_low()
700 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_high_2_low()
703 /* Poll - Wait for Refresh operation completion */ in ddr3_dfs_high_2_low()
722 /* [2] - DFS Self refresh disable */ in ddr3_dfs_high_2_low()
724 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
726 /* [1] - DFS Block enable */ in ddr3_dfs_high_2_low()
728 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
731 * Poll DFS Register - 0x1528 [3] - DfsAtSR - in ddr3_dfs_high_2_low()
732 * All DRAM devices on all ranks are in self refresh mode - DFS can in ddr3_dfs_high_2_low()
740 /* [0] - Enable Dunit to crossbar retry */ in ddr3_dfs_high_2_low()
741 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_high_2_low()
744 /* 0x1600 - PHY lock mask register */ in ddr3_dfs_high_2_low()
749 /* 0x1670 - PHY lock mask register */ in ddr3_dfs_high_2_low()
754 DEBUG_DFS_C("DDR3 - DFS - High To Low - Ended successfuly - new Frequency - ", in ddr3_dfs_high_2_low()
764 * Args: freq - target frequency
766 * Returns: MV_OK - success, MV_FAIL - fail
775 DEBUG_DFS_C("DDR3 - DFS - Low To High - Starting DFS procedure to Frequency - ", in ddr3_dfs_low_2_high()
778 /* target frequency - freq */ in ddr3_dfs_low_2_high()
787 /* Configure - DRAM DLL final state after DFS is complete - Enable */ in ddr3_dfs_low_2_high()
789 /* [0] - DfsDllNextState - Enable */ in ddr3_dfs_low_2_high()
791 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
794 * Configure - XBAR Retry response during Block to enable in ddr3_dfs_low_2_high()
795 * internal access - Disable in ddr3_dfs_low_2_high()
798 /* [0] - RetryMask - Disable */ in ddr3_dfs_low_2_high()
800 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_low_2_high()
803 /* Configure - Block new external transactions - Enable */ in ddr3_dfs_low_2_high()
805 reg |= (1 << REG_DFS_BLOCK_OFFS); /* [1] - DfsBlock - Enable */ in ddr3_dfs_low_2_high()
806 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
808 /* Configure - Move DRAM into Self Refresh */ in ddr3_dfs_low_2_high()
810 reg |= (1 << REG_DFS_SR_OFFS); /* [2] - DfsSR - Enable */ in ddr3_dfs_low_2_high()
811 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
813 /* Poll - Wait for Self Refresh indication */ in ddr3_dfs_low_2_high()
816 } while (reg == 0x0); /* 0x1528 [3] - DfsAtSR - Wait for '1' */ in ddr3_dfs_low_2_high()
848 reg |= (freq_par << 8); /* full Integer ratio from PLL-out to ddr-clk */ in ddr3_dfs_low_2_high()
869 * Initial Setup - assure that the "load new ratio" is clear (bit 24) in ddr3_dfs_low_2_high()
875 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_low_2_high()
882 /* 0x18704 - CPU Div CLK control 0 */ in ddr3_dfs_low_2_high()
888 /* full Integer ratio from PLL-out to ddr-clk */ in ddr3_dfs_low_2_high()
889 /* 0x1870C - CPU Div CLK control 3 register */ in ddr3_dfs_low_2_high()
894 * All the rest are kept as is (forced, but could be read-modify-write). in ddr3_dfs_low_2_high()
913 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_low_2_high()
919 * Poll Div CLK status 0 register - indication that the clocks in ddr3_dfs_low_2_high()
920 * are active - 0x18718 [8] in ddr3_dfs_low_2_high()
932 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_low_2_high()
938 /* Configure - Select normal clock for the DDR PHY - Disable */ in ddr3_dfs_low_2_high()
940 /* [16] - ddr_phy_trn_clk_sel - Disable */ in ddr3_dfs_low_2_high()
942 /* 0x18488 - DRAM Init control status register */ in ddr3_dfs_low_2_high()
947 * Configure - Set Correct Ratio - according to target ratio in ddr3_dfs_low_2_high()
948 * parameter - 2:1/1:1 in ddr3_dfs_low_2_high()
952 * [15] - Phy2UnitClkRatio = 1 - Set 2:1 Ratio between in ddr3_dfs_low_2_high()
959 * [15] - Phy2UnitClkRatio = 0 - Set 1:1 Ratio between in ddr3_dfs_low_2_high()
965 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Register */ in ddr3_dfs_low_2_high()
967 /* Configure - 2T Mode - Restore original configuration */ in ddr3_dfs_low_2_high()
969 /* [3:4] 2T - Restore value */ in ddr3_dfs_low_2_high()
971 reg |= ((dram_info->mode_2t & REG_DUNIT_CTRL_LOW_2T_MASK) << in ddr3_dfs_low_2_high()
973 /* 0x1404 - DDR Controller Control Low Register */ in ddr3_dfs_low_2_high()
976 /* Configure - Restore CL and CWL - MRS Commands */ in ddr3_dfs_low_2_high()
982 if (dram_info->target_frequency == 0x8) in ddr3_dfs_low_2_high()
987 tmp = ddr3_cl_to_valid_cl(dram_info->cl); in ddr3_dfs_low_2_high()
990 /* [8] - DfsCLNextState */ in ddr3_dfs_low_2_high()
993 /* [12] - DfsCWLNextState */ in ddr3_dfs_low_2_high()
997 /* [12] - DfsCWLNextState */ in ddr3_dfs_low_2_high()
998 reg |= (((dram_info->cwl) & REG_DFS_CWL_NEXT_STATE_MASK) << in ddr3_dfs_low_2_high()
1001 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1003 /* Optional - Configure - DDR3_Rtt_nom_CS# */ in ddr3_dfs_low_2_high()
1005 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_low_2_high()
1009 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_dfs_low_2_high()
1015 /* Configure - Reset ADLLs - Set Reset */ in ddr3_dfs_low_2_high()
1017 /* [31:30]] - reset pup data ctrl ADLL */ in ddr3_dfs_low_2_high()
1018 /* 0x15EC - DRAM PHY Config Register */ in ddr3_dfs_low_2_high()
1021 /* Configure - Reset ADLLs - Release Reset */ in ddr3_dfs_low_2_high()
1023 /* [31:30] - normal pup data ctrl ADLL */ in ddr3_dfs_low_2_high()
1024 /* 0x15EC - DRAM PHY Config register */ in ddr3_dfs_low_2_high()
1027 /* Poll - Wait for APLL + ADLLs lock on new frequency */ in ddr3_dfs_low_2_high()
1031 /* 0x1674 [10:0] - Phy lock status Register */ in ddr3_dfs_low_2_high()
1034 /* Configure - Reset the PHY SDR clock divider */ in ddr3_dfs_low_2_high()
1036 /* Pup Reset Divider B - Set Reset */ in ddr3_dfs_low_2_high()
1037 /* [28] - DataPupRdRST = 0 */ in ddr3_dfs_low_2_high()
1040 /* [28] - DataPupRdRST = 1 */ in ddr3_dfs_low_2_high()
1043 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1046 /* Pup Reset Divider B - Release Reset */ in ddr3_dfs_low_2_high()
1047 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1051 /* Configure - Reset the PHY Read FIFO and Write channels - Set Reset */ in ddr3_dfs_low_2_high()
1053 /* [30:29] = 0 - Data Pup R/W path reset */ in ddr3_dfs_low_2_high()
1054 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1058 * Configure - DRAM Data PHY Read [30], Write [29] path reset - in ddr3_dfs_low_2_high()
1062 /* [30:29] = '11' - Data Pup R/W path reset */ in ddr3_dfs_low_2_high()
1063 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1067 if (dram_info->reg_dimm) { in ddr3_dfs_low_2_high()
1069 * Configure - Change register DRAM operating speed in ddr3_dfs_low_2_high()
1070 * (DDR3-1333 / DDR3-1600) - CWA_RC in ddr3_dfs_low_2_high()
1076 * Configure - Change register DRAM operating speed in ddr3_dfs_low_2_high()
1077 * (DDR3-800) - CWA_DATA in ddr3_dfs_low_2_high()
1083 * Configure - Change register DRAM operating speed in ddr3_dfs_low_2_high()
1084 * (DDR3-1066) - CWA_DATA in ddr3_dfs_low_2_high()
1090 * Configure - Change register DRAM operating speed in ddr3_dfs_low_2_high()
1091 * (DDR3-1333) - CWA_DATA in ddr3_dfs_low_2_high()
1097 * Configure - Change register DRAM operating speed in ddr3_dfs_low_2_high()
1098 * (DDR3-1600) - CWA_DATA in ddr3_dfs_low_2_high()
1104 /* Configure - Set Delay - tSTAB */ in ddr3_dfs_low_2_high()
1106 /* Configure - Issue CWA command with the above parameters */ in ddr3_dfs_low_2_high()
1110 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1113 /* Poll - Wait for CWA operation completion */ in ddr3_dfs_low_2_high()
1120 /* Configure - Exit Self Refresh */ in ddr3_dfs_low_2_high()
1121 /* [2] - DfsSR */ in ddr3_dfs_low_2_high()
1123 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1126 * Poll - DFS Register - 0x1528 [3] - DfsAtSR - All DRAM in ddr3_dfs_low_2_high()
1133 /* Configure - Issue Refresh command */ in ddr3_dfs_low_2_high()
1134 /* [3-0] = 0x2 - Refresh Command, [11-8] - enabled Cs */ in ddr3_dfs_low_2_high()
1137 if (dram_info->cs_ena & (1 << cs)) in ddr3_dfs_low_2_high()
1141 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1144 /* Poll - Wait for Refresh operation completion */ in ddr3_dfs_low_2_high()
1147 /* Configure - Block new external transactions - Disable */ in ddr3_dfs_low_2_high()
1149 reg &= ~(1 << REG_DFS_BLOCK_OFFS); /* [1] - DfsBlock - Disable */ in ddr3_dfs_low_2_high()
1150 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1153 * Configure - XBAR Retry response during Block to enable in ddr3_dfs_low_2_high()
1154 * internal access - Disable in ddr3_dfs_low_2_high()
1157 /* [0] - RetryMask - Enable */ in ddr3_dfs_low_2_high()
1159 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_low_2_high()
1163 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_low_2_high()
1164 /* Configure - Set CL */ in ddr3_dfs_low_2_high()
1171 tmp = ddr3_cl_to_valid_cl(dram_info->cl); in ddr3_dfs_low_2_high()
1177 /* Configure - Set CWL */ in ddr3_dfs_low_2_high()
1184 reg |= ((dram_info->cwl) << REG_DDR3_MR2_CWL_OFFS); in ddr3_dfs_low_2_high()
1190 DEBUG_DFS_C("DDR3 - DFS - Low To High - Ended successfuly - new Frequency - ", in ddr3_dfs_low_2_high()
1202 DEBUG_DFS_C("DDR3 - DFS - Low To High - Starting DFS procedure to Frequency - ", in ddr3_dfs_low_2_high()
1205 /* target frequency - freq */ in ddr3_dfs_low_2_high()
1211 /* 0x1600 - PHY lock mask register */ in ddr3_dfs_low_2_high()
1216 /* 0x1670 - PHY lock mask register */ in ddr3_dfs_low_2_high()
1222 reg = reg_read(REG_DFS_ADDR); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1223 /* [4] - Disable - reconfig MR registers after DFS_ERG */ in ddr3_dfs_low_2_high()
1225 /* [0] - Enable - DRAM DLL after DFS */ in ddr3_dfs_low_2_high()
1226 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1229 /* [0] - disable */ in ddr3_dfs_low_2_high()
1231 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_low_2_high()
1235 /* [1] - DFS Block enable */ in ddr3_dfs_low_2_high()
1237 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1240 /* [2] - DFS Self refresh enable */ in ddr3_dfs_low_2_high()
1242 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1245 * Poll DFS Register - All DRAM devices on all ranks are in in ddr3_dfs_low_2_high()
1246 * self refresh mode - DFS can be executed afterwards in ddr3_dfs_low_2_high()
1248 /* 0x1528 [3] - DfsAtSR */ in ddr3_dfs_low_2_high()
1254 * Set Correct Ratio - if freq>MARGIN_FREQ use 2:1 ratio in ddr3_dfs_low_2_high()
1258 /* [15] = 1 - Set 2:1 Ratio between Dunit and Phy */ in ddr3_dfs_low_2_high()
1262 /* [15] = 0 - Set 1:1 Ratio between Dunit and Phy */ in ddr3_dfs_low_2_high()
1266 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Register */ in ddr3_dfs_low_2_high()
1271 * [29] - training logic request DFS, [28:27] - in ddr3_dfs_low_2_high()
1275 /* 0x18488 - DRAM Init control status register */ in ddr3_dfs_low_2_high()
1282 * Initial Setup - assure that the "load new ratio" is clear (bit 24) in ddr3_dfs_low_2_high()
1287 /* 0x18700 - CPU Div CLK control 0 */ in ddr3_dfs_low_2_high()
1294 /* 0x18704 - CPU Div CLK control 0 */ in ddr3_dfs_low_2_high()
1300 /* Full Integer ratio from PLL-out to ddr-clk */ in ddr3_dfs_low_2_high()
1301 /* 0x1870C - CPU Div CLK control 3 register */ in ddr3_dfs_low_2_high()
1306 * All the rest are kept as is (forced, but could be read-modify-write). in ddr3_dfs_low_2_high()
1327 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_low_2_high()
1333 * Poll Div CLK status 0 register - indication that the clocks are in ddr3_dfs_low_2_high()
1334 * active - 0x18718 [8] in ddr3_dfs_low_2_high()
1346 /* 0x18700 - CPU Div CLK control 0 register */ in ddr3_dfs_low_2_high()
1352 /* Pup Reset Divider B - Set Reset */ in ddr3_dfs_low_2_high()
1353 /* [28] = 0 - Pup Reset Divider B */ in ddr3_dfs_low_2_high()
1355 /* [28] = 1 - Pup Reset Divider B */ in ddr3_dfs_low_2_high()
1357 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1360 /* Pup Reset Divider B - Release Reset */ in ddr3_dfs_low_2_high()
1361 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1365 /* DRAM Data PHYs ADLL Reset - Set Reset */ in ddr3_dfs_low_2_high()
1367 /* [31:30]] - reset pup data ctrl ADLL */ in ddr3_dfs_low_2_high()
1368 /* 0x15EC - DRAM PHY Config Register */ in ddr3_dfs_low_2_high()
1373 /* APLL lock indication - Poll Phy lock status Register - 0x1674 [9] */ in ddr3_dfs_low_2_high()
1379 /* DRAM Data PHYs ADLL Reset - Release Reset */ in ddr3_dfs_low_2_high()
1381 /* [31:30] - normal pup data ctrl ADLL */ in ddr3_dfs_low_2_high()
1382 /* 0x15EC - DRAM PHY Config register */ in ddr3_dfs_low_2_high()
1388 * APLL lock indication - Poll Phy lock status Register - 0x1674 [11:0] in ddr3_dfs_low_2_high()
1395 /* DRAM Data PHY Read [30], Write [29] path reset - Set Reset */ in ddr3_dfs_low_2_high()
1397 /* [30:29] = 0 - Data Pup R/W path reset */ in ddr3_dfs_low_2_high()
1398 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1401 /* DRAM Data PHY Read [30], Write [29] path reset - Release Reset */ in ddr3_dfs_low_2_high()
1403 /* [30:29] = '11' - Data Pup R/W path reset */ in ddr3_dfs_low_2_high()
1404 /* 0x1400 - SDRAM Configuration register */ in ddr3_dfs_low_2_high()
1409 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1411 /* [2] - DFS Self refresh disable */ in ddr3_dfs_low_2_high()
1413 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1416 * Poll DFS Register - 0x1528 [3] - DfsAtSR - All DRAM devices on in ddr3_dfs_low_2_high()
1426 /* Configure - 2T Mode - Restore original configuration */ in ddr3_dfs_low_2_high()
1427 /* [3:4] 2T - Restore value */ in ddr3_dfs_low_2_high()
1429 reg |= ((dram_info->mode_2t & REG_DUNIT_CTRL_LOW_2T_MASK) << in ddr3_dfs_low_2_high()
1436 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dfs_low_2_high()
1438 /* DLL Enable */ in ddr3_dfs_low_2_high()
1446 * [3-0] = 0x4 - MR1 Command, [11-8] - in ddr3_dfs_low_2_high()
1449 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1452 /* Poll - Wait for Refresh operation completion */ in ddr3_dfs_low_2_high()
1455 /* DLL Reset - MR0 */ in ddr3_dfs_low_2_high()
1463 * [3-0] = 0x4 - MR1 Command, [11-8] - in ddr3_dfs_low_2_high()
1466 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1469 /* Poll - Wait for Refresh operation completion */ in ddr3_dfs_low_2_high()
1478 tmp = ddr3_cl_to_valid_cl(dram_info->cl) & 0xF; in ddr3_dfs_low_2_high()
1486 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1489 /* Poll - Wait for Refresh operation completion */ in ddr3_dfs_low_2_high()
1496 reg |= dram_info->cwl << REG_DDR3_MR2_CWL_OFFS; in ddr3_dfs_low_2_high()
1500 /* 0x1418 - SDRAM Operation Register */ in ddr3_dfs_low_2_high()
1503 /* Poll - Wait for Refresh operation completion */ in ddr3_dfs_low_2_high()
1510 reg |= (dram_info->cl << in ddr3_dfs_low_2_high()
1518 reg |= ((dram_info->cl + 1) << in ddr3_dfs_low_2_high()
1524 /* Enable ODT on DLL-on mode */ in ddr3_dfs_low_2_high()
1527 /* [1] - DFS Block disable */ in ddr3_dfs_low_2_high()
1529 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1532 /* 0x1600 - PHY lock mask register */ in ddr3_dfs_low_2_high()
1538 /* 0x1670 - PHY lock mask register */ in ddr3_dfs_low_2_high()
1543 reg = reg_read(REG_METAL_MASK_ADDR) | (1 << 0); /* [0] - disable */ in ddr3_dfs_low_2_high()
1544 /* 0x14B0 - Dunit MMask Register */ in ddr3_dfs_low_2_high()
1547 DEBUG_DFS_C("DDR3 - DFS - Low To High - Ended successfuly - new Frequency - ", in ddr3_dfs_low_2_high()