Lines Matching +full:dll +full:- +full:config
66 writeb(value, addr + (1 << shift) - 1); in serial_out_shift()
83 return readb(addr + (1 << shift) - 1); in serial_in_shift()
97 struct ns16550_platdata *plat = port->plat; in ns16550_writeb()
100 offset *= 1 << plat->reg_shift; in ns16550_writeb()
101 addr = (unsigned char *)plat->base + offset; in ns16550_writeb()
105 * these options at run-time, so use the existing CONFIG options. in ns16550_writeb()
107 serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); in ns16550_writeb()
112 struct ns16550_platdata *plat = port->plat; in ns16550_readb()
115 offset *= 1 << plat->reg_shift; in ns16550_readb()
116 addr = (unsigned char *)plat->base + offset; in ns16550_readb()
118 return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); in ns16550_readb()
123 struct ns16550_platdata *plat = port->plat; in ns16550_getfcr()
125 return plat->fcr; in ns16550_getfcr()
131 (unsigned char *)addr - (unsigned char *)com_port, value)
134 (unsigned char *)addr - (unsigned char *)com_port)
152 int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE; in NS16550_setbrg()
154 serial_out(UART_LCR_BKSE | lcr_val, &com_port->lcr); in NS16550_setbrg()
155 serial_out(baud_divisor & 0xff, &com_port->dll); in NS16550_setbrg()
156 serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); in NS16550_setbrg()
157 serial_out(lcr_val, &com_port->lcr); in NS16550_setbrg()
169 if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE)) in NS16550_init()
171 if (baud_divisor != -1) in NS16550_init()
173 serial_out(0, &com_port->mdr1); in NS16550_init()
177 while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT)) in NS16550_init()
180 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); in NS16550_init()
182 serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ in NS16550_init()
185 serial_out(UART_MCRVAL, &com_port->mcr); in NS16550_init()
186 serial_out(ns16550_getfcr(com_port), &com_port->fcr); in NS16550_init()
187 /* initialize serial config to 8N1 before writing baudrate */ in NS16550_init()
188 serial_out(UART_LCRVAL, &com_port->lcr); in NS16550_init()
189 if (baud_divisor != -1) in NS16550_init()
194 serial_out(0, &com_port->mdr1); in NS16550_init()
197 serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); in NS16550_init()
204 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); in NS16550_reinit()
206 serial_out(UART_MCRVAL, &com_port->mcr); in NS16550_reinit()
207 serial_out(ns16550_getfcr(com_port), &com_port->fcr); in NS16550_reinit()
214 while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0) in NS16550_putc()
216 serial_out(c, &com_port->thr); in NS16550_putc()
231 while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) { in NS16550_getc()
238 return serial_in(&com_port->rbr); in NS16550_getc()
243 return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0; in NS16550_tstc()
265 serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); in _debug_uart_init()
266 serial_dout(&com_port->mcr, UART_MCRVAL); in _debug_uart_init()
267 serial_dout(&com_port->fcr, UART_FCR_DEFVAL); in _debug_uart_init()
269 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); in _debug_uart_init()
270 serial_dout(&com_port->dll, baud_divisor & 0xff); in _debug_uart_init()
271 serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); in _debug_uart_init()
272 serial_dout(&com_port->lcr, UART_LCRVAL); in _debug_uart_init()
279 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); in NS16550_read_baud_divisor()
280 ret = serial_din(&com_port->dll) & 0xff; in NS16550_read_baud_divisor()
281 ret |= (serial_din(&com_port->dlm) & 0xff) << 8; in NS16550_read_baud_divisor()
282 serial_dout(&com_port->lcr, UART_LCRVAL); in NS16550_read_baud_divisor()
291 while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) { in _debug_uart_putc()
297 serial_dout(&com_port->thr, ch); in _debug_uart_putc()
309 if (!(serial_in(&com_port->lsr) & UART_LSR_THRE)) in ns16550_serial_putc()
310 return -EAGAIN; in ns16550_serial_putc()
311 serial_out(ch, &com_port->thr); in ns16550_serial_putc()
330 return (serial_in(&com_port->lsr) & UART_LSR_DR) ? 1 : 0; in ns16550_serial_pending()
332 return (serial_in(&com_port->lsr) & UART_LSR_THRE) ? 0 : 1; in ns16550_serial_pending()
339 if (!(serial_in(&com_port->lsr) & UART_LSR_DR)) in ns16550_serial_getc()
340 return -EAGAIN; in ns16550_serial_getc()
342 return serial_in(&com_port->rbr); in ns16550_serial_getc()
348 struct ns16550_platdata *plat = com_port->plat; in ns16550_serial_setbrg()
351 clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate); in ns16550_serial_setbrg()
367 * only parity config is implemented, check if other serial settings in ns16550_serial_setconfig()
371 return -ENOTSUPP; /* not supported in driver*/ in ns16550_serial_setconfig()
384 return -ENOTSUPP; /* not supported in driver*/ in ns16550_serial_setconfig()
387 serial_out(lcr_val, &com_port->lcr); in ns16550_serial_setconfig()
395 struct ns16550_platdata *plat = com_port->plat; in ns16550_serial_getinfo()
397 info->type = SERIAL_CHIP_16550_COMPATIBLE; in ns16550_serial_getinfo()
399 info->addr_space = SERIAL_ADDRESS_SPACE_IO; in ns16550_serial_getinfo()
401 info->addr_space = SERIAL_ADDRESS_SPACE_MEMORY; in ns16550_serial_getinfo()
403 info->addr = plat->base; in ns16550_serial_getinfo()
404 info->reg_width = plat->reg_width; in ns16550_serial_getinfo()
405 info->reg_shift = plat->reg_shift; in ns16550_serial_getinfo()
406 info->reg_offset = plat->reg_offset; in ns16550_serial_getinfo()
420 com_port->plat = dev_get_platdata(dev); in ns16550_serial_probe()
421 NS16550_init(com_port, -1); in ns16550_serial_probe()
436 struct ns16550_platdata *plat = dev->platdata; in ns16550_serial_ofdata_to_platdata()
451 /* we prefer to use a memory-mapped register */ in ns16550_serial_ofdata_to_platdata()
452 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev), in ns16550_serial_ofdata_to_platdata()
456 /* try if there is any i/o-mapped register */ in ns16550_serial_ofdata_to_platdata()
457 ret = fdtdec_get_pci_addr(gd->fdt_blob, in ns16550_serial_ofdata_to_platdata()
474 return -EINVAL; in ns16550_serial_ofdata_to_platdata()
477 plat->base = addr; in ns16550_serial_ofdata_to_platdata()
479 plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE); in ns16550_serial_ofdata_to_platdata()
482 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); in ns16550_serial_ofdata_to_platdata()
483 plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); in ns16550_serial_ofdata_to_platdata()
484 plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1); in ns16550_serial_ofdata_to_platdata()
490 plat->clock = err; in ns16550_serial_ofdata_to_platdata()
491 } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { in ns16550_serial_ofdata_to_platdata()
496 if (!plat->clock) in ns16550_serial_ofdata_to_platdata()
497 plat->clock = dev_read_u32_default(dev, "clock-frequency", in ns16550_serial_ofdata_to_platdata()
499 if (!plat->clock) { in ns16550_serial_ofdata_to_platdata()
501 return -EINVAL; in ns16550_serial_ofdata_to_platdata()
504 plat->fcr = UART_FCR_DEFVAL; in ns16550_serial_ofdata_to_platdata()
506 plat->fcr |= UART_FCR_UME; in ns16550_serial_ofdata_to_platdata()
530 { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 },
531 { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 },
532 { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },