1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 29ffa7a35SPurna Chandra Mandal /* 39ffa7a35SPurna Chandra Mandal * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com> 49ffa7a35SPurna Chandra Mandal * 59ffa7a35SPurna Chandra Mandal */ 69ffa7a35SPurna Chandra Mandal 79ffa7a35SPurna Chandra Mandal #ifndef __MICROCHIP_DDR2_REGS_H 89ffa7a35SPurna Chandra Mandal #define __MICROCHIP_DDR2_REGS_H 99ffa7a35SPurna Chandra Mandal 109ffa7a35SPurna Chandra Mandal #include <linux/bitops.h> 119ffa7a35SPurna Chandra Mandal 129ffa7a35SPurna Chandra Mandal /* DDR2 Controller */ 139ffa7a35SPurna Chandra Mandal struct ddr2_ctrl_regs { 149ffa7a35SPurna Chandra Mandal u32 tsel; 159ffa7a35SPurna Chandra Mandal u32 minlim; 169ffa7a35SPurna Chandra Mandal u32 reqprd; 179ffa7a35SPurna Chandra Mandal u32 mincmd; 189ffa7a35SPurna Chandra Mandal u32 memcon; 199ffa7a35SPurna Chandra Mandal u32 memcfg0; 209ffa7a35SPurna Chandra Mandal u32 memcfg1; 219ffa7a35SPurna Chandra Mandal u32 memcfg2; 229ffa7a35SPurna Chandra Mandal u32 memcfg3; 239ffa7a35SPurna Chandra Mandal u32 memcfg4; 249ffa7a35SPurna Chandra Mandal u32 refcfg; 259ffa7a35SPurna Chandra Mandal u32 pwrcfg; 269ffa7a35SPurna Chandra Mandal u32 dlycfg0; 279ffa7a35SPurna Chandra Mandal u32 dlycfg1; 289ffa7a35SPurna Chandra Mandal u32 dlycfg2; 299ffa7a35SPurna Chandra Mandal u32 dlycfg3; 309ffa7a35SPurna Chandra Mandal u32 odtcfg; 319ffa7a35SPurna Chandra Mandal u32 xfercfg; 329ffa7a35SPurna Chandra Mandal u32 cmdissue; 339ffa7a35SPurna Chandra Mandal u32 odtencfg; 349ffa7a35SPurna Chandra Mandal u32 memwidth; 359ffa7a35SPurna Chandra Mandal u32 unused[11]; 369ffa7a35SPurna Chandra Mandal u32 cmd10[16]; 379ffa7a35SPurna Chandra Mandal u32 cmd20[16]; 389ffa7a35SPurna Chandra Mandal }; 399ffa7a35SPurna Chandra Mandal 409ffa7a35SPurna Chandra Mandal /* Arbiter Config */ 419ffa7a35SPurna Chandra Mandal #define MIN_LIM_WIDTH 5 429ffa7a35SPurna Chandra Mandal #define RQST_PERIOD_WIDTH 8 439ffa7a35SPurna Chandra Mandal #define MIN_CMDACPT_WIDTH 8 449ffa7a35SPurna Chandra Mandal 459ffa7a35SPurna Chandra Mandal /* Refresh Config */ 469ffa7a35SPurna Chandra Mandal #define REFCNT_CLK(x) (x) 479ffa7a35SPurna Chandra Mandal #define REFDLY_CLK(x) ((x) << 16) 489ffa7a35SPurna Chandra Mandal #define MAX_PEND_REF(x) ((x) << 24) 499ffa7a35SPurna Chandra Mandal 509ffa7a35SPurna Chandra Mandal /* Power Config */ 519ffa7a35SPurna Chandra Mandal #define PRECH_PWR_DN_ONLY(x) ((x) << 22) 529ffa7a35SPurna Chandra Mandal #define SELF_REF_DLY(x) ((x) << 12) 539ffa7a35SPurna Chandra Mandal #define PWR_DN_DLY(x) ((x) << 4) 549ffa7a35SPurna Chandra Mandal #define EN_AUTO_SELF_REF(x) ((x) << 3) 559ffa7a35SPurna Chandra Mandal #define EN_AUTO_PWR_DN(x) ((x) << 2) 569ffa7a35SPurna Chandra Mandal #define ERR_CORR_EN(x) ((x) << 1) 579ffa7a35SPurna Chandra Mandal #define ECC_EN(x) (x) 589ffa7a35SPurna Chandra Mandal 599ffa7a35SPurna Chandra Mandal /* Memory Width */ 609ffa7a35SPurna Chandra Mandal #define HALF_RATE_MODE BIT(3) 619ffa7a35SPurna Chandra Mandal 629ffa7a35SPurna Chandra Mandal /* Delay Config */ 639ffa7a35SPurna Chandra Mandal #define ODTWLEN(x) ((x) << 20) 649ffa7a35SPurna Chandra Mandal #define ODTRLEN(x) ((x) << 16) 659ffa7a35SPurna Chandra Mandal #define ODTWDLY(x) ((x) << 12) 669ffa7a35SPurna Chandra Mandal #define ODTRDLY(x) ((x) << 8) 679ffa7a35SPurna Chandra Mandal 689ffa7a35SPurna Chandra Mandal /* Xfer Config */ 699ffa7a35SPurna Chandra Mandal #define BIG_ENDIAN(x) ((x) << 31) 709ffa7a35SPurna Chandra Mandal #define MAX_BURST(x) ((x) << 24) 719ffa7a35SPurna Chandra Mandal #define RDATENDLY(x) ((x) << 16) 729ffa7a35SPurna Chandra Mandal #define NXDATAVDLY(x) ((x) << 4) 739ffa7a35SPurna Chandra Mandal #define NXTDATRQDLY(x) ((x) << 0) 749ffa7a35SPurna Chandra Mandal 759ffa7a35SPurna Chandra Mandal /* Host Commands */ 769ffa7a35SPurna Chandra Mandal #define IDLE_NOP 0x00ffffff 779ffa7a35SPurna Chandra Mandal #define PRECH_ALL_CMD 0x00fff401 789ffa7a35SPurna Chandra Mandal #define REF_CMD 0x00fff801 799ffa7a35SPurna Chandra Mandal #define LOAD_MODE_CMD 0x00fff001 809ffa7a35SPurna Chandra Mandal #define CKE_LOW 0x00ffeffe 819ffa7a35SPurna Chandra Mandal 829ffa7a35SPurna Chandra Mandal #define NUM_HOST_CMDS 12 839ffa7a35SPurna Chandra Mandal 849ffa7a35SPurna Chandra Mandal /* Host CMD Issue */ 859ffa7a35SPurna Chandra Mandal #define CMD_VALID BIT(4) 869ffa7a35SPurna Chandra Mandal #define NUMHOSTCMD(x) (x) 879ffa7a35SPurna Chandra Mandal 889ffa7a35SPurna Chandra Mandal /* Memory Control */ 899ffa7a35SPurna Chandra Mandal #define INIT_DONE BIT(1) 909ffa7a35SPurna Chandra Mandal #define INIT_START BIT(0) 919ffa7a35SPurna Chandra Mandal 929ffa7a35SPurna Chandra Mandal /* Address Control */ 939ffa7a35SPurna Chandra Mandal #define EN_AUTO_PRECH 0 949ffa7a35SPurna Chandra Mandal #define SB_PRI 1 959ffa7a35SPurna Chandra Mandal 969ffa7a35SPurna Chandra Mandal /* DDR2 Phy Register */ 979ffa7a35SPurna Chandra Mandal struct ddr2_phy_regs { 989ffa7a35SPurna Chandra Mandal u32 scl_start; 999ffa7a35SPurna Chandra Mandal u32 unused1[2]; 1009ffa7a35SPurna Chandra Mandal u32 scl_latency; 1019ffa7a35SPurna Chandra Mandal u32 unused2[2]; 1029ffa7a35SPurna Chandra Mandal u32 scl_config_1; 1039ffa7a35SPurna Chandra Mandal u32 scl_config_2; 1049ffa7a35SPurna Chandra Mandal u32 pad_ctrl; 1059ffa7a35SPurna Chandra Mandal u32 dll_recalib; 1069ffa7a35SPurna Chandra Mandal }; 1079ffa7a35SPurna Chandra Mandal 1089ffa7a35SPurna Chandra Mandal /* PHY PAD CONTROL */ 1099ffa7a35SPurna Chandra Mandal #define ODT_SEL BIT(0) 1109ffa7a35SPurna Chandra Mandal #define ODT_EN BIT(1) 1119ffa7a35SPurna Chandra Mandal #define DRIVE_SEL(x) ((x) << 2) 1129ffa7a35SPurna Chandra Mandal #define ODT_PULLDOWN(x) ((x) << 4) 1139ffa7a35SPurna Chandra Mandal #define ODT_PULLUP(x) ((x) << 6) 1149ffa7a35SPurna Chandra Mandal #define EXTRA_OEN_CLK(x) ((x) << 8) 1159ffa7a35SPurna Chandra Mandal #define NOEXT_DLL BIT(9) 1169ffa7a35SPurna Chandra Mandal #define DLR_DFT_WRCMD BIT(13) 1179ffa7a35SPurna Chandra Mandal #define HALF_RATE BIT(14) 1189ffa7a35SPurna Chandra Mandal #define DRVSTR_PFET(x) ((x) << 16) 1199ffa7a35SPurna Chandra Mandal #define DRVSTR_NFET(x) ((x) << 20) 1209ffa7a35SPurna Chandra Mandal #define RCVR_EN BIT(28) 1219ffa7a35SPurna Chandra Mandal #define PREAMBLE_DLY(x) ((x) << 29) 1229ffa7a35SPurna Chandra Mandal 1239ffa7a35SPurna Chandra Mandal /* PHY DLL RECALIBRATE */ 1249ffa7a35SPurna Chandra Mandal #define RECALIB_CNT(x) ((x) << 8) 1259ffa7a35SPurna Chandra Mandal #define DISABLE_RECALIB(x) ((x) << 26) 1269ffa7a35SPurna Chandra Mandal #define DELAY_START_VAL(x) ((x) << 28) 1279ffa7a35SPurna Chandra Mandal 1289ffa7a35SPurna Chandra Mandal /* PHY SCL CONFIG1 */ 1299ffa7a35SPurna Chandra Mandal #define SCL_BURST8 BIT(0) 1309ffa7a35SPurna Chandra Mandal #define SCL_DDR_CONNECTED BIT(1) 1319ffa7a35SPurna Chandra Mandal #define SCL_RCAS_LAT(x) ((x) << 4) 1329ffa7a35SPurna Chandra Mandal #define SCL_ODTCSWW BIT(24) 1339ffa7a35SPurna Chandra Mandal 1349ffa7a35SPurna Chandra Mandal /* PHY SCL CONFIG2 */ 1359ffa7a35SPurna Chandra Mandal #define SCL_CSEN BIT(0) 1369ffa7a35SPurna Chandra Mandal #define SCL_WCAS_LAT(x) ((x) << 8) 1379ffa7a35SPurna Chandra Mandal 1389ffa7a35SPurna Chandra Mandal /* PHY SCL Latency */ 1399ffa7a35SPurna Chandra Mandal #define SCL_CAPCLKDLY(x) ((x) << 0) 1409ffa7a35SPurna Chandra Mandal #define SCL_DDRCLKDLY(x) ((x) << 4) 1419ffa7a35SPurna Chandra Mandal 1429ffa7a35SPurna Chandra Mandal /* PHY SCL START */ 1439ffa7a35SPurna Chandra Mandal #define SCL_START BIT(28) 1449ffa7a35SPurna Chandra Mandal #define SCL_EN BIT(26) 1459ffa7a35SPurna Chandra Mandal #define SCL_LUBPASS (BIT(1) | BIT(0)) 1469ffa7a35SPurna Chandra Mandal 1479ffa7a35SPurna Chandra Mandal #endif /* __MICROCHIP_DDR2_REGS_H */ 148