Lines Matching +full:dll +full:- +full:config
1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
12 #include <dt-structs.h>
102 rk_clrsetreg(&cru->cru_softrst_con[10], in ddr_reset()
115 rk_clrsetreg(&cru->cru_softrst_con[10], in ddr_phy_ctl_reset()
127 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
129 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
132 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
134 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
150 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
152 setbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
153 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); in phy_dll_bypass_set()
155 setbits_le32(&publ->datx8[i].dxdllcr, in phy_dll_bypass_set()
158 setbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
160 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
161 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); in phy_dll_bypass_set()
163 clrbits_le32(&publ->datx8[i].dxdllcr, in phy_dll_bypass_set()
167 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
173 writel(DFI_INIT_START, &pctl->dfistcfg0); in dfi_cfg()
175 &pctl->dfistcfg1); in dfi_cfg()
176 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); in dfi_cfg()
178 &pctl->dfilpcfg0); in dfi_cfg()
180 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); in dfi_cfg()
181 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); in dfi_cfg()
182 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); in dfi_cfg()
183 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); in dfi_cfg()
184 writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); in dfi_cfg()
185 writel(1, &pctl->dfitphyupdtype0); in dfi_cfg()
189 &pctl->dfiodtcfg); in dfi_cfg()
191 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); in dfi_cfg()
193 writel(0, &pctl->dfiupdcfg); in dfi_cfg()
204 rk_clrsetreg(&grf->soc_con0, in ddr_set_enable()
217 rk_clrsetreg(&grf->soc_con0, mask, val); in ddr_set_ddr3_mode()
231 rk_clrsetreg(&grf->soc_con2, mask, in ddr_set_en_bst_odt()
245 burstlen = (sdram_params->base.noc_timing >> 18) & 0x7; in pctl_cfg()
246 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, in pctl_cfg()
247 sizeof(sdram_params->pctl_timing)); in pctl_cfg()
248 switch (sdram_params->base.dramtype) { in pctl_cfg()
250 writel(sdram_params->pctl_timing.tcl - 1, in pctl_cfg()
251 &pctl->dfitrddataen); in pctl_cfg()
252 writel(sdram_params->pctl_timing.tcwl, in pctl_cfg()
253 &pctl->dfitphywrlat); in pctl_cfg()
257 (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST | in pctl_cfg()
259 &pctl->mcfg); in pctl_cfg()
263 sdram_params->base.odt); in pctl_cfg()
266 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { in pctl_cfg()
267 writel(sdram_params->pctl_timing.tcl - 3, in pctl_cfg()
268 &pctl->dfitrddataen); in pctl_cfg()
270 writel(sdram_params->pctl_timing.tcl - 2, in pctl_cfg()
271 &pctl->dfitrddataen); in pctl_cfg()
273 writel(sdram_params->pctl_timing.tcwl - 1, in pctl_cfg()
274 &pctl->dfitphywrlat); in pctl_cfg()
276 DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | in pctl_cfg()
278 &pctl->mcfg); in pctl_cfg()
286 setbits_le32(&pctl->scfg, 1); in pctl_cfg()
292 struct rk3288_ddr_publ *publ = chan->publ; in phy_cfg()
293 struct rk3288_msch *msch = chan->msch; in phy_cfg()
294 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; in phy_cfg()
300 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, in phy_cfg()
301 sizeof(sdram_params->phy_timing)); in phy_cfg()
302 writel(sdram_params->base.noc_timing, &msch->ddrtiming); in phy_cfg()
303 writel(0x3f, &msch->readlatency); in phy_cfg()
304 writel(sdram_params->base.noc_activate, &msch->activate); in phy_cfg()
306 1 << BUSRDTORD_SHIFT, &msch->devtodev); in phy_cfg()
309 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); in phy_cfg()
312 &publ->ptr[1]); in phy_cfg()
315 &publ->ptr[2]); in phy_cfg()
317 switch (sdram_params->base.dramtype) { in phy_cfg()
319 clrsetbits_le32(&publ->pgcr, 0x1F, in phy_cfg()
325 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, in phy_cfg()
327 clrsetbits_le32(&publ->dxccr, in phy_cfg()
331 tmp = readl(&publ->dtpr[1]); in phy_cfg()
332 tmp = ((tmp >> TDQSCKMAX_SHIFT) & TDQSCKMAX_MASK) - in phy_cfg()
334 clrsetbits_le32(&publ->dsgcr, in phy_cfg()
340 clrbits_le32(&publ->pgcr, 0x1f); in phy_cfg()
341 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, in phy_cfg()
345 if (sdram_params->base.odt) { in phy_cfg()
348 setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); in phy_cfg()
352 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); in phy_cfg()
358 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST in phy_init()
361 while ((readl(&publ->pgsr) & in phy_init()
370 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
372 while (readl(&pctl->mcmd) & START_CMD) in send_command()
386 setbits_le32(&publ->pir, in memory_init()
391 while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) in memory_init()
402 state = readl(&pctl->stat) & PCTL_STAT_MSK; in move_to_config_state()
406 writel(WAKEUP_STATE, &pctl->sctl); in move_to_config_state()
407 while ((readl(&pctl->stat) & PCTL_STAT_MSK) in move_to_config_state()
410 /* wait DLL lock */ in move_to_config_state()
411 while ((readl(&publ->pgsr) & PGSR_DLDONE) in move_to_config_state()
416 * and then enter the config in move_to_config_state()
422 writel(CFG_STATE, &pctl->sctl); in move_to_config_state()
423 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) in move_to_config_state()
426 case CONFIG: in move_to_config_state()
437 struct rk3288_ddr_pctl *pctl = chan->pctl; in set_bandwidth_ratio()
438 struct rk3288_ddr_publ *publ = chan->publ; in set_bandwidth_ratio()
439 struct rk3288_msch *msch = chan->msch; in set_bandwidth_ratio()
442 setbits_le32(&pctl->ppcfg, 1); in set_bandwidth_ratio()
443 rk_setreg(&grf->soc_con0, 1 << (8 + channel)); in set_bandwidth_ratio()
444 setbits_le32(&msch->ddrtiming, 1 << 31); in set_bandwidth_ratio()
446 clrbits_le32(&publ->datx8[2].dxgcr, 1); in set_bandwidth_ratio()
447 clrbits_le32(&publ->datx8[3].dxgcr, 1); in set_bandwidth_ratio()
448 /* disable DLL */ in set_bandwidth_ratio()
449 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
450 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
452 clrbits_le32(&pctl->ppcfg, 1); in set_bandwidth_ratio()
453 rk_clrreg(&grf->soc_con0, 1 << (8 + channel)); in set_bandwidth_ratio()
454 clrbits_le32(&msch->ddrtiming, 1 << 31); in set_bandwidth_ratio()
456 setbits_le32(&publ->datx8[2].dxgcr, 1); in set_bandwidth_ratio()
457 setbits_le32(&publ->datx8[3].dxgcr, 1); in set_bandwidth_ratio()
459 /* enable DLL */ in set_bandwidth_ratio()
460 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
461 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); in set_bandwidth_ratio()
462 /* reset DLL */ in set_bandwidth_ratio()
463 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
464 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
466 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
467 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); in set_bandwidth_ratio()
469 setbits_le32(&pctl->dfistcfg0, 1 << 2); in set_bandwidth_ratio()
480 struct rk3288_ddr_publ *publ = chan->publ; in data_training()
481 struct rk3288_ddr_pctl *pctl = chan->pctl; in data_training()
484 writel(0, &pctl->trefi); in data_training()
486 if (sdram_params->base.dramtype != LPDDR3) in data_training()
487 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); in data_training()
488 rank = sdram_params->ch[channel].rank | 1; in data_training()
494 setbits_le32(&publ->pir, PIR_CLRSR); in data_training()
497 setbits_le32(&publ->pir, in data_training()
502 while ((readl(&publ->datx8[0].dxgsr[0]) & rank) in data_training()
505 while ((readl(&publ->datx8[1].dxgsr[0]) & rank) in data_training()
508 if (!(readl(&pctl->ppcfg) & 1)) { in data_training()
509 while ((readl(&publ->datx8[2].dxgsr[0]) in data_training()
512 while ((readl(&publ->datx8[3].dxgsr[0]) in data_training()
516 if (readl(&publ->pgsr) & in data_training()
518 ret = -1; in data_training()
526 if (sdram_params->base.dramtype != LPDDR3) in data_training()
527 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); in data_training()
530 writel(sdram_params->pctl_timing.trefi, &pctl->trefi); in data_training()
537 struct rk3288_ddr_publ *publ = chan->publ; in move_to_access_state()
538 struct rk3288_ddr_pctl *pctl = chan->pctl; in move_to_access_state()
542 state = readl(&pctl->stat) & PCTL_STAT_MSK; in move_to_access_state()
546 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & in move_to_access_state()
550 writel(WAKEUP_STATE, &pctl->sctl); in move_to_access_state()
551 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) in move_to_access_state()
553 /* wait DLL lock */ in move_to_access_state()
554 while ((readl(&publ->pgsr) & PGSR_DLDONE) in move_to_access_state()
559 writel(CFG_STATE, &pctl->sctl); in move_to_access_state()
560 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) in move_to_access_state()
562 case CONFIG: in move_to_access_state()
563 writel(GO_STATE, &pctl->sctl); in move_to_access_state()
564 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) in move_to_access_state()
578 struct rk3288_ddr_publ *publ = chan->publ; in dram_cfg_rbc()
580 if (sdram_params->ch[chnum].bk == 3) in dram_cfg_rbc()
581 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, in dram_cfg_rbc()
584 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); in dram_cfg_rbc()
586 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); in dram_cfg_rbc()
595 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; in dram_all_config()
596 sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; in dram_all_config()
597 for (chan = 0; chan < sdram_params->num_channels; chan++) { in dram_all_config()
599 &sdram_params->ch[chan]; in dram_all_config()
601 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); in dram_all_config()
603 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); in dram_all_config()
604 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); in dram_all_config()
605 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); in dram_all_config()
606 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); in dram_all_config()
607 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); in dram_all_config()
608 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); in dram_all_config()
609 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); in dram_all_config()
611 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
613 writel(sys_reg, &dram->pmu->sys_reg[2]); in dram_all_config()
614 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride); in dram_all_config()
622 const struct chan_info *chan = &dram->chan[channel]; in sdram_rank_bw_detect()
623 struct rk3288_ddr_publ *publ = chan->publ; in sdram_rank_bw_detect()
626 reg = readl(&publ->datx8[0].dxgsr[0]); in sdram_rank_bw_detect()
630 return -EIO; in sdram_rank_bw_detect()
633 sdram_params->num_channels = 1; in sdram_rank_bw_detect()
638 sdram_params->ch[channel].rank = 1; in sdram_rank_bw_detect()
639 clrsetbits_le32(&publ->pgcr, 0xF << 18, in sdram_rank_bw_detect()
640 sdram_params->ch[channel].rank << 18); in sdram_rank_bw_detect()
643 reg = readl(&publ->datx8[2].dxgsr[0]); in sdram_rank_bw_detect()
645 sdram_params->ch[channel].bw = 1; in sdram_rank_bw_detect()
647 sdram_params->ch[channel].bw, in sdram_rank_bw_detect()
648 dram->grf); in sdram_rank_bw_detect()
653 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; in sdram_rank_bw_detect()
657 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
658 ddr_phy_ctl_reset(dram->cru, channel, 1); in sdram_rank_bw_detect()
660 ddr_phy_ctl_reset(dram->cru, channel, 0); in sdram_rank_bw_detect()
664 return -EIO; in sdram_rank_bw_detect()
675 const struct chan_info *chan = &dram->chan[channel]; in sdram_col_row_detect()
676 struct rk3288_ddr_pctl *pctl = chan->pctl; in sdram_col_row_detect()
677 struct rk3288_ddr_publ *publ = chan->publ; in sdram_col_row_detect()
681 for (col = 11; col >= 9; col--) { in sdram_col_row_detect()
684 (1 << (col + sdram_params->ch[channel].bw - 1)); in sdram_col_row_detect()
692 ret = -EINVAL; in sdram_col_row_detect()
695 sdram_params->ch[channel].col = col; in sdram_col_row_detect()
699 writel(4, &chan->msch->ddrconf); in sdram_col_row_detect()
702 for (row = 16; row >= 12; row--) { in sdram_col_row_detect()
704 addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); in sdram_col_row_detect()
712 ret = -EINVAL; in sdram_col_row_detect()
714 sdram_params->ch[channel].cs1_row = row; in sdram_col_row_detect()
715 sdram_params->ch[channel].row_3_4 = 0; in sdram_col_row_detect()
717 sdram_params->ch[channel].cs0_row = row; in sdram_col_row_detect()
728 tmp = sdram_params->ch[0].col - 9; in sdram_get_niu_config()
729 tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; in sdram_get_niu_config()
730 tmp |= ((sdram_params->ch[0].cs0_row - 12) << 4); in sdram_get_niu_config()
736 printf("niu config not found\n"); in sdram_get_niu_config()
737 ret = -EINVAL; in sdram_get_niu_config()
739 sdram_params->base.ddrconfig = i; in sdram_get_niu_config()
747 int stride = -1; in sdram_get_stride()
749 long cap = sdram_params->num_channels * (1u << in sdram_get_stride()
750 (sdram_params->ch[0].cs0_row + in sdram_get_stride()
751 sdram_params->ch[0].col + in sdram_get_stride()
752 (sdram_params->ch[0].rank - 1) + in sdram_get_stride()
753 sdram_params->ch[0].bw + in sdram_get_stride()
754 3 - 20)); in sdram_get_stride()
770 stride = -1; in sdram_get_stride()
772 ret = -EINVAL; in sdram_get_stride()
775 sdram_params->base.stride = stride; in sdram_get_stride()
788 if ((sdram_params->base.dramtype == DDR3 && in sdram_init()
789 sdram_params->base.ddr_freq > 800000000) || in sdram_init()
790 (sdram_params->base.dramtype == LPDDR3 && in sdram_init()
791 sdram_params->base.ddr_freq > 533000000)) { in sdram_init()
793 return -E2BIG; in sdram_init()
797 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); in sdram_init()
805 const struct chan_info *chan = &dram->chan[channel]; in sdram_init()
806 struct rk3288_ddr_pctl *pctl = chan->pctl; in sdram_init()
807 struct rk3288_ddr_publ *publ = chan->publ; in sdram_init()
811 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x17); in sdram_init()
813 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x1a); in sdram_init()
814 phy_pctrl_reset(dram->cru, publ, channel); in sdram_init()
815 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); in sdram_init()
817 dfi_cfg(pctl, sdram_params->base.dramtype); in sdram_init()
819 pctl_cfg(channel, pctl, sdram_params, dram->grf); in sdram_init()
825 writel(POWER_UP_START, &pctl->powctl); in sdram_init()
826 while (!(readl(&pctl->powstat) & POWER_UP_DONE)) in sdram_init()
829 memory_init(publ, sdram_params->base.dramtype); in sdram_init()
832 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
840 sdram_params->phy_timing.mr[1]); in sdram_init()
843 sdram_params->phy_timing.mr[2]); in sdram_init()
846 sdram_params->phy_timing.mr[3]); in sdram_init()
851 sdram_params->ch[channel].bw = 2; in sdram_init()
853 sdram_params->ch[channel].bw, dram->grf); in sdram_init()
860 sdram_params->ch[channel].rank = 2, in sdram_init()
861 clrsetbits_le32(&publ->pgcr, 0xF << 18, in sdram_init()
862 (sdram_params->ch[channel].rank | 1) << 18); in sdram_init()
868 writel(zqcr, &publ->zq1cr[0]); in sdram_init()
869 writel(zqcr, &publ->zq0cr[0]); in sdram_init()
871 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
875 sdram_params->ch[channel].rank | 1, in sdram_init()
877 sdram_params->base.odt ? 3 : 0); in sdram_init()
879 writel(0, &pctl->mrrcfg0); in sdram_init()
882 if ((readl(&pctl->mrrstat0) & 0x3) != 3) { in sdram_init()
884 return -EREMOTEIO; in sdram_init()
889 /* Detect the rank and bit-width with data-training */ in sdram_init()
892 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
894 writel(0, &pctl->mrrcfg0); in sdram_init()
898 writel(15, &chan->msch->ddrconf); in sdram_init()
901 sdram_params->ch[channel].bk = 3; in sdram_init()
945 rk3288_clk_configure_cpu(priv->cru, priv->grf); in veyron_init()
957 if (priv->is_veyron) { in setup_sdram()
975 /* Rk3288 supports dual-channel, set default channel num to 2 */ in rk3288_dmc_ofdata_to_platdata()
976 params->num_channels = 2; in rk3288_dmc_ofdata_to_platdata()
977 ret = dev_read_u32_array(dev, "rockchip,pctl-timing", in rk3288_dmc_ofdata_to_platdata()
978 (u32 *)¶ms->pctl_timing, in rk3288_dmc_ofdata_to_platdata()
979 sizeof(params->pctl_timing) / sizeof(u32)); in rk3288_dmc_ofdata_to_platdata()
981 debug("%s: Cannot read rockchip,pctl-timing\n", __func__); in rk3288_dmc_ofdata_to_platdata()
982 return -EINVAL; in rk3288_dmc_ofdata_to_platdata()
984 ret = dev_read_u32_array(dev, "rockchip,phy-timing", in rk3288_dmc_ofdata_to_platdata()
985 (u32 *)¶ms->phy_timing, in rk3288_dmc_ofdata_to_platdata()
986 sizeof(params->phy_timing) / sizeof(u32)); in rk3288_dmc_ofdata_to_platdata()
988 debug("%s: Cannot read rockchip,phy-timing\n", __func__); in rk3288_dmc_ofdata_to_platdata()
989 return -EINVAL; in rk3288_dmc_ofdata_to_platdata()
991 ret = dev_read_u32_array(dev, "rockchip,sdram-params", in rk3288_dmc_ofdata_to_platdata()
992 (u32 *)¶ms->base, in rk3288_dmc_ofdata_to_platdata()
993 sizeof(params->base) / sizeof(u32)); in rk3288_dmc_ofdata_to_platdata()
995 debug("%s: Cannot read rockchip,sdram-params\n", __func__); in rk3288_dmc_ofdata_to_platdata()
996 return -EINVAL; in rk3288_dmc_ofdata_to_platdata()
1001 priv->is_veyron = !fdt_node_check_compatible(blob, 0, "google,veyron"); in rk3288_dmc_ofdata_to_platdata()
1003 ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map); in rk3288_dmc_ofdata_to_platdata()
1016 struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat; in conv_of_platdata()
1019 memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, in conv_of_platdata()
1020 sizeof(plat->pctl_timing)); in conv_of_platdata()
1021 memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, in conv_of_platdata()
1022 sizeof(plat->phy_timing)); in conv_of_platdata()
1023 memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); in conv_of_platdata()
1024 /* Rk3288 supports dual-channel, set default channel num to 2 */ in conv_of_platdata()
1025 plat->num_channels = 2; in conv_of_platdata()
1026 ret = regmap_init_mem_platdata(dev, of_plat->reg, in conv_of_platdata()
1027 ARRAY_SIZE(of_plat->reg) / 2, in conv_of_platdata()
1028 &plat->map); in conv_of_platdata()
1046 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); in rk3288_dmc_probe()
1056 priv->chan[0].msch = regmap_get_range(map, 0); in rk3288_dmc_probe()
1057 priv->chan[1].msch = (struct rk3288_msch *) in rk3288_dmc_probe()
1060 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); in rk3288_dmc_probe()
1061 priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); in rk3288_dmc_probe()
1063 priv->chan[0].pctl = regmap_get_range(plat->map, 0); in rk3288_dmc_probe()
1064 priv->chan[0].publ = regmap_get_range(plat->map, 1); in rk3288_dmc_probe()
1065 priv->chan[1].pctl = regmap_get_range(plat->map, 2); in rk3288_dmc_probe()
1066 priv->chan[1].publ = regmap_get_range(plat->map, 3); in rk3288_dmc_probe()
1071 priv->ddr_clk.id = CLK_DDR; in rk3288_dmc_probe()
1072 ret = clk_request(dev_clk, &priv->ddr_clk); in rk3288_dmc_probe()
1076 priv->cru = rockchip_get_cru(); in rk3288_dmc_probe()
1077 if (IS_ERR(priv->cru)) in rk3288_dmc_probe()
1078 return PTR_ERR(priv->cru); in rk3288_dmc_probe()
1083 priv->info.base = CONFIG_SYS_SDRAM_BASE; in rk3288_dmc_probe()
1084 priv->info.size = rockchip_sdram_size( in rk3288_dmc_probe()
1085 (phys_addr_t)&priv->pmu->sys_reg[2]); in rk3288_dmc_probe()
1095 *info = priv->info; in rk3288_dmc_get_info()
1105 { .compatible = "rockchip,rk3288-dmc" },