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/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dsdrc.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2004-2010
10 * Texas Instruments Incorporated - http://www.ti.com/
13 * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
35 * is_mem_sdr -
36 * - Return 1 if mem type in use is SDR
40 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) in is_mem_sdr()
46 * make_cs1_contiguous -
47 * - When we have CS1 populated we want to have it mapped after cs0 to allow
59 writel((a_add_high | a_add_low), &sdrc_base->cs_cfg); in make_cs1_contiguous()
[all …]
H A Dspl_id_nand.c1 // SPDX-License-Identifier: GPL-2.0+
10 * Richard Woodruff <r-woodruff2@ti.com>
32 /* Make sure that we have setup GPMC for NAND correctly. */ in identify_nand_chip()
38 writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); in identify_nand_chip()
39 writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); in identify_nand_chip()
40 while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) in identify_nand_chip()
43 if (--loops == 0) in identify_nand_chip()
46 writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd); in identify_nand_chip()
49 writeb(0x0, &gpmc_cfg->cs[0].nand_adr); in identify_nand_chip()
52 *mfr = readb(&gpmc_cfg->cs[0].nand_dat); in identify_nand_chip()
[all …]
/openbmc/u-boot/cmd/
H A Dmmc_spi.c2 * Command for mmc_spi setup.
5 * Licensed under the GPL-2 or later.
35 uint cs = CONFIG_MMC_SPI_CS; in do_mmc_spi() local
44 cs = simple_strtoul(argv[1], &endp, 0); in do_mmc_spi()
50 bus = cs; in do_mmc_spi()
51 cs = simple_strtoul(endp + 1, &endp, 0); in do_mmc_spi()
65 if (!spi_cs_is_valid(bus, cs)) { in do_mmc_spi()
66 printf("Invalid SPI bus %u cs %u\n", bus, cs); in do_mmc_spi()
70 mmc = mmc_spi_init(bus, cs, speed, mode); in do_mmc_spi()
75 printf("%s: %d at %u:%u hz %u mode %u\n", mmc->cfg->name, in do_mmc_spi()
[all …]
/openbmc/u-boot/arch/sandbox/include/asm/
H A Dspi.h4 * Copyright (c) 2011-2013 The Chromium OS Authors.
8 * Licensed under the GPL-2 or later.
23 /* The bus wants to instantiate a new client, so setup everything */
24 int (*setup)(void **priv, const char *spec); member
27 /* The CS has been "activated" -- we won't worry about low/high */
29 /* The CS has been "deactivated" -- we won't worry about low/high */
31 /* The client is rx-ing bytes from the bus, so it should tx some */
36 * Extract the bus/cs from the spi spec and return the start of the spi
37 * client spec. If the bus/cs are invalid for the current config, then
40 * Example: arg="0:1:foo" will set bus to 0, cs to 1, and return "foo"
[all …]
/openbmc/u-boot/board/atmel/at91sam9261ek/
H A Dat91sam9261ek.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
24 #include <asm/mach-types.h>
28 /* ------------------------------------------------------------------------- */
41 csa = readl(&matrix->ebicsa); in at91sam9261ek_nand_hw_init()
44 writel(csa, &matrix->ebicsa); in at91sam9261ek_nand_hw_init()
50 &smc->cs[3].setup); in at91sam9261ek_nand_hw_init()
53 &smc->cs[3].pulse); in at91sam9261ek_nand_hw_init()
55 &smc->cs[3].cycle); in at91sam9261ek_nand_hw_init()
59 &smc->cs[3].setup); in at91sam9261ek_nand_hw_init()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dkeystone-k2l-evm.dts10 /dts-v1/;
13 #include "keystone-k2l.dtsi"
16 compatible = "ti,k2l-evm","ti,keystone";
22 #clock-cells = <0>;
23 compatible = "fixed-clock";
24 clock-frequency = <122880000>;
25 clock-output-names = "refclk-sys";
48 #address-cells = <2>;
49 #size-cells = <1>;
50 clock-ranges;
[all …]
H A Dkeystone-k2e-evm.dts2 * Copyright 2013-2014 Texas Instruments, Inc.
10 /dts-v1/;
13 #include "keystone-k2e.dtsi"
16 compatible = "ti,k2e-evm","ti,keystone";
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <100000000>;
26 clock-output-names = "refclk-sys";
30 #clock-cells = <0>;
31 compatible = "fixed-clock";
[all …]
H A Dkeystone-k2hk-evm.dts2 * Copyright 2013-2014 Texas Instruments, Inc.
10 /dts-v1/;
13 #include "keystone-k2hk.dtsi"
16 compatible = "ti,k2hk-evm","ti,keystone";
22 #clock-cells = <0>;
23 compatible = "fixed-clock";
24 clock-frequency = <122880000>;
25 clock-output-names = "refclk-sys";
29 #clock-cells = <0>;
30 compatible = "fixed-clock";
[all …]
/openbmc/qemu/bsd-user/x86_64/
H A Dtarget_arch_cpu.h23 #include "signal-common.h"
32 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; in target_cpu_init()
33 env->hflags |= HF_PE_MASK | HF_CPL_MASK; in target_cpu_init()
34 if (env->features[FEAT_1_EDX] & CPUID_SSE) { in target_cpu_init()
35 env->cr[4] |= CR4_OSFXSR_MASK; in target_cpu_init()
36 env->hflags |= HF_OSFXSR_MASK; in target_cpu_init()
40 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { in target_cpu_init()
44 env->cr[4] |= CR4_PAE_MASK; in target_cpu_init()
45 env->efer |= MSR_EFER_LMA | MSR_EFER_LME; in target_cpu_init()
46 env->hflags |= HF_LMA_MASK; in target_cpu_init()
[all …]
/openbmc/qemu/bsd-user/i386/
H A Dtarget_arch_cpu.h23 #include "signal-common.h"
32 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; in target_cpu_init()
33 env->hflags |= HF_PE_MASK | HF_CPL_MASK; in target_cpu_init()
34 if (env->features[FEAT_1_EDX] & CPUID_SSE) { in target_cpu_init()
35 env->cr[4] |= CR4_OSFXSR_MASK; in target_cpu_init()
36 env->hflags |= HF_OSFXSR_MASK; in target_cpu_init()
39 /* flags setup : we activate the IRQs by default as in user mode */ in target_cpu_init()
40 env->eflags |= IF_MASK; in target_cpu_init()
42 /* register setup */ in target_cpu_init()
43 env->regs[R_EAX] = regs->eax; in target_cpu_init()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_init.c1 // SPDX-License-Identifier: GPL-2.0
76 puts("\n########### LOG LEVEL 1 (D-UNIT SETUP)###########\n"); in print_dunit_setup()
79 puts("\nStatic D-UNIT Setup:\n"); in print_dunit_setup()
82 puts("\nDynamic(using SPD) D-UNIT Setup:\n"); in print_dunit_setup()
140 u32 ui, reg, cs; in ddr3_restore_and_set_final_windows() local
157 /* Return XBAR windows 4-7 or 16-19 init configuration */ in ddr3_restore_and_set_final_windows()
161 DEBUG_INIT_FULL_S("DDR3 Training Sequence - Switching XBAR Window to FastPath Window\n"); in ddr3_restore_and_set_final_windows()
168 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_restore_and_set_final_windows()
169 if (cs_ena & (1 << cs)) { in ddr3_restore_and_set_final_windows()
170 /* set fast path window control for the cs */ in ddr3_restore_and_set_final_windows()
[all …]
/openbmc/u-boot/drivers/spi/
H A Dmscc_bb_spi.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
21 bool cs_active; /* State flag as to whether CS is asserted */
31 static int mscc_bb_spi_cs_activate(struct mscc_bb_priv *priv, int mode, int cs) in mscc_bb_spi_cs_activate() argument
33 if (!priv->cs_active) { in mscc_bb_spi_cs_activate()
37 priv->cs_num = cs; in mscc_bb_spi_cs_activate()
41 priv->clk1 = ICPU_SW_MODE_SW_SPI_SCK; in mscc_bb_spi_cs_activate()
42 priv->clk2 = 0; in mscc_bb_spi_cs_activate()
45 priv->clk1 = 0; in mscc_bb_spi_cs_activate()
46 priv->clk2 = ICPU_SW_MODE_SW_SPI_SCK; in mscc_bb_spi_cs_activate()
50 priv->svalue = (ICPU_SW_MODE_SW_PIN_CTRL_MODE | /* Bitbang */ in mscc_bb_spi_cs_activate()
[all …]
H A Dmxc_spi.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
15 #include <asm/mach-imx/spi.h>
27 __weak int board_spi_cs_gpio(unsigned bus, unsigned cs) in board_spi_cs_gpio() argument
29 return -1; in board_spi_cs_gpio()
63 dm_gpio_set_value(&mxcs->ss, 1); in mxc_spi_cs_activate()
65 if (mxcs->gpio > 0) in mxc_spi_cs_activate()
66 gpio_set_value(mxcs->gpio, mxcs->ss_pol); in mxc_spi_cs_activate()
73 dm_gpio_set_value(&mxcs->ss, 0); in mxc_spi_cs_deactivate()
75 if (mxcs->gpio > 0) in mxc_spi_cs_deactivate()
[all …]
/openbmc/u-boot/board/gumstix/duovero/
H A Dduovero.c1 // SPDX-License-Identifier: GPL-2.0+
16 #include <asm/mach-types.h>
30 #include <asm/ehci-omap.h>
50 gd->bd->bi_arch_number = MACH_TYPE_DUOVERO; in board_init()
51 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
57 * @brief misc_init_r - Configure board specific configurations
68 /* wifi setup: first enable 32Khz clock from 6030 pmic */ in misc_init_r()
74 /* then setup WIFI_EN as an output pin and send reset pulse */ in misc_init_r()
92 do_set_mux((*ctrl)->control_padconf_core_base, in set_muxconf_regs()
97 do_set_mux((*ctrl)->control_padconf_wkup_base, in set_muxconf_regs()
[all …]
/openbmc/u-boot/board/esd/meesc/
H A Dmeesc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
7 * (C) Copyright 2009-2015
15 #include <asm/mach-types.h>
16 #include <asm/setup.h>
33 static int hw_rev = -1; /* hardware revision */
60 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; in meesc_nand_hw_init()
61 writel(csa, &matrix->csa[0]); in meesc_nand_hw_init()
66 &smc->cs[3].setup); in meesc_nand_hw_init()
70 &smc->cs[3].pulse); in meesc_nand_hw_init()
[all …]
/openbmc/openbmc/meta-openembedded/meta-initramfs/recipes-kernel/kexec/kexec-tools-klibc/
H A DFix-building-on-x86_64-with-binutils-2.41.patch3 Date: Tue, 30 Jan 2024 04:14:31 -0600
7 complain about the ".arch i386" in files assembled with "as --64",
11 that the assembler is no longer expecting 64-bit instructions to be used
17 Signed-off-by: Michel Lind <michel@michel-slm.name>
18 Signed-off-by: Simon Horman <horms@kernel.org>
20 Upstream-Status: Backport [https://git.kernel.org/pub/scm/utils/kernel/kexec/kexec-tools.git/commit…
21 Signed-off-by: Yoann Congal <yoann.congal@smile.fr>
22 ---
23 purgatory/arch/i386/entry32-16-debug.S | 2 +-
24 purgatory/arch/i386/entry32-16.S | 2 +-
[all …]
/openbmc/u-boot/board/laird/wb45n/
H A Dwb45n.c1 // SPDX-License-Identifier: GPL-2.0+
18 /* ------------------------------------------------------------------------- */
28 csa = readl(&matrix->ebicsa); in wb45n_nand_hw_init()
33 writel(csa, &matrix->ebicsa); in wb45n_nand_hw_init()
38 &smc->cs[3].setup); in wb45n_nand_hw_init()
41 &smc->cs[3].pulse); in wb45n_nand_hw_init()
43 &smc->cs[3].cycle); in wb45n_nand_hw_init()
47 AT91_SMC_MODE_TDF_CYCLE(1), &smc->cs[3].mode); in wb45n_nand_hw_init()
70 /* Setup USB pins */ in wb45n_gpio_hw_init()
98 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
[all …]
/openbmc/u-boot/board/cobra5272/bdm/
H A Dcobra5272_uboot.gdb13 set $scr = $mbar - 1 + 0x004
14 set $spr = $mbar - 1 + 0x006
15 set $pmr = $mbar - 1 + 0x008
16 set $apmr = $mbar - 1 + 0x00e
17 set $dir = $mbar - 1 + 0x010
18 set $icr1 = $mbar - 1 + 0x020
19 set $icr2 = $mbar - 1 + 0x024
20 set $icr3 = $mbar - 1 + 0x028
21 set $icr4 = $mbar - 1 + 0x02c
22 set $isr = $mbar - 1 + 0x030
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Dehci-marvell.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
39 * USB 2.0 Bridge Address Decoding registers setup
50 * to the common mvebu archticture including the mbus setup, this
65 for (i = 0; i < dram->num_cs; i++) { in usb_brg_adrdec_setup()
66 const struct mbus_dram_window *cs = dram->cs + i; in usb_brg_adrdec_setup() local
69 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | in usb_brg_adrdec_setup()
70 (dram->mbus_dram_target_id << 4) | 1, in usb_brg_adrdec_setup()
74 writel(cs->base, base + USB_WINDOW_BASE(i)); in usb_brg_adrdec_setup()
81 struct ehci_mvebu_priv *priv = ctrl->priv; in marvell_ehci_powerup_fixup()
[all …]
/openbmc/u-boot/drivers/ddr/fsl/
H A Dmpc86xx_ddr.c1 // SPDX-License-Identifier: GPL-2.0
34 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
35 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
38 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
39 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
42 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
43 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
46 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
47 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
51 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); in fsl_ddr_set_memctl_regs()
[all …]
H A Dmpc85xx_ddr_gen1.c1 // SPDX-License-Identifier: GPL-2.0
28 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
29 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
32 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
33 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
36 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
37 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
40 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
41 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
45 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
[all …]
H A Dmpc85xx_ddr_gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008-2011 Freescale Semiconductor, Inc.
39 if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) == in fsl_ddr_set_memctl_regs()
41 out_be32(&gur->ddrioovcr, 0x90000000); in fsl_ddr_set_memctl_regs()
43 out_be32(&gur->ddrioovcr, 0xA8000000); in fsl_ddr_set_memctl_regs()
49 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
50 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
53 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
54 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
57 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
[all …]
H A Darm_ddr_gen3.c1 // SPDX-License-Identifier: GPL-2.0+
22 * regs has the to-be-set values for DDR controller registers
66 if (regs->ddr_eor) in fsl_ddr_set_memctl_regs()
67 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
70 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
71 ddr_out32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
72 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
75 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
76 ddr_out32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
77 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
[all …]
/openbmc/u-boot/board/atmel/sama5d3xek/
H A Dsama5d3xek.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 - 2013 Atmel Corporation
24 /* ------------------------------------------------------------------------- */
39 &smc->cs[3].setup); in sama5d3xek_nand_hw_init()
42 &smc->cs[3].pulse); in sama5d3xek_nand_hw_init()
44 &smc->cs[3].cycle); in sama5d3xek_nand_hw_init()
48 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); in sama5d3xek_nand_hw_init()
57 &smc->cs[3].mode); in sama5d3xek_nand_hw_init()
71 &smc->cs[0].setup); in sama5d3xek_nor_hw_init()
74 &smc->cs[0].pulse); in sama5d3xek_nor_hw_init()
[all …]
/openbmc/u-boot/board/atmel/at91sam9n12ek/
H A Dat91sam9n12ek.c1 // SPDX-License-Identifier: GPL-2.0+
27 /* ------------------------------------------------------------------------- */
39 csa = readl(&matrix->ebicsa); in at91sam9n12ek_nand_hw_init()
46 writel(csa, &matrix->ebicsa); in at91sam9n12ek_nand_hw_init()
51 &smc->cs[3].setup); in at91sam9n12ek_nand_hw_init()
54 &smc->cs[3].pulse); in at91sam9n12ek_nand_hw_init()
56 &smc->cs[3].cycle); in at91sam9n12ek_nand_hw_init()
65 &smc->cs[3].mode); in at91sam9n12ek_nand_hw_init()
123 dram_size += gd->bd->bi_dram[i].size; in lcd_show_board_info()
126 nand_size += get_nand_dev_by_index(i)->size; in lcd_show_board_info()
[all …]

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