Lines Matching +full:cs +full:- +full:setup
1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2004-2010
10 * Texas Instruments Incorporated - http://www.ti.com/
13 * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
35 * is_mem_sdr -
36 * - Return 1 if mem type in use is SDR
40 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) in is_mem_sdr()
46 * make_cs1_contiguous -
47 * - When we have CS1 populated we want to have it mapped after cs0 to allow
59 writel((a_add_high | a_add_low), &sdrc_base->cs_cfg); in make_cs1_contiguous()
65 * get_sdr_cs_size -
66 * - Get size of chip select 0/1
68 u32 get_sdr_cs_size(u32 cs) in get_sdr_cs_size() argument
73 size = readl(&sdrc_base->cs[cs].mcfg) >> 8; in get_sdr_cs_size()
80 * get_sdr_cs_offset -
81 * - Get offset of cs from cs0 start
83 u32 get_sdr_cs_offset(u32 cs) in get_sdr_cs_offset() argument
87 if (!cs) in get_sdr_cs_offset()
90 offset = readl(&sdrc_base->cs_cfg); in get_sdr_cs_offset()
97 * write_sdrc_timings -
98 * - Takes CS and associated timings and initalize SDRAM
99 * - Test CS to make sure it's OK for use
101 static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, in write_sdrc_timings() argument
104 /* Setup timings we got from the board. */ in write_sdrc_timings()
105 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); in write_sdrc_timings()
106 writel(timings->ctrla, &sdrc_actim_base->ctrla); in write_sdrc_timings()
107 writel(timings->ctrlb, &sdrc_actim_base->ctrlb); in write_sdrc_timings()
108 writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); in write_sdrc_timings()
109 writel(CMD_NOP, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
110 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
111 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
112 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); in write_sdrc_timings()
113 writel(timings->mr, &sdrc_base->cs[cs].mr); in write_sdrc_timings()
119 if (!mem_ok(cs)) in write_sdrc_timings()
120 writel(0, &sdrc_base->cs[cs].mcfg); in write_sdrc_timings()
124 * do_sdrc_init -
125 * - Code called once in C-Stack only context for CS0 and with early being
129 void do_sdrc_init(u32 cs, u32 early) in do_sdrc_init() argument
145 * from the first bank to the second. We will setup CS0, in do_sdrc_init()
147 * setup CS1. in do_sdrc_init()
150 /* set/modify board-specific timings */ in do_sdrc_init()
155 writel(SOFTRESET, &sdrc_base->sysconfig); in do_sdrc_init()
156 wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status, in do_sdrc_init()
158 writel(0, &sdrc_base->sysconfig); in do_sdrc_init()
160 /* setup sdrc to ball mux */ in do_sdrc_init()
161 writel(timings.sharing, &sdrc_base->sharing); in do_sdrc_init()
165 &sdrc_base->power); in do_sdrc_init()
167 writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); in do_sdrc_init()
180 * both CS0 and CS1 (such as some older versions of x-loader) in do_sdrc_init()
181 * so we may be asked now to setup CS1. in do_sdrc_init()
183 if (cs == CS1) { in do_sdrc_init()
184 timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg), in do_sdrc_init()
185 timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); in do_sdrc_init()
186 timings.ctrla = readl(&sdrc_actim_base0->ctrla); in do_sdrc_init()
187 timings.ctrlb = readl(&sdrc_actim_base0->ctrlb); in do_sdrc_init()
188 timings.mr = readl(&sdrc_base->cs[CS0].mr); in do_sdrc_init()
189 write_sdrc_timings(cs, sdrc_actim_base1, &timings); in do_sdrc_init()
194 * dram_init -
195 * - Sets uboots idea of sdram size
206 * configured correctly. CS0 will already have been setup in dram_init()
213 gd->ram_size = size0 + size1; in dram_init()
225 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; in dram_init_banksize()
226 gd->bd->bi_dram[0].size = size0; in dram_init_banksize()
227 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); in dram_init_banksize()
228 gd->bd->bi_dram[1].size = size1; in dram_init_banksize()
234 * mem_init -
235 * - Init the sdrc chip,
236 * - Selects CS0 and CS1,