1 // SPDX-License-Identifier: GPL-2.0+
27 /* ------------------------------------------------------------------------- */
39 	csa = readl(&matrix->ebicsa);  in at91sam9n12ek_nand_hw_init()
46 	writel(csa, &matrix->ebicsa);  in at91sam9n12ek_nand_hw_init()
51 		&smc->cs[3].setup);  in at91sam9n12ek_nand_hw_init()
54 		&smc->cs[3].pulse);  in at91sam9n12ek_nand_hw_init()
56 		&smc->cs[3].cycle);  in at91sam9n12ek_nand_hw_init()
65 		&smc->cs[3].mode);  in at91sam9n12ek_nand_hw_init()
123 		dram_size += gd->bd->bi_dram[i].size;  in lcd_show_board_info()
126 		nand_size += get_nand_dev_by_index(i)->size;  in lcd_show_board_info()
141 	       &smc->cs[2].setup);  in at91sam9n12ek_ks8851_hw_init()
144 	       &smc->cs[2].pulse);  in at91sam9n12ek_ks8851_hw_init()
146 	       &smc->cs[2].cycle);  in at91sam9n12ek_ks8851_hw_init()
151 	       &smc->cs[2].mode);  in at91sam9n12ek_ks8851_hw_init()
185 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;  in board_init()
215 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,  in dram_init()
238 	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);  in ddr2_conf()
240 	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |  in ddr2_conf()
246 	ddr2->rtr = 0x411;  in ddr2_conf()
248 	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |  in ddr2_conf()
257 	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |  in ddr2_conf()
262 	ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |  in ddr2_conf()
278 	writel(AT91_PMC_DDR, &pmc->scer);  in mem_init()
281 	csa = readl(&matrix->ebicsa);  in mem_init()
286 	writel(csa, &matrix->ebicsa);  in mem_init()