1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
21 	bool cs_active;   /* State flag as to whether CS is asserted */
31 static int mscc_bb_spi_cs_activate(struct mscc_bb_priv *priv, int mode, int cs)  in mscc_bb_spi_cs_activate()  argument
33 	if (!priv->cs_active) {  in mscc_bb_spi_cs_activate()
37 		priv->cs_num = cs;  in mscc_bb_spi_cs_activate()
41 			priv->clk1 = ICPU_SW_MODE_SW_SPI_SCK;  in mscc_bb_spi_cs_activate()
42 			priv->clk2 = 0;  in mscc_bb_spi_cs_activate()
45 			priv->clk1 = 0;  in mscc_bb_spi_cs_activate()
46 			priv->clk2 = ICPU_SW_MODE_SW_SPI_SCK;  in mscc_bb_spi_cs_activate()
50 		priv->svalue = (ICPU_SW_MODE_SW_PIN_CTRL_MODE | /* Bitbang */  in mscc_bb_spi_cs_activate()
54 		/* Add CS */  in mscc_bb_spi_cs_activate()
55 		if (cs >= 0) {  in mscc_bb_spi_cs_activate()
57 				ICPU_SW_MODE_SW_SPI_CS_OE(BIT(cs)) |  in mscc_bb_spi_cs_activate()
58 				ICPU_SW_MODE_SW_SPI_CS(BIT(cs));  in mscc_bb_spi_cs_activate()
63 		priv->svalue |= cs_value;  in mscc_bb_spi_cs_activate()
65 		/* Enable the CS in HW, Initial clock value */  in mscc_bb_spi_cs_activate()
66 		writel(priv->svalue | priv->clk2, priv->regs);  in mscc_bb_spi_cs_activate()
68 		priv->cs_active = true;  in mscc_bb_spi_cs_activate()
69 		debug("Activated CS%d\n", priv->cs_num);  in mscc_bb_spi_cs_activate()
77 	if (priv->cs_active) {  in mscc_bb_spi_cs_deactivate()
79 		 * actively deselecting CS.  in mscc_bb_spi_cs_deactivate()
81 		u32 value = readl(priv->regs);  in mscc_bb_spi_cs_deactivate()
84 		writel(value, priv->regs);  in mscc_bb_spi_cs_deactivate()
87 		/* Stop driving the clock, but keep CS with nCS == 1 */  in mscc_bb_spi_cs_deactivate()
89 		writel(value, priv->regs);  in mscc_bb_spi_cs_deactivate()
96 		writel(0, priv->regs);  in mscc_bb_spi_cs_deactivate()
98 		priv->cs_active = false;  in mscc_bb_spi_cs_deactivate()
99 		debug("Deactivated CS%d\n", priv->cs_num);  in mscc_bb_spi_cs_deactivate()
125 	debug("spi_xfer: slave %s:%s cs%d mode %d, dout %p din %p bitlen %u\n",  in mscc_bb_spi_xfer()
126 	      dev->parent->name, dev->name, plat->cs,  plat->mode, dout,  in mscc_bb_spi_xfer()
130 		mscc_bb_spi_cs_activate(priv, plat->mode, plat->cs);  in mscc_bb_spi_xfer()
138 			value = priv->svalue;  in mscc_bb_spi_xfer()
148 			writel(value | priv->clk1, priv->regs);  in mscc_bb_spi_xfer()
151 			 * setup-time, so we always insert some delay  in mscc_bb_spi_xfer()
153 			 * setup-time, which can be adjusted by the  in mscc_bb_spi_xfer()
154 			 * user through vcoreiii_device->delay.  in mscc_bb_spi_xfer()
159 			writel(value | priv->clk2, priv->regs);  in mscc_bb_spi_xfer()
169 			value = readl(priv->regs);  in mscc_bb_spi_xfer()
184 		mscc_bb_spi_cs_deactivate(priv, priv->deactivate_delay_us);  in mscc_bb_spi_xfer()
209 	{ .compatible = "mscc,luton-bb-spi" },
219 	priv->regs = (void __iomem *)dev_read_addr(bus);  in mscc_bb_spi_probe()
221 	priv->deactivate_delay_us =  in mscc_bb_spi_probe()
222 		dev_read_u32_default(bus, "spi-deactivate-delay", 0);  in mscc_bb_spi_probe()
224 	priv->cs_active = false;  in mscc_bb_spi_probe()