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/openbmc/linux/drivers/clk/renesas/
H A DMakefile5 obj-$(CONFIG_CLK_R7S9210) += r7s9210-cpg-mssr.o
8 obj-$(CONFIG_CLK_R8A7742) += r8a7742-cpg-mssr.o
9 obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
10 obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
11 obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
12 obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
13 obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
14 obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
15 obj-$(CONFIG_CLK_R8A774E1) += r8a774e1-cpg-mssr.o
18 obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g054.dtsi9 #include <dt-bindings/clock/r9a07g054-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
255 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
256 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
259 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
262 power-domains = <&cpg>;
[all …]
H A Dr9a07g044.dtsi9 #include <dt-bindings/clock/r9a07g044-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
255 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
256 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
259 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
262 power-domains = <&cpg>;
[all …]
H A Dr9a07g043.dtsi8 #include <dt-bindings/clock/r9a07g043-cpg.h>
140 clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>;
141 power-domains = <&cpg>;
142 resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>;
155 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
156 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
159 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
162 power-domains = <&cpg>;
175 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
176 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
[all …]
H A Dr9a09g011.dtsi9 #include <dt-bindings/clock/r9a09g011-cpg.h>
41 clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
68 clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
78 clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
79 <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
80 <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
81 <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
83 resets = <&cpg R9A09G011_SDI0_IXRST>;
84 power-domains = <&cpg>;
94 clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
[all …]
H A Dhihope-rev4.dtsi96 clocks = <&cpg CPG_MOD 1005>,
97 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
98 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
99 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
100 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
101 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
102 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
103 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
104 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
105 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
[all …]
H A Dr8a77990.dtsi8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
79 clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
91 clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>;
161 clocks = <&cpg CPG_MOD 402>;
163 resets = <&cpg 402>;
177 clocks = <&cpg CPG_MOD 912>;
179 resets = <&cpg 912>;
192 clocks = <&cpg CPG_MOD 911>;
194 resets = <&cpg 911>;
207 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77995.dtsi9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
98 clocks = <&cpg CPG_MOD 402>;
100 resets = <&cpg 402>;
114 clocks = <&cpg CPG_MOD 912>;
116 resets = <&cpg 912>;
129 clocks = <&cpg CPG_MOD 911>;
131 resets = <&cpg 911>;
144 clocks = <&cpg CPG_MOD 910>;
146 resets = <&cpg 910>;
159 clocks = <&cpg CPG_MOD 909>;
[all …]
H A Dr8a774c0.dtsi8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
89 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>;
146 clocks = <&cpg CPG_MOD 402>;
148 resets = <&cpg 402>;
162 clocks = <&cpg CPG_MOD 912>;
164 resets = <&cpg 912>;
177 clocks = <&cpg CPG_MOD 911>;
179 resets = <&cpg 911>;
192 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a77951.dtsi8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
153 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
167 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
181 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
195 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
211 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
224 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
237 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
250 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
361 clocks = <&cpg CPG_MOD 402>;
[all …]
H A Dr8a77965.dtsi11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
106 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
118 clocks = <&cpg CPG_CORE R8A77965_CLK_Z>;
196 clocks = <&cpg CPG_MOD 402>;
198 resets = <&cpg 402>;
212 clocks = <&cpg CPG_MOD 912>;
214 resets = <&cpg 912>;
227 clocks = <&cpg CPG_MOD 911>;
229 resets = <&cpg 911>;
242 clocks = <&cpg CPG_MOD 910>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-mssr.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
18 - The CPG block generates various core clocks,
27 - renesas,r7s9210-cpg-mssr # RZ/A2
28 - renesas,r8a7742-cpg-mssr # RZ/G1H
29 - renesas,r8a7743-cpg-mssr # RZ/G1M
30 - renesas,r8a7744-cpg-mssr # RZ/G1N
31 - renesas,r8a7745-cpg-mssr # RZ/G1E
32 - renesas,r8a77470-cpg-mssr # RZ/G1C
33 - renesas,r8a774a1-cpg-mssr # RZ/G2M
[all …]
/openbmc/u-boot/board/kmc/kzm9g/
H A Dkzm9g.c135 struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; in s_init() local
151 clrbits_le32(&cpg->smstpcr3, (1 << 15)); in s_init()
153 clrbits_le32(&cpg->smstpcr2, (1 << 18)); in s_init()
155 writel(0x0, &cpg->pllecr); in s_init()
157 cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); in s_init()
158 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); in s_init()
160 writel(0x2D000000, &cpg->pll0cr); in s_init()
161 writel(0x17100000, &cpg->pll1cr); in s_init()
162 writel(0x96235880, &cpg->frqcrb); in s_init()
163 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); in s_init()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dr8a7795.dtsi8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
126 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
138 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
150 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
162 clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
174 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
185 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
196 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
207 clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
294 clocks = <&cpg CPG_MOD 402>;
[all …]
H A Dr8a7792.dtsi8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
64 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
112 clocks = <&cpg CPG_MOD 402>;
114 resets = <&cpg 402>;
128 clocks = <&cpg CPG_MOD 912>;
130 resets = <&cpg 912>;
143 clocks = <&cpg CPG_MOD 911>;
145 resets = <&cpg 911>;
158 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7791.dtsi10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
78 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
98 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
163 clocks = <&cpg CPG_MOD 402>;
165 resets = <&cpg 402>;
179 clocks = <&cpg CPG_MOD 912>;
181 resets = <&cpg 912>;
194 clocks = <&cpg CPG_MOD 911>;
196 resets = <&cpg 911>;
209 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7796.dtsi8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
137 clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
149 clocks =<&cpg CPG_CORE R8A7796_CLK_Z>;
161 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
172 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
183 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
194 clocks =<&cpg CPG_CORE R8A7796_CLK_Z2>;
273 clocks = <&cpg CPG_MOD 402>;
275 resets = <&cpg 402>;
289 clocks = <&cpg CPG_MOD 912>;
[all …]
H A Dr8a77995.dtsi9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
80 clocks = <&cpg CPG_MOD 402>;
82 resets = <&cpg 402>;
96 clocks = <&cpg CPG_MOD 912>;
98 resets = <&cpg 912>;
111 clocks = <&cpg CPG_MOD 911>;
113 resets = <&cpg 911>;
126 clocks = <&cpg CPG_MOD 910>;
128 resets = <&cpg 910>;
141 clocks = <&cpg CPG_MOD 909>;
[all …]
H A Dr8a7793.dtsi8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
70 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
148 clocks = <&cpg CPG_MOD 402>;
150 resets = <&cpg 402>;
164 clocks = <&cpg CPG_MOD 912>;
166 resets = <&cpg 912>;
179 clocks = <&cpg CPG_MOD 911>;
181 resets = <&cpg 911>;
194 clocks = <&cpg CPG_MOD 910>;
[all …]
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7792.dtsi8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
54 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
65 clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
115 clocks = <&cpg CPG_MOD 402>;
117 resets = <&cpg 402>;
131 clocks = <&cpg CPG_MOD 912>;
133 resets = <&cpg 912>;
146 clocks = <&cpg CPG_MOD 911>;
148 resets = <&cpg 911>;
161 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7791.dtsi10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
77 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
98 clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
165 clocks = <&cpg CPG_MOD 402>;
167 resets = <&cpg 402>;
181 clocks = <&cpg CPG_MOD 912>;
183 resets = <&cpg 912>;
196 clocks = <&cpg CPG_MOD 911>;
198 resets = <&cpg 911>;
211 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7745.dtsi10 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
73 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
84 clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
139 clocks = <&cpg CPG_MOD 912>;
141 resets = <&cpg 912>;
154 clocks = <&cpg CPG_MOD 911>;
156 resets = <&cpg 911>;
169 clocks = <&cpg CPG_MOD 910>;
171 resets = <&cpg 910>;
184 clocks = <&cpg CPG_MOD 909>;
[all …]
H A Dr8a77470.dtsi10 #include <dt-bindings/clock/r8a77470-cpg-mssr.h>
34 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
45 clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
95 clocks = <&cpg CPG_MOD 402>;
97 resets = <&cpg 402>;
111 clocks = <&cpg CPG_MOD 912>;
113 resets = <&cpg 912>;
126 clocks = <&cpg CPG_MOD 911>;
128 resets = <&cpg 911>;
141 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7793.dtsi8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
69 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
150 clocks = <&cpg CPG_MOD 402>;
152 resets = <&cpg 402>;
166 clocks = <&cpg CPG_MOD 912>;
168 resets = <&cpg 912>;
181 clocks = <&cpg CPG_MOD 911>;
183 resets = <&cpg 911>;
196 clocks = <&cpg CPG_MOD 910>;
[all …]
H A Dr8a7794.dtsi9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
71 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
82 clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
132 clocks = <&cpg CPG_MOD 402>;
134 resets = <&cpg 402>;
148 clocks = <&cpg CPG_MOD 912>;
150 resets = <&cpg 912>;
163 clocks = <&cpg CPG_MOD 911>;
165 resets = <&cpg 911>;
178 clocks = <&cpg CPG_MOD 910>;
[all …]

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