arm/dts/r8a77995.dtsi

9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
80 			clocks = <&cpg CPG_MOD 402>;
82 			resets = <&cpg 402>;
96 			clocks = <&cpg CPG_MOD 912>;
98 			resets = <&cpg 912>;
111 			clocks = <&cpg CPG_MOD 911>;
113 			resets = <&cpg 911>;
126 			clocks = <&cpg CPG_MOD 910>;
128 			resets = <&cpg 910>;
141 			clocks = <&cpg CPG_MOD 909>;
143 			resets = <&cpg 909>;
156 			clocks = <&cpg CPG_MOD 908>;
158 			resets = <&cpg 908>;
171 			clocks = <&cpg CPG_MOD 907>;
173 			resets = <&cpg 907>;
186 			clocks = <&cpg CPG_MOD 906>;
188 			resets = <&cpg 906>;
196 		cpg: clock-controller@e6150000 {  label
197 			compatible = "renesas,r8a77995-cpg-mssr";
223 			clocks = <&cpg CPG_MOD 522>;
225 			resets = <&cpg 522>;
240 			clocks = <&cpg CPG_MOD 407>;
242 			resets = <&cpg 407>;
251 			clocks = <&cpg CPG_MOD 520>,
252 				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
259 			resets = <&cpg 520>;
269 			clocks = <&cpg CPG_MOD 517>,
270 				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
276 			resets = <&cpg 517>;
287 			clocks = <&cpg CPG_MOD 931>;
289 			resets = <&cpg 931>;
304 			clocks = <&cpg CPG_MOD 930>;
306 			resets = <&cpg 930>;
321 			clocks = <&cpg CPG_MOD 929>;
323 			resets = <&cpg 929>;
338 			clocks = <&cpg CPG_MOD 928>;
340 			resets = <&cpg 928>;
353 			clocks = <&cpg CPG_MOD 914>,
354 			       <&cpg CPG_CORE R8A77995_CLK_CANFD>,
357 			assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
360 			resets = <&cpg 914>;
388 			clocks = <&cpg CPG_MOD 219>;
391 			resets = <&cpg 219>;
412 			clocks = <&cpg CPG_MOD 218>;
415 			resets = <&cpg 218>;
436 			clocks = <&cpg CPG_MOD 217>;
439 			resets = <&cpg 217>;
561 			clocks = <&cpg CPG_MOD 812>;
563 			resets = <&cpg 812>;
576 			clocks = <&cpg CPG_MOD 916>,
577 			       <&cpg CPG_CORE R8A77995_CLK_CANFD>,
580 			assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
583 			resets = <&cpg 916>;
592 			clocks = <&cpg CPG_MOD 915>,
593 			       <&cpg CPG_CORE R8A77995_CLK_CANFD>,
596 			assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
599 			resets = <&cpg 915>;
607 			clocks = <&cpg CPG_MOD 523>;
609 			resets = <&cpg 523>;
617 			clocks = <&cpg CPG_MOD 523>;
619 			resets = <&cpg 523>;
627 			clocks = <&cpg CPG_MOD 523>;
629 			resets = <&cpg 523>;
637 			clocks = <&cpg CPG_MOD 523>;
639 			resets = <&cpg 523>;
648 			clocks = <&cpg CPG_MOD 207>,
649 				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
656 			resets = <&cpg 207>;
665 			clocks = <&cpg CPG_MOD 206>,
666 				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
673 			resets = <&cpg 206>;
682 			clocks = <&cpg CPG_MOD 310>,
683 				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
690 			resets = <&cpg 310>;
699 			clocks = <&cpg CPG_MOD 204>,
700 				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
706 			resets = <&cpg 204>;
715 			clocks = <&cpg CPG_MOD 203>,
716 				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
722 			resets = <&cpg 203>;
731 			clocks = <&cpg CPG_MOD 202>,
732 				 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
739 			resets = <&cpg 202>;
748 			clocks = <&cpg CPG_MOD 211>;
753 			resets = <&cpg 211>;
764 			clocks = <&cpg CPG_MOD 210>;
769 			resets = <&cpg 210>;
780 			clocks = <&cpg CPG_MOD 209>;
784 			resets = <&cpg 209>;
795 			clocks = <&cpg CPG_MOD 208>;
799 			resets = <&cpg 208>;
809 			clocks = <&cpg CPG_MOD 807>;
811 			resets = <&cpg 807>;
820 			clocks = <&cpg CPG_MOD 703>;
824 			resets = <&cpg 703>;
832 			clocks = <&cpg CPG_MOD 703>;
837 			resets = <&cpg 703>;
846 			clocks = <&cpg CPG_MOD 703>;
848 			resets = <&cpg 703>;
858 			clocks = <&cpg CPG_MOD 312>;
861 			resets = <&cpg 312>;
876 			clocks = <&cpg CPG_MOD 408>;
879 			resets = <&cpg 408>;
886 			clocks = <&cpg CPG_MOD 627>;
888 			resets = <&cpg 627>;
896 			clocks = <&cpg CPG_MOD 623>;
898 			resets = <&cpg 623>;
906 			clocks = <&cpg CPG_MOD 622>;
908 			resets = <&cpg 622>;
915 			clocks = <&cpg CPG_MOD 607>;
917 			resets = <&cpg 607>;
924 			clocks = <&cpg CPG_MOD 603>;
926 			resets = <&cpg 603>;
933 			clocks = <&cpg CPG_MOD 602>;
935 			resets = <&cpg 602>;
944 			clocks = <&cpg CPG_MOD 724>,
945 				 <&cpg CPG_MOD 723>;