Lines Matching full:cpg
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
240 clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
255 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
256 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
259 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
262 power-domains = <&cpg>;
275 clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
276 <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
279 resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
282 power-domains = <&cpg>;
294 clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
295 <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
298 resets = <&cpg R9A07G054_SSI2_RST_M2_REG>;
301 power-domains = <&cpg>;
314 clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
315 <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
318 resets = <&cpg R9A07G054_SSI3_RST_M2_REG>;
321 power-domains = <&cpg>;
333 clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>;
334 resets = <&cpg R9A07G054_RSPI0_RST>;
337 power-domains = <&cpg>;
351 clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>;
352 resets = <&cpg R9A07G054_RSPI1_RST>;
355 power-domains = <&cpg>;
369 clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>;
370 resets = <&cpg R9A07G054_RSPI2_RST>;
373 power-domains = <&cpg>;
392 clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
394 power-domains = <&cpg>;
395 resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
411 clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
413 power-domains = <&cpg>;
414 resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
430 clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
432 power-domains = <&cpg>;
433 resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
449 clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
451 power-domains = <&cpg>;
452 resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
468 clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
470 power-domains = <&cpg>;
471 resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
483 clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
485 power-domains = <&cpg>;
486 resets = <&cpg R9A07G054_SCI0_RST>;
498 clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
500 power-domains = <&cpg>;
501 resets = <&cpg R9A07G054_SCI1_RST>;
519 clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>,
520 <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
523 assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;
525 resets = <&cpg R9A07G054_CANFD_RSTP_N>,
526 <&cpg R9A07G054_CANFD_RSTC_N>;
528 power-domains = <&cpg>;
554 clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
556 resets = <&cpg R9A07G054_I2C0_MRST>;
557 power-domains = <&cpg>;
576 clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
578 resets = <&cpg R9A07G054_I2C1_MRST>;
579 power-domains = <&cpg>;
598 clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
600 resets = <&cpg R9A07G054_I2C2_MRST>;
601 power-domains = <&cpg>;
620 clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
622 resets = <&cpg R9A07G054_I2C3_MRST>;
623 power-domains = <&cpg>;
631 clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
632 <&cpg CPG_MOD R9A07G054_ADC_PCLK>;
634 resets = <&cpg R9A07G054_ADC_PRESETN>,
635 <&cpg R9A07G054_ADC_ADRST_N>;
637 power-domains = <&cpg>;
673 clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>;
674 resets = <&cpg R9A07G054_TSU_PRESETN>;
675 power-domains = <&cpg>;
687 clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
688 <&cpg CPG_MOD R9A07G054_SPI_CLK>;
689 resets = <&cpg R9A07G054_SPI_RST>;
690 power-domains = <&cpg>;
699 clocks = <&cpg CPG_MOD R9A07G054_CRU_VCLK>,
700 <&cpg CPG_MOD R9A07G054_CRU_PCLK>,
701 <&cpg CPG_MOD R9A07G054_CRU_ACLK>;
707 resets = <&cpg R9A07G054_CRU_PRESETN>,
708 <&cpg R9A07G054_CRU_ARESETN>;
710 power-domains = <&cpg>;
744 clocks = <&cpg CPG_MOD R9A07G054_CRU_SYSCLK>,
745 <&cpg CPG_MOD R9A07G054_CRU_VCLK>,
746 <&cpg CPG_MOD R9A07G054_CRU_PCLK>;
748 resets = <&cpg R9A07G054_CRU_PRESETN>,
749 <&cpg R9A07G054_CRU_CMN_RSTB>;
751 power-domains = <&cpg>;
788 clocks = <&cpg CPG_MOD R9A07G054_MIPI_DSI_PLLCLK>,
789 <&cpg CPG_MOD R9A07G054_MIPI_DSI_SYSCLK>,
790 <&cpg CPG_MOD R9A07G054_MIPI_DSI_ACLK>,
791 <&cpg CPG_MOD R9A07G054_MIPI_DSI_PCLK>,
792 <&cpg CPG_MOD R9A07G054_MIPI_DSI_VCLK>,
793 <&cpg CPG_MOD R9A07G054_MIPI_DSI_LPCLK>;
795 resets = <&cpg R9A07G054_MIPI_DSI_CMN_RSTB>,
796 <&cpg R9A07G054_MIPI_DSI_ARESET_N>,
797 <&cpg R9A07G054_MIPI_DSI_PRESET_N>;
799 power-domains = <&cpg>;
808 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
809 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
810 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
812 power-domains = <&cpg>;
813 resets = <&cpg R9A07G054_LCDC_RESET_N>;
821 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
822 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
823 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
825 power-domains = <&cpg>;
826 resets = <&cpg R9A07G054_LCDC_RESET_N>;
829 cpg: clock-controller@11010000 { label
830 compatible = "renesas,r9a07g054-cpg";
861 clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
862 power-domains = <&cpg>;
863 resets = <&cpg R9A07G054_GPIO_RSTN>,
864 <&cpg R9A07G054_GPIO_PORT_RESETN>,
865 <&cpg R9A07G054_GPIO_SPARE_RESETN>;
936 clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
937 <&cpg CPG_MOD R9A07G054_IA55_PCLK>;
939 power-domains = <&cpg>;
940 resets = <&cpg R9A07G054_IA55_RESETN>;
970 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
971 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
973 power-domains = <&cpg>;
974 resets = <&cpg R9A07G054_DMAC_ARESETN>,
975 <&cpg R9A07G054_DMAC_RST_ASYNC>;
990 clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>,
991 <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>,
992 <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>;
994 power-domains = <&cpg>;
995 resets = <&cpg R9A07G054_GPU_RESETN>,
996 <&cpg R9A07G054_GPU_AXI_RESETN>,
997 <&cpg R9A07G054_GPU_ACE_RESETN>;
1018 clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
1019 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
1020 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
1021 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
1023 resets = <&cpg R9A07G054_SDHI0_IXRST>;
1024 power-domains = <&cpg>;
1034 clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
1035 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
1036 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
1037 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
1039 resets = <&cpg R9A07G054_SDHI1_IXRST>;
1040 power-domains = <&cpg>;
1053 clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
1054 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
1055 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1057 resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
1058 power-domains = <&cpg>;
1073 clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
1074 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
1075 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1077 resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
1078 power-domains = <&cpg>;
1088 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
1089 resets = <&cpg R9A07G054_USB_PRESETN>;
1090 power-domains = <&cpg>;
1099 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1100 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1102 <&cpg R9A07G054_USB_U2H0_HRESETN>;
1105 power-domains = <&cpg>;
1113 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1114 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1116 <&cpg R9A07G054_USB_U2H1_HRESETN>;
1119 power-domains = <&cpg>;
1127 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1128 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1130 <&cpg R9A07G054_USB_U2H0_HRESETN>;
1134 power-domains = <&cpg>;
1142 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1143 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1145 <&cpg R9A07G054_USB_U2H1_HRESETN>;
1149 power-domains = <&cpg>;
1158 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1159 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1162 power-domains = <&cpg>;
1171 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1172 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1175 power-domains = <&cpg>;
1187 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1188 <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>;
1190 <&cpg R9A07G054_USB_U2P_EXL_SYSRST>;
1194 power-domains = <&cpg>;
1202 clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>,
1203 <&cpg CPG_MOD R9A07G054_WDT0_CLK>;
1208 resets = <&cpg R9A07G054_WDT0_PRESETN>;
1209 power-domains = <&cpg>;
1217 clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
1218 <&cpg CPG_MOD R9A07G054_WDT1_CLK>;
1223 resets = <&cpg R9A07G054_WDT1_PRESETN>;
1224 power-domains = <&cpg>;
1233 clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
1234 resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
1235 power-domains = <&cpg>;
1244 clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
1245 resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
1246 power-domains = <&cpg>;
1255 clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
1256 resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
1257 power-domains = <&cpg>;