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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43 |
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| #
a4c125a8 |
| 27-Jul-2023 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Add MTU3a node
Add MTU3a node to R9A07G043 (RZ/{G2UL,Five}) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+ren
arm64: dts: renesas: r9a07g043: Add MTU3a node
Add MTU3a node to R9A07G043 (RZ/{G2UL,Five}) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230727081848.100834-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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Revision tags: v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20 |
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| #
05d11e2f |
| 15-Mar-2023 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: rzg2l: Add clock-names and reset-names to DMAC nodes
Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and
RZ/Five DMAC nodes.
Signed-off-by: Biju Das <biju.das.jz@bp.r
arm64: dts: renesas: rzg2l: Add clock-names and reset-names to DMAC nodes
Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and
RZ/Five DMAC nodes.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230315064726.22739-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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Revision tags: v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2 |
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| #
2a5c9891 |
| 17-Feb-2023 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels
From R01UH0968EJ0100 Rev.1.00 HW manual the interrupt numbers for SSI
channels have been updated,
SPI 329 - SSIF0 is now marked a
arm64: dts: renesas: r9a07g043: Update IRQ numbers for SSI channels
From R01UH0968EJ0100 Rev.1.00 HW manual the interrupt numbers for SSI
channels have been updated,
SPI 329 - SSIF0 is now marked as reserved
SPI 333 - SSIF1 is now marked as reserved
SPI 335 - SSIF2 is now marked as reserved
SPI 336 - SSIF2 is now marked as reserved
SPI 341 - SSIF3 is now marked as reserved
This patch drops the above IRQs from SoC DTSI.
Fixes: 559f2b0708c70 ("arm64: dts: renesas: r9a07g043: Add SSI{1,2,3} nodes and fillup the SSI0 stub node")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230217185225.43310-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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Revision tags: v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17 |
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| #
85169df7 |
| 02-Jan-2023 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
arm64: dts: renesas: r9a07g043u: Update pinctrl node to handle GPIO interrupts
Add required properties in pinctrl node to handle GPIO interrupts.
Note as IRQC is not enabled in RZ/Five the phandle
arm64: dts: renesas: r9a07g043u: Update pinctrl node to handle GPIO interrupts
Add required properties in pinctrl node to handle GPIO interrupts.
Note as IRQC is not enabled in RZ/Five the phandle for interrupt-parent
is added in RZ/G2UL specific dtsi so that RZ/Five pinctrl driver
continues without waiting for IRQC to probe.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230102221815.273719-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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Revision tags: v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4 |
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| #
b9a0be20 |
| 25-Oct-2022 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
Move RZ/G2UL SoC specific parts to r9a07g043u.dtsi so that
r9a07g043.dtsi can be shared with RZ/Five (RISC-V SoC).
Below are the
arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts
Move RZ/G2UL SoC specific parts to r9a07g043u.dtsi so that
r9a07g043.dtsi can be shared with RZ/Five (RISC-V SoC).
Below are the changes due to which SoC specific parts are moved to
r9a07g043u.dtsi:
- RZ/G2UL has Cortex-A55 (ARM64) whereas RZ/Five has AX45MP (RISC-V),
- RZ/G2UL has GICv3 as interrupt controller whereas RZ/Five has PLIC,
- RZ/G2UL has interrupts for SYSC block whereas interrupts are missing
for SYSC block on RZ/Five,
- RZ/G2UL has armv8-timer whereas RZ/Five has riscv-timer,
- RZ/G2UL has PSCI whereas RZ/Five have OpenSBI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20221025220629.79321-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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| #
49669da6 |
| 25-Oct-2022 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property
Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property so
that we can share the common
arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property
Introduce SOC_PERIPHERAL_IRQ() macro to specify interrupt property so
that we can share the common parts of the SoC DTSI with the RZ/Five
(RISC-V) SoC and the RZ/G2UL (ARM64) SoC.
This patch adds a new file r9a07g043u.dtsi to separate out RZ/G2UL
(ARM64) SoC specific parts. No functional changes (same DTB).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221025220629.79321-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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Revision tags: v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1 |
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| #
c02734d6 |
| 09-Oct-2022 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
arm64: dts: renesas: rzg2l: Drop WDT2 nodes
On members of the RZ/G2L family, WDT CH2 is specifically meant to check
the operation of the Cortex-M33 CPU. Using it from a Cortex-A55 CPU
would result
arm64: dts: renesas: rzg2l: Drop WDT2 nodes
On members of the RZ/G2L family, WDT CH2 is specifically meant to check
the operation of the Cortex-M33 CPU. Using it from a Cortex-A55 CPU
would result in unexpected behaviour. Hence drop all WDT2 nodes and
their references from the affected SoC and SoM DTSI files.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221009230044.10961-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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Revision tags: v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69 |
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| #
4ebf297b |
| 16-Sep-2022 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
arm64: dts: renesas: Adjust whitespace around '{'
Drop extra space around the '{' sign. No functional changes (same DTB).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link
arm64: dts: renesas: Adjust whitespace around '{'
Drop extra space around the '{' sign. No functional changes (same DTB).
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220916100251.20329-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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Revision tags: v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59 |
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| #
72a482db |
| 02-Aug-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Fix SCI{Rx,Tx} interrupt types
As per the RZ/G2UL Hardware User's Manual (Rev.1.00 Apr, 2022),
the interrupt type of SCI{Rx,Tx} is edge triggered.
Signed-off-by: Bij
arm64: dts: renesas: r9a07g043: Fix SCI{Rx,Tx} interrupt types
As per the RZ/G2UL Hardware User's Manual (Rev.1.00 Apr, 2022),
the interrupt type of SCI{Rx,Tx} is edge triggered.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Fixes: cf40c9689e5109bf ("arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC")
Link: https://lore.kernel.org/r/20220802101534.1401342-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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Revision tags: v5.19, v5.15.58 |
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| #
56f0a373 |
| 29-Jul-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Fix audio clk node names
Replace the clk node names audio-clk{1,2} with audio{1,2}-clk as per
the device tree specification.
Signed-off-by: Biju Das <biju.das.jz@bp.
arm64: dts: renesas: r9a07g043: Fix audio clk node names
Replace the clk node names audio-clk{1,2} with audio{1,2}-clk as per
the device tree specification.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220729084527.388023-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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| #
200d8e01 |
| 28-Jul-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Add DMA support to RSPI
Add DMA properties to RSPI nodes to support DMA operation.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org
arm64: dts: renesas: r9a07g043: Add DMA support to RSPI
Add DMA properties to RSPI nodes to support DMA operation.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220728122312.189766-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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Revision tags: v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38 |
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| #
9a71e89d |
| 05-May-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Add ADC node
Add ADC node to R9A07G043 (RZ/G2UL) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220505184353.512133
arm64: dts: renesas: r9a07g043: Add ADC node
Add ADC node to R9A07G043 (RZ/G2UL) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220505184353.512133-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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| #
470218e2 |
| 02-May-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Add SPI Multi I/O Bus controller node
Add SPI Multi I/O Bus controller node to R9A07G043 (RZ/G2UL) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Lin
arm64: dts: renesas: r9a07g043: Add SPI Multi I/O Bus controller node
Add SPI Multi I/O Bus controller node to R9A07G043 (RZ/G2UL) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220502190155.84496-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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Revision tags: v5.15.37 |
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| #
c2ff5c02 |
| 01-May-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Create thermal zone to support IPA
Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supp
arm64: dts: renesas: r9a07g043: Create thermal zone to support IPA
Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supports power extension.
Based on the work done by Dien Pham <dien.pham.ry@renesas.com>
and others for r8a77990 SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501112926.47024-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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| #
91e548da |
| 01-May-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Add TSU node
Add TSU node to RZ/G2UL SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501112926.47024-5-biju.das.j
arm64: dts: renesas: r9a07g043: Add TSU node
Add TSU node to RZ/G2UL SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501112926.47024-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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| #
e6a9acc3 |
| 01-May-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Add OPP table
Add OPP table for RZ/G2UL SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501112926.47024-4-biju.das.jz@
arm64: dts: renesas: r9a07g043: Add OPP table
Add OPP table for RZ/G2UL SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501112926.47024-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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| #
22ec8689 |
| 01-May-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Add RSPI{0,1,2} nodes
Add RSPI{0,1,2} nodes to R9A07G043 (RZ/G2UL) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/202
arm64: dts: renesas: r9a07g043: Add RSPI{0,1,2} nodes
Add RSPI{0,1,2} nodes to R9A07G043 (RZ/G2UL) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501112926.47024-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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|
Revision tags: v5.15.36 |
|
| #
a8352a51 |
| 25-Apr-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Fillup the WDT{0,2} stub nodes
Fillup the WDT{0,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad
arm64: dts: renesas: r9a07g043: Fillup the WDT{0,2} stub nodes
Fillup the WDT{0,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425170530.200921-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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| #
e42faad1 |
| 25-Apr-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Fillup the OSTM{0,1,2} stub nodes
Fillup the OSTM{0,1,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by
arm64: dts: renesas: r9a07g043: Fillup the OSTM{0,1,2} stub nodes
Fillup the OSTM{0,1,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425170530.200921-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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| #
1de1b448 |
| 25-Apr-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Fillup the CANFD stub node
Fillup the CANFD stub node in RZ/G2UL (R9A07G043) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhaka
arm64: dts: renesas: r9a07g043: Fillup the CANFD stub node
Fillup the CANFD stub node in RZ/G2UL (R9A07G043) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425170530.200921-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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| #
f52e1409 |
| 25-Apr-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Add USB2.0 support
Add USB2.0 host and device support by filling usb phy control,
phy, device and host stub nodes in RZ/G2UL SoC dtsi.
Signed-off-by: Biju Das <biju.
arm64: dts: renesas: r9a07g043: Add USB2.0 support
Add USB2.0 host and device support by filling usb phy control,
phy, device and host stub nodes in RZ/G2UL SoC dtsi.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425170530.200921-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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| #
559f2b07 |
| 25-Apr-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Add SSI{1,2,3} nodes and fillup the SSI0 stub node
Add SSI{1,2,3} nodes and fillup the SSI0 stub node in RZ/G2UL
(R9A07G043) SoC DTSI.
Signed-off-by: Biju Das <biju.
arm64: dts: renesas: r9a07g043: Add SSI{1,2,3} nodes and fillup the SSI0 stub node
Add SSI{1,2,3} nodes and fillup the SSI0 stub node in RZ/G2UL
(R9A07G043) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425170530.200921-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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| #
bc9e1dbb |
| 25-Apr-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Add I2C2 node and fillup the I2C{0,1,3} stub nodes
Add I2C2 node and fillup the I2C{0,1,3} stub nodes in RZ/G2UL
(R9A07G043) SoC DTSI.
Signed-off-by: Biju Das <biju.
arm64: dts: renesas: r9a07g043: Add I2C2 node and fillup the I2C{0,1,3} stub nodes
Add I2C2 node and fillup the I2C{0,1,3} stub nodes in RZ/G2UL
(R9A07G043) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425170530.200921-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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|
Revision tags: v5.15.35, v5.15.34, v5.15.33 |
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| #
13ea8b35 |
| 02-Apr-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Add GbEthernet nodes
Add Gigabit Ethernet{0,1} nodes to SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-
arm64: dts: renesas: r9a07g043: Add GbEthernet nodes
Add Gigabit Ethernet{0,1} nodes to SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402081328.26292-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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| #
20e63d39 |
| 02-Apr-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
arm64: dts: renesas: r9a07g043: Add SDHI nodes
Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp
arm64: dts: renesas: r9a07g043: Add SDHI nodes
Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402081328.26292-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
show more ...
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