3cc7942a | 22-Jun-2018 |
Bibek Basu <bbasu@nvidia.com> |
ARM: tegra: implement RAM repair
RAM repair has a few pre-requisites: 1) PMIC power supply (rail) enabled. 2) PMC CRAIL power partition powered. 3) Fuse clock active (it's the default). 4) PLLP resh
ARM: tegra: implement RAM repair
RAM repair has a few pre-requisites: 1) PMIC power supply (rail) enabled. 2) PMC CRAIL power partition powered. 3) Fuse clock active (it's the default). 4) PLLP reshift branch enabled (it's the default, when PLLP is active).
RAM repair also only need run whenever specific partitions are powered (main SoC and CCPLEX respectively); RAM repair does not need to be triggered when any other partition changes state.
start_cpu() needs to be re-ordered slightly to match these requirements. Note that C0NC and CE0 aren't required for RAM repair to operate, but they also do no harm, so the entire of powerup_cpus() is moved rather than splitting it up. The call to remove_cpu_resets() is moved last to ensure that all other actions complete before releasing reset; since the PMC power partitions are now enabled early, releasing reset is what causes the CPUs to start executing code, and RAM repair must complete before the CPU boots.
Note that this commit is the result of squashing a numbmer of commits in NVIDIA's downstream L4T branch, hence the multiple signoffs below.
Signed-off-by: Bibek Basu <bbasu@nvidia.com> Signed-off-by: Sandipan Patra <spatra@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
aba11d44 | 08-Sep-2015 |
Thierry Reding <treding@nvidia.com> |
ARM: tegra124: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up a
ARM: tegra124: Clear IDDQ when enabling PLLC
Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence").
Reported-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|
79cf644e | 21-Apr-2015 |
Thierry Reding <treding@nvidia.com> |
ARM: tegra: Enable SMMU when going non-secure
Make sure to enable the SMMU when booting the kernel in non-secure mode. This is necessary because some of the SMMU registers are restricted to TrustZon
ARM: tegra: Enable SMMU when going non-secure
Make sure to enable the SMMU when booting the kernel in non-secure mode. This is necessary because some of the SMMU registers are restricted to TrustZone-secured requestors, hence the kernel wouldn't be able to turn the SMMU on. At the same time, enable translation for all memory clients for the same reasons. The kernel will still be able to control SMMU IOVA translation using the per-SWGROUP enable bits.
Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
show more ...
|