1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_PHYS_64BIT 15 16 #ifdef CONFIG_RAMBOOT_PBL 17 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 18 #ifdef CONFIG_T1040RDB 19 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg 20 #endif 21 #ifdef CONFIG_T1042RDB_PI 22 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg 23 #endif 24 25 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 26 #define CONFIG_SPL_ENV_SUPPORT 27 #define CONFIG_SPL_SERIAL_SUPPORT 28 #define CONFIG_SPL_FLUSH_IMAGE 29 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 30 #define CONFIG_SPL_LIBGENERIC_SUPPORT 31 #define CONFIG_SPL_LIBCOMMON_SUPPORT 32 #define CONFIG_SPL_I2C_SUPPORT 33 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 34 #define CONFIG_FSL_LAW /* Use common FSL init code */ 35 #define CONFIG_SYS_TEXT_BASE 0x00201000 36 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 37 #define CONFIG_SPL_PAD_TO 0x40000 38 #define CONFIG_SPL_MAX_SIZE 0x28000 39 #ifdef CONFIG_SPL_BUILD 40 #define CONFIG_SPL_SKIP_RELOCATE 41 #define CONFIG_SPL_COMMON_INIT_DDR 42 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 43 #define CONFIG_SYS_NO_FLASH 44 #endif 45 #define RESET_VECTOR_OFFSET 0x27FFC 46 #define BOOT_PAGE_OFFSET 0x27000 47 48 #ifdef CONFIG_NAND 49 #define CONFIG_SPL_NAND_SUPPORT 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 51 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 55 #define CONFIG_SPL_NAND_BOOT 56 #endif 57 58 #ifdef CONFIG_SPIFLASH 59 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 60 #define CONFIG_SPL_SPI_SUPPORT 61 #define CONFIG_SPL_SPI_FLASH_SUPPORT 62 #define CONFIG_SPL_SPI_FLASH_MINIMAL 63 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 66 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 67 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 68 #ifndef CONFIG_SPL_BUILD 69 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 70 #endif 71 #define CONFIG_SPL_SPI_BOOT 72 #endif 73 74 #ifdef CONFIG_SDCARD 75 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 76 #define CONFIG_SPL_MMC_SUPPORT 77 #define CONFIG_SPL_MMC_MINIMAL 78 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 79 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 80 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 81 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 82 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 83 #ifndef CONFIG_SPL_BUILD 84 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 85 #endif 86 #define CONFIG_SPL_MMC_BOOT 87 #endif 88 89 #endif 90 91 /* High Level Configuration Options */ 92 #define CONFIG_BOOKE 93 #define CONFIG_E500 /* BOOKE e500 family */ 94 #define CONFIG_E500MC /* BOOKE e500mc family */ 95 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 96 #define CONFIG_MP /* support multiple processors */ 97 98 /* support deep sleep */ 99 #define CONFIG_DEEP_SLEEP 100 #define CONFIG_SILENT_CONSOLE 101 102 #ifndef CONFIG_SYS_TEXT_BASE 103 #define CONFIG_SYS_TEXT_BASE 0xeff40000 104 #endif 105 106 #ifndef CONFIG_RESET_VECTOR_ADDRESS 107 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 108 #endif 109 110 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 111 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 112 #define CONFIG_FSL_IFC /* Enable IFC Support */ 113 #define CONFIG_PCI /* Enable PCI/PCIE */ 114 #define CONFIG_PCI_INDIRECT_BRIDGE 115 #define CONFIG_PCIE1 /* PCIE controler 1 */ 116 #define CONFIG_PCIE2 /* PCIE controler 2 */ 117 #define CONFIG_PCIE3 /* PCIE controler 3 */ 118 #define CONFIG_PCIE4 /* PCIE controler 4 */ 119 120 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 121 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 122 123 #define CONFIG_FSL_LAW /* Use common FSL init code */ 124 125 #define CONFIG_ENV_OVERWRITE 126 127 #ifndef CONFIG_SYS_NO_FLASH 128 #define CONFIG_FLASH_CFI_DRIVER 129 #define CONFIG_SYS_FLASH_CFI 130 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 131 #endif 132 133 #if defined(CONFIG_SPIFLASH) 134 #define CONFIG_SYS_EXTRA_ENV_RELOC 135 #define CONFIG_ENV_IS_IN_SPI_FLASH 136 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 137 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 138 #define CONFIG_ENV_SECT_SIZE 0x10000 139 #elif defined(CONFIG_SDCARD) 140 #define CONFIG_SYS_EXTRA_ENV_RELOC 141 #define CONFIG_ENV_IS_IN_MMC 142 #define CONFIG_SYS_MMC_ENV_DEV 0 143 #define CONFIG_ENV_SIZE 0x2000 144 #define CONFIG_ENV_OFFSET (512 * 0x800) 145 #elif defined(CONFIG_NAND) 146 #define CONFIG_SYS_EXTRA_ENV_RELOC 147 #define CONFIG_ENV_IS_IN_NAND 148 #define CONFIG_ENV_SIZE 0x2000 149 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 150 #else 151 #define CONFIG_ENV_IS_IN_FLASH 152 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 153 #define CONFIG_ENV_SIZE 0x2000 154 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 155 #endif 156 157 #define CONFIG_SYS_CLK_FREQ 100000000 158 #define CONFIG_DDR_CLK_FREQ 66666666 159 160 /* 161 * These can be toggled for performance analysis, otherwise use default. 162 */ 163 #define CONFIG_SYS_CACHE_STASHING 164 #define CONFIG_BACKSIDE_L2_CACHE 165 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 166 #define CONFIG_BTB /* toggle branch predition */ 167 #define CONFIG_DDR_ECC 168 #ifdef CONFIG_DDR_ECC 169 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 170 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 171 #endif 172 173 #define CONFIG_ENABLE_36BIT_PHYS 174 175 #define CONFIG_ADDR_MAP 176 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 177 178 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 179 #define CONFIG_SYS_MEMTEST_END 0x00400000 180 #define CONFIG_SYS_ALT_MEMTEST 181 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 182 183 /* 184 * Config the L3 Cache as L3 SRAM 185 */ 186 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 187 #define CONFIG_SYS_L3_SIZE 256 << 10 188 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 189 #ifdef CONFIG_RAMBOOT_PBL 190 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 191 #endif 192 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 193 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 194 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 195 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 196 197 #define CONFIG_SYS_DCSRBAR 0xf0000000 198 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 199 200 /* 201 * DDR Setup 202 */ 203 #define CONFIG_VERY_BIG_RAM 204 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 205 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 206 207 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 208 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 209 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 210 211 #define CONFIG_DDR_SPD 212 #define CONFIG_SYS_DDR_RAW_TIMING 213 #define CONFIG_SYS_FSL_DDR3 214 215 #define CONFIG_SYS_SPD_BUS_NUM 0 216 #define SPD_EEPROM_ADDRESS 0x51 217 218 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 219 220 /* 221 * IFC Definitions 222 */ 223 #define CONFIG_SYS_FLASH_BASE 0xe8000000 224 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 225 226 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 227 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 228 CSPR_PORT_SIZE_16 | \ 229 CSPR_MSEL_NOR | \ 230 CSPR_V) 231 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 232 233 /* 234 * TDM Definition 235 */ 236 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 237 238 /* NOR Flash Timing Params */ 239 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 240 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 241 FTIM0_NOR_TEADC(0x5) | \ 242 FTIM0_NOR_TEAHC(0x5)) 243 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 244 FTIM1_NOR_TRAD_NOR(0x1A) |\ 245 FTIM1_NOR_TSEQRAD_NOR(0x13)) 246 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 247 FTIM2_NOR_TCH(0x4) | \ 248 FTIM2_NOR_TWPH(0x0E) | \ 249 FTIM2_NOR_TWP(0x1c)) 250 #define CONFIG_SYS_NOR_FTIM3 0x0 251 252 #define CONFIG_SYS_FLASH_QUIET_TEST 253 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 254 255 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 256 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 257 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 258 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 259 260 #define CONFIG_SYS_FLASH_EMPTY_INFO 261 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 262 263 /* CPLD on IFC */ 264 #define CPLD_LBMAP_MASK 0x3F 265 #define CPLD_BANK_SEL_MASK 0x07 266 #define CPLD_BANK_OVERRIDE 0x40 267 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 268 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 269 #define CPLD_LBMAP_RESET 0xFF 270 #define CPLD_LBMAP_SHIFT 0x03 271 272 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 273 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 274 #define CONFIG_SYS_CSPR2_EXT (0xf) 275 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 276 | CSPR_PORT_SIZE_8 \ 277 | CSPR_MSEL_GPCM \ 278 | CSPR_V) 279 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 280 #define CONFIG_SYS_CSOR2 0x0 281 /* CPLD Timing parameters for IFC CS2 */ 282 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 283 FTIM0_GPCM_TEADC(0x0e) | \ 284 FTIM0_GPCM_TEAHC(0x0e)) 285 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 286 FTIM1_GPCM_TRAD(0x1f)) 287 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 288 FTIM2_GPCM_TCH(0x8) | \ 289 FTIM2_GPCM_TWP(0x1f)) 290 #define CONFIG_SYS_CS2_FTIM3 0x0 291 292 /* NAND Flash on IFC */ 293 #define CONFIG_NAND_FSL_IFC 294 #define CONFIG_SYS_NAND_BASE 0xff800000 295 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 296 297 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 298 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 299 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 300 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 301 | CSPR_V) 302 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 303 304 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 305 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 306 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 307 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 308 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 309 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 310 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 311 312 #define CONFIG_SYS_NAND_ONFI_DETECTION 313 314 /* ONFI NAND Flash mode0 Timing Params */ 315 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 316 FTIM0_NAND_TWP(0x18) | \ 317 FTIM0_NAND_TWCHT(0x07) | \ 318 FTIM0_NAND_TWH(0x0a)) 319 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 320 FTIM1_NAND_TWBE(0x39) | \ 321 FTIM1_NAND_TRR(0x0e) | \ 322 FTIM1_NAND_TRP(0x18)) 323 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 324 FTIM2_NAND_TREH(0x0a) | \ 325 FTIM2_NAND_TWHRE(0x1e)) 326 #define CONFIG_SYS_NAND_FTIM3 0x0 327 328 #define CONFIG_SYS_NAND_DDR_LAW 11 329 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 330 #define CONFIG_SYS_MAX_NAND_DEVICE 1 331 #define CONFIG_MTD_NAND_VERIFY_WRITE 332 #define CONFIG_CMD_NAND 333 334 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 335 336 #if defined(CONFIG_NAND) 337 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 338 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 339 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 340 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 341 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 342 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 343 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 344 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 345 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 346 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 347 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 348 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 349 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 350 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 351 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 352 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 353 #else 354 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 355 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 356 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 357 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 358 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 359 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 360 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 361 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 362 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 363 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 364 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 365 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 366 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 367 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 368 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 369 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 370 #endif 371 372 #ifdef CONFIG_SPL_BUILD 373 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 374 #else 375 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 376 #endif 377 378 #if defined(CONFIG_RAMBOOT_PBL) 379 #define CONFIG_SYS_RAMBOOT 380 #endif 381 382 #define CONFIG_BOARD_EARLY_INIT_R 383 #define CONFIG_MISC_INIT_R 384 385 #define CONFIG_HWCONFIG 386 387 /* define to use L1 as initial stack */ 388 #define CONFIG_L1_INIT_RAM 389 #define CONFIG_SYS_INIT_RAM_LOCK 390 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 391 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 392 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 393 /* The assembler doesn't like typecast */ 394 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 395 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 396 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 397 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 398 399 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 400 GENERATED_GBL_DATA_SIZE) 401 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 402 403 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 404 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 405 406 /* Serial Port - controlled on board with jumper J8 407 * open - index 2 408 * shorted - index 1 409 */ 410 #define CONFIG_CONS_INDEX 1 411 #define CONFIG_SYS_NS16550 412 #define CONFIG_SYS_NS16550_SERIAL 413 #define CONFIG_SYS_NS16550_REG_SIZE 1 414 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 415 416 #define CONFIG_SYS_BAUDRATE_TABLE \ 417 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 418 419 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 420 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 421 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 422 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 423 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 424 #ifndef CONFIG_SPL_BUILD 425 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 426 #endif 427 428 /* Use the HUSH parser */ 429 #define CONFIG_SYS_HUSH_PARSER 430 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 431 432 /* pass open firmware flat tree */ 433 #define CONFIG_OF_LIBFDT 434 #define CONFIG_OF_BOARD_SETUP 435 #define CONFIG_OF_STDOUT_VIA_ALIAS 436 437 /* new uImage format support */ 438 #define CONFIG_FIT 439 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 440 441 /* I2C */ 442 #define CONFIG_SYS_I2C 443 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 444 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 445 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 446 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 447 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 448 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 449 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 450 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 451 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 452 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 453 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 454 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 455 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 456 457 /* I2C bus multiplexer */ 458 #define I2C_MUX_PCA_ADDR 0x70 459 #ifdef CONFIG_T1040RDB 460 #define I2C_MUX_CH_DEFAULT 0x8 461 #endif 462 463 #ifdef CONFIG_T1042RDB_PI 464 /* 465 * RTC configuration 466 */ 467 #define RTC 468 #define CONFIG_RTC_DS1337 1 469 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 470 471 /*DVI encoder*/ 472 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 473 #endif 474 475 /* 476 * eSPI - Enhanced SPI 477 */ 478 #define CONFIG_FSL_ESPI 479 #define CONFIG_SPI_FLASH 480 #define CONFIG_SPI_FLASH_STMICRO 481 #define CONFIG_CMD_SF 482 #define CONFIG_SF_DEFAULT_SPEED 10000000 483 #define CONFIG_SF_DEFAULT_MODE 0 484 #define CONFIG_ENV_SPI_BUS 0 485 #define CONFIG_ENV_SPI_CS 0 486 #define CONFIG_ENV_SPI_MAX_HZ 10000000 487 #define CONFIG_ENV_SPI_MODE 0 488 489 /* 490 * General PCI 491 * Memory space is mapped 1-1, but I/O space must start from 0. 492 */ 493 494 #ifdef CONFIG_PCI 495 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 496 #ifdef CONFIG_PCIE1 497 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 498 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 499 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 500 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 501 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 502 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 503 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 504 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 505 #endif 506 507 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 508 #ifdef CONFIG_PCIE2 509 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 510 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 511 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 512 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 513 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 514 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 515 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 516 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 517 #endif 518 519 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 520 #ifdef CONFIG_PCIE3 521 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 522 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 523 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 524 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 525 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 526 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 527 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 528 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 529 #endif 530 531 /* controller 4, Base address 203000 */ 532 #ifdef CONFIG_PCIE4 533 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 534 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 535 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 536 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 537 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 538 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 539 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 540 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 541 #endif 542 543 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 544 #define CONFIG_E1000 545 546 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 547 #define CONFIG_DOS_PARTITION 548 #endif /* CONFIG_PCI */ 549 550 /* SATA */ 551 #define CONFIG_FSL_SATA_V2 552 #ifdef CONFIG_FSL_SATA_V2 553 #define CONFIG_LIBATA 554 #define CONFIG_FSL_SATA 555 556 #define CONFIG_SYS_SATA_MAX_DEVICE 1 557 #define CONFIG_SATA1 558 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 559 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 560 561 #define CONFIG_LBA48 562 #define CONFIG_CMD_SATA 563 #define CONFIG_DOS_PARTITION 564 #define CONFIG_CMD_EXT2 565 #endif 566 567 /* 568 * USB 569 */ 570 #define CONFIG_HAS_FSL_DR_USB 571 572 #ifdef CONFIG_HAS_FSL_DR_USB 573 #define CONFIG_USB_EHCI 574 575 #ifdef CONFIG_USB_EHCI 576 #define CONFIG_CMD_USB 577 #define CONFIG_USB_STORAGE 578 #define CONFIG_USB_EHCI_FSL 579 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 580 #define CONFIG_CMD_EXT2 581 #endif 582 #endif 583 584 #define CONFIG_MMC 585 586 #ifdef CONFIG_MMC 587 #define CONFIG_FSL_ESDHC 588 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 589 #define CONFIG_CMD_MMC 590 #define CONFIG_GENERIC_MMC 591 #define CONFIG_CMD_EXT2 592 #define CONFIG_CMD_FAT 593 #define CONFIG_DOS_PARTITION 594 #endif 595 596 /* Qman/Bman */ 597 #ifndef CONFIG_NOBQFMAN 598 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 599 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 600 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 601 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 602 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 603 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 604 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 605 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 606 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 607 608 #define CONFIG_SYS_DPAA_FMAN 609 #define CONFIG_SYS_DPAA_PME 610 611 #ifdef CONFIG_T1040RDB 612 #define CONFIG_QE 613 #define CONFIG_U_QE 614 #endif 615 616 /* Default address of microcode for the Linux Fman driver */ 617 #if defined(CONFIG_SPIFLASH) 618 /* 619 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 620 * env, so we got 0x110000. 621 */ 622 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 623 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 624 #elif defined(CONFIG_SDCARD) 625 /* 626 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 627 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 628 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 629 */ 630 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 631 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 632 #elif defined(CONFIG_NAND) 633 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 634 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 635 #else 636 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 637 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 638 #endif 639 640 #ifdef CONFIG_T1040RDB 641 #if defined(CONFIG_SPIFLASH) 642 #define CONFIG_SYS_QE_FW_ADDR 0x130000 643 #elif defined(CONFIG_SDCARD) 644 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 645 #elif defined(CONFIG_NAND) 646 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 647 #else 648 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 649 #endif 650 #endif 651 652 653 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 654 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 655 #endif /* CONFIG_NOBQFMAN */ 656 657 #ifdef CONFIG_SYS_DPAA_FMAN 658 #define CONFIG_FMAN_ENET 659 #define CONFIG_PHY_VITESSE 660 #define CONFIG_PHY_REALTEK 661 #endif 662 663 #ifdef CONFIG_FMAN_ENET 664 #ifdef CONFIG_T1040RDB 665 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 666 #endif 667 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 668 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 669 670 #define CONFIG_MII /* MII PHY management */ 671 #define CONFIG_ETHPRIME "FM1@DTSEC4" 672 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 673 #endif 674 675 /* 676 * Environment 677 */ 678 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 679 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 680 681 /* 682 * Command line configuration. 683 */ 684 #include <config_cmd_default.h> 685 686 #ifdef CONFIG_T1042RDB_PI 687 #define CONFIG_CMD_DATE 688 #endif 689 #define CONFIG_CMD_DHCP 690 #define CONFIG_CMD_ELF 691 #define CONFIG_CMD_ERRATA 692 #define CONFIG_CMD_GREPENV 693 #define CONFIG_CMD_IRQ 694 #define CONFIG_CMD_I2C 695 #define CONFIG_CMD_MII 696 #define CONFIG_CMD_PING 697 #define CONFIG_CMD_REGINFO 698 #define CONFIG_CMD_SETEXPR 699 700 #ifdef CONFIG_PCI 701 #define CONFIG_CMD_PCI 702 #define CONFIG_CMD_NET 703 #endif 704 705 /* 706 * Miscellaneous configurable options 707 */ 708 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 709 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 710 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 711 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 712 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 713 #ifdef CONFIG_CMD_KGDB 714 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 715 #else 716 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 717 #endif 718 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 719 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 720 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 721 722 /* 723 * For booting Linux, the board info and command line data 724 * have to be in the first 64 MB of memory, since this is 725 * the maximum mapped by the Linux kernel during initialization. 726 */ 727 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 728 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 729 730 #ifdef CONFIG_CMD_KGDB 731 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 732 #endif 733 734 /* 735 * Dynamic MTD Partition support with mtdparts 736 */ 737 #ifndef CONFIG_SYS_NO_FLASH 738 #define CONFIG_MTD_DEVICE 739 #define CONFIG_MTD_PARTITIONS 740 #define CONFIG_CMD_MTDPARTS 741 #define CONFIG_FLASH_CFI_MTD 742 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 743 "spi0=spife110000.0" 744 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 745 "128k(dtb),96m(fs),-(user);"\ 746 "fff800000.flash:2m(uboot),9m(kernel),"\ 747 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 748 "2m(uboot),9m(kernel),128k(dtb),-(user)" 749 #endif 750 751 /* 752 * Environment Configuration 753 */ 754 #define CONFIG_ROOTPATH "/opt/nfsroot" 755 #define CONFIG_BOOTFILE "uImage" 756 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 757 758 /* default location for tftp and bootm */ 759 #define CONFIG_LOADADDR 1000000 760 761 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ 762 763 #define CONFIG_BAUDRATE 115200 764 765 #define __USB_PHY_TYPE utmi 766 767 #ifdef CONFIG_T1040RDB 768 #define FDTFILE "t1040rdb/t1040rdb.dtb" 769 #define RAMDISKFILE "t1040rdb/ramdisk.uboot" 770 #elif CONFIG_T1042RDB_PI 771 #define FDTFILE "t1040rdb_pi/t1040rdb_pi.dtb" 772 #define RAMDISKFILE "t1040rdb_pi/ramdisk.uboot" 773 #endif 774 775 #define CONFIG_EXTRA_ENV_SETTINGS \ 776 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 777 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 778 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 779 "netdev=eth0\0" \ 780 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 781 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 782 "tftpflash=tftpboot $loadaddr $uboot && " \ 783 "protect off $ubootaddr +$filesize && " \ 784 "erase $ubootaddr +$filesize && " \ 785 "cp.b $loadaddr $ubootaddr $filesize && " \ 786 "protect on $ubootaddr +$filesize && " \ 787 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 788 "consoledev=ttyS0\0" \ 789 "ramdiskaddr=2000000\0" \ 790 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 791 "fdtaddr=c00000\0" \ 792 "fdtfile=" __stringify(FDTFILE) "\0" \ 793 "bdev=sda3\0" 794 795 #define CONFIG_LINUX \ 796 "setenv bootargs root=/dev/ram rw " \ 797 "console=$consoledev,$baudrate $othbootargs;" \ 798 "setenv ramdiskaddr 0x02000000;" \ 799 "setenv fdtaddr 0x00c00000;" \ 800 "setenv loadaddr 0x1000000;" \ 801 "bootm $loadaddr $ramdiskaddr $fdtaddr" 802 803 #define CONFIG_HDBOOT \ 804 "setenv bootargs root=/dev/$bdev rw " \ 805 "console=$consoledev,$baudrate $othbootargs;" \ 806 "tftp $loadaddr $bootfile;" \ 807 "tftp $fdtaddr $fdtfile;" \ 808 "bootm $loadaddr - $fdtaddr" 809 810 #define CONFIG_NFSBOOTCOMMAND \ 811 "setenv bootargs root=/dev/nfs rw " \ 812 "nfsroot=$serverip:$rootpath " \ 813 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 814 "console=$consoledev,$baudrate $othbootargs;" \ 815 "tftp $loadaddr $bootfile;" \ 816 "tftp $fdtaddr $fdtfile;" \ 817 "bootm $loadaddr - $fdtaddr" 818 819 #define CONFIG_RAMBOOTCOMMAND \ 820 "setenv bootargs root=/dev/ram rw " \ 821 "console=$consoledev,$baudrate $othbootargs;" \ 822 "tftp $ramdiskaddr $ramdiskfile;" \ 823 "tftp $loadaddr $bootfile;" \ 824 "tftp $fdtaddr $fdtfile;" \ 825 "bootm $loadaddr $ramdiskaddr $fdtaddr" 826 827 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 828 829 #ifdef CONFIG_SECURE_BOOT 830 #include <asm/fsl_secure_boot.h> 831 #endif 832 833 #endif /* __CONFIG_H */ 834