1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #define CONFIG_T104xRDB 14 #define CONFIG_PHYS_64BIT 15 #define CONFIG_SYS_GENERIC_BOARD 16 #define CONFIG_DISPLAY_BOARDINFO 17 18 #define CONFIG_E500 /* BOOKE e500 family */ 19 #include <asm/config_mpc85xx.h> 20 21 #ifdef CONFIG_RAMBOOT_PBL 22 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 23 #ifdef CONFIG_T1040RDB 24 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg 25 #endif 26 #ifdef CONFIG_T1042RDB_PI 27 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg 28 #endif 29 #ifdef CONFIG_T1042RDB 30 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg 31 #endif 32 33 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 34 #define CONFIG_SPL_ENV_SUPPORT 35 #define CONFIG_SPL_SERIAL_SUPPORT 36 #define CONFIG_SPL_FLUSH_IMAGE 37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 38 #define CONFIG_SPL_LIBGENERIC_SUPPORT 39 #define CONFIG_SPL_LIBCOMMON_SUPPORT 40 #define CONFIG_SPL_I2C_SUPPORT 41 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 42 #define CONFIG_FSL_LAW /* Use common FSL init code */ 43 #define CONFIG_SYS_TEXT_BASE 0x30001000 44 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 45 #define CONFIG_SPL_PAD_TO 0x40000 46 #define CONFIG_SPL_MAX_SIZE 0x28000 47 #ifdef CONFIG_SPL_BUILD 48 #define CONFIG_SPL_SKIP_RELOCATE 49 #define CONFIG_SPL_COMMON_INIT_DDR 50 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 51 #define CONFIG_SYS_NO_FLASH 52 #endif 53 #define RESET_VECTOR_OFFSET 0x27FFC 54 #define BOOT_PAGE_OFFSET 0x27000 55 56 #ifdef CONFIG_NAND 57 #define CONFIG_SPL_NAND_SUPPORT 58 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 59 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 60 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 61 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 62 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 63 #define CONFIG_SPL_NAND_BOOT 64 #endif 65 66 #ifdef CONFIG_SPIFLASH 67 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 68 #define CONFIG_SPL_SPI_SUPPORT 69 #define CONFIG_SPL_SPI_FLASH_SUPPORT 70 #define CONFIG_SPL_SPI_FLASH_MINIMAL 71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 75 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 76 #ifndef CONFIG_SPL_BUILD 77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 78 #endif 79 #define CONFIG_SPL_SPI_BOOT 80 #endif 81 82 #ifdef CONFIG_SDCARD 83 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 84 #define CONFIG_SPL_MMC_SUPPORT 85 #define CONFIG_SPL_MMC_MINIMAL 86 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 87 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 88 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 89 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 90 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 91 #ifndef CONFIG_SPL_BUILD 92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 93 #endif 94 #define CONFIG_SPL_MMC_BOOT 95 #endif 96 97 #endif 98 99 /* High Level Configuration Options */ 100 #define CONFIG_BOOKE 101 #define CONFIG_E500MC /* BOOKE e500mc family */ 102 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 103 #define CONFIG_MP /* support multiple processors */ 104 105 /* support deep sleep */ 106 #define CONFIG_DEEP_SLEEP 107 #if defined(CONFIG_DEEP_SLEEP) 108 #define CONFIG_BOARD_EARLY_INIT_F 109 #define CONFIG_SILENT_CONSOLE 110 #endif 111 112 #ifndef CONFIG_SYS_TEXT_BASE 113 #define CONFIG_SYS_TEXT_BASE 0xeff40000 114 #endif 115 116 #ifndef CONFIG_RESET_VECTOR_ADDRESS 117 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 118 #endif 119 120 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 121 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 122 #define CONFIG_FSL_IFC /* Enable IFC Support */ 123 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 124 #define CONFIG_PCI /* Enable PCI/PCIE */ 125 #define CONFIG_PCI_INDIRECT_BRIDGE 126 #define CONFIG_PCIE1 /* PCIE controler 1 */ 127 #define CONFIG_PCIE2 /* PCIE controler 2 */ 128 #define CONFIG_PCIE3 /* PCIE controler 3 */ 129 #define CONFIG_PCIE4 /* PCIE controler 4 */ 130 131 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 132 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 133 134 #define CONFIG_FSL_LAW /* Use common FSL init code */ 135 136 #define CONFIG_ENV_OVERWRITE 137 138 #ifndef CONFIG_SYS_NO_FLASH 139 #define CONFIG_FLASH_CFI_DRIVER 140 #define CONFIG_SYS_FLASH_CFI 141 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 142 #endif 143 144 #if defined(CONFIG_SPIFLASH) 145 #define CONFIG_SYS_EXTRA_ENV_RELOC 146 #define CONFIG_ENV_IS_IN_SPI_FLASH 147 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 148 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 149 #define CONFIG_ENV_SECT_SIZE 0x10000 150 #elif defined(CONFIG_SDCARD) 151 #define CONFIG_SYS_EXTRA_ENV_RELOC 152 #define CONFIG_ENV_IS_IN_MMC 153 #define CONFIG_SYS_MMC_ENV_DEV 0 154 #define CONFIG_ENV_SIZE 0x2000 155 #define CONFIG_ENV_OFFSET (512 * 0x800) 156 #elif defined(CONFIG_NAND) 157 #define CONFIG_SYS_EXTRA_ENV_RELOC 158 #define CONFIG_ENV_IS_IN_NAND 159 #define CONFIG_ENV_SIZE 0x2000 160 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 161 #else 162 #define CONFIG_ENV_IS_IN_FLASH 163 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 164 #define CONFIG_ENV_SIZE 0x2000 165 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 166 #endif 167 168 #define CONFIG_SYS_CLK_FREQ 100000000 169 #define CONFIG_DDR_CLK_FREQ 66666666 170 171 /* 172 * These can be toggled for performance analysis, otherwise use default. 173 */ 174 #define CONFIG_SYS_CACHE_STASHING 175 #define CONFIG_BACKSIDE_L2_CACHE 176 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 177 #define CONFIG_BTB /* toggle branch predition */ 178 #define CONFIG_DDR_ECC 179 #ifdef CONFIG_DDR_ECC 180 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 181 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 182 #endif 183 184 #define CONFIG_ENABLE_36BIT_PHYS 185 186 #define CONFIG_ADDR_MAP 187 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 188 189 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 190 #define CONFIG_SYS_MEMTEST_END 0x00400000 191 #define CONFIG_SYS_ALT_MEMTEST 192 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 193 194 /* 195 * Config the L3 Cache as L3 SRAM 196 */ 197 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 198 #define CONFIG_SYS_L3_SIZE 256 << 10 199 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 200 #ifdef CONFIG_RAMBOOT_PBL 201 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 202 #endif 203 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 204 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 205 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 206 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 207 208 #define CONFIG_SYS_DCSRBAR 0xf0000000 209 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 210 211 /* 212 * DDR Setup 213 */ 214 #define CONFIG_VERY_BIG_RAM 215 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 216 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 217 218 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 219 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 220 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 221 222 #define CONFIG_DDR_SPD 223 #define CONFIG_SYS_FSL_DDR3 224 225 #define CONFIG_SYS_SPD_BUS_NUM 0 226 #define SPD_EEPROM_ADDRESS 0x51 227 228 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 229 230 /* 231 * IFC Definitions 232 */ 233 #define CONFIG_SYS_FLASH_BASE 0xe8000000 234 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 235 236 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 237 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 238 CSPR_PORT_SIZE_16 | \ 239 CSPR_MSEL_NOR | \ 240 CSPR_V) 241 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 242 243 /* 244 * TDM Definition 245 */ 246 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 247 248 /* NOR Flash Timing Params */ 249 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 250 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 251 FTIM0_NOR_TEADC(0x5) | \ 252 FTIM0_NOR_TEAHC(0x5)) 253 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 254 FTIM1_NOR_TRAD_NOR(0x1A) |\ 255 FTIM1_NOR_TSEQRAD_NOR(0x13)) 256 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 257 FTIM2_NOR_TCH(0x4) | \ 258 FTIM2_NOR_TWPH(0x0E) | \ 259 FTIM2_NOR_TWP(0x1c)) 260 #define CONFIG_SYS_NOR_FTIM3 0x0 261 262 #define CONFIG_SYS_FLASH_QUIET_TEST 263 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 264 265 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 266 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 267 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 268 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 269 270 #define CONFIG_SYS_FLASH_EMPTY_INFO 271 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 272 273 /* CPLD on IFC */ 274 #define CPLD_LBMAP_MASK 0x3F 275 #define CPLD_BANK_SEL_MASK 0x07 276 #define CPLD_BANK_OVERRIDE 0x40 277 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 278 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 279 #define CPLD_LBMAP_RESET 0xFF 280 #define CPLD_LBMAP_SHIFT 0x03 281 #ifdef CONFIG_T1042RDB_PI 282 #define CPLD_DIU_SEL_DFP 0x80 283 #endif 284 285 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 286 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 287 #define CONFIG_SYS_CSPR2_EXT (0xf) 288 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 289 | CSPR_PORT_SIZE_8 \ 290 | CSPR_MSEL_GPCM \ 291 | CSPR_V) 292 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 293 #define CONFIG_SYS_CSOR2 0x0 294 /* CPLD Timing parameters for IFC CS2 */ 295 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 296 FTIM0_GPCM_TEADC(0x0e) | \ 297 FTIM0_GPCM_TEAHC(0x0e)) 298 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 299 FTIM1_GPCM_TRAD(0x1f)) 300 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 301 FTIM2_GPCM_TCH(0x8) | \ 302 FTIM2_GPCM_TWP(0x1f)) 303 #define CONFIG_SYS_CS2_FTIM3 0x0 304 305 /* NAND Flash on IFC */ 306 #define CONFIG_NAND_FSL_IFC 307 #define CONFIG_SYS_NAND_BASE 0xff800000 308 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 309 310 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 311 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 312 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 313 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 314 | CSPR_V) 315 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 316 317 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 318 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 319 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 320 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 321 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 322 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 323 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 324 325 #define CONFIG_SYS_NAND_ONFI_DETECTION 326 327 /* ONFI NAND Flash mode0 Timing Params */ 328 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 329 FTIM0_NAND_TWP(0x18) | \ 330 FTIM0_NAND_TWCHT(0x07) | \ 331 FTIM0_NAND_TWH(0x0a)) 332 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 333 FTIM1_NAND_TWBE(0x39) | \ 334 FTIM1_NAND_TRR(0x0e) | \ 335 FTIM1_NAND_TRP(0x18)) 336 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 337 FTIM2_NAND_TREH(0x0a) | \ 338 FTIM2_NAND_TWHRE(0x1e)) 339 #define CONFIG_SYS_NAND_FTIM3 0x0 340 341 #define CONFIG_SYS_NAND_DDR_LAW 11 342 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 343 #define CONFIG_SYS_MAX_NAND_DEVICE 1 344 #define CONFIG_MTD_NAND_VERIFY_WRITE 345 #define CONFIG_CMD_NAND 346 347 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 348 349 #if defined(CONFIG_NAND) 350 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 351 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 352 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 353 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 354 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 355 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 356 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 357 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 358 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 359 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 360 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 361 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 362 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 363 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 364 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 365 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 366 #else 367 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 368 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 369 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 370 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 371 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 372 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 373 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 374 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 375 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 376 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 377 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 378 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 379 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 380 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 381 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 382 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 383 #endif 384 385 #ifdef CONFIG_SPL_BUILD 386 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 387 #else 388 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 389 #endif 390 391 #if defined(CONFIG_RAMBOOT_PBL) 392 #define CONFIG_SYS_RAMBOOT 393 #endif 394 395 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 396 #if defined(CONFIG_NAND) 397 #define CONFIG_A008044_WORKAROUND 398 #endif 399 #endif 400 401 #define CONFIG_BOARD_EARLY_INIT_R 402 #define CONFIG_MISC_INIT_R 403 404 #define CONFIG_HWCONFIG 405 406 /* define to use L1 as initial stack */ 407 #define CONFIG_L1_INIT_RAM 408 #define CONFIG_SYS_INIT_RAM_LOCK 409 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 410 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 411 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 412 /* The assembler doesn't like typecast */ 413 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 414 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 415 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 416 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 417 418 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 419 GENERATED_GBL_DATA_SIZE) 420 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 421 422 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 423 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 424 425 /* Serial Port - controlled on board with jumper J8 426 * open - index 2 427 * shorted - index 1 428 */ 429 #define CONFIG_CONS_INDEX 1 430 #define CONFIG_SYS_NS16550 431 #define CONFIG_SYS_NS16550_SERIAL 432 #define CONFIG_SYS_NS16550_REG_SIZE 1 433 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 434 435 #define CONFIG_SYS_BAUDRATE_TABLE \ 436 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 437 438 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 439 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 440 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 441 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 442 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 443 #ifndef CONFIG_SPL_BUILD 444 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 445 #endif 446 447 /* Use the HUSH parser */ 448 #define CONFIG_SYS_HUSH_PARSER 449 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 450 451 #ifdef CONFIG_T1042RDB_PI 452 /* Video */ 453 #define CONFIG_FSL_DIU_FB 454 455 #ifdef CONFIG_FSL_DIU_FB 456 #define CONFIG_FSL_DIU_CH7301 457 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 458 #define CONFIG_VIDEO 459 #define CONFIG_CMD_BMP 460 #define CONFIG_CFB_CONSOLE 461 #define CONFIG_CFB_CONSOLE_ANSI 462 #define CONFIG_VIDEO_SW_CURSOR 463 #define CONFIG_VGA_AS_SINGLE_DEVICE 464 #define CONFIG_VIDEO_LOGO 465 #define CONFIG_VIDEO_BMP_LOGO 466 #endif 467 #endif 468 469 /* pass open firmware flat tree */ 470 #define CONFIG_OF_LIBFDT 471 #define CONFIG_OF_BOARD_SETUP 472 #define CONFIG_OF_STDOUT_VIA_ALIAS 473 474 /* new uImage format support */ 475 #define CONFIG_FIT 476 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 477 478 /* I2C */ 479 #define CONFIG_SYS_I2C 480 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 481 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 482 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 483 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 484 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 485 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 486 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 487 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 488 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 489 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 490 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 491 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 492 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 493 494 /* I2C bus multiplexer */ 495 #define I2C_MUX_PCA_ADDR 0x70 496 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 497 #define I2C_MUX_CH_DEFAULT 0x8 498 #endif 499 500 #ifdef CONFIG_T1042RDB_PI 501 /* LDI/DVI Encoder for display */ 502 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 503 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 504 505 /* 506 * RTC configuration 507 */ 508 #define RTC 509 #define CONFIG_RTC_DS1337 1 510 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 511 512 /*DVI encoder*/ 513 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 514 #endif 515 516 /* 517 * eSPI - Enhanced SPI 518 */ 519 #define CONFIG_FSL_ESPI 520 #define CONFIG_SPI_FLASH 521 #define CONFIG_SPI_FLASH_STMICRO 522 #define CONFIG_SPI_FLASH_BAR 523 #define CONFIG_CMD_SF 524 #define CONFIG_SF_DEFAULT_SPEED 10000000 525 #define CONFIG_SF_DEFAULT_MODE 0 526 #define CONFIG_ENV_SPI_BUS 0 527 #define CONFIG_ENV_SPI_CS 0 528 #define CONFIG_ENV_SPI_MAX_HZ 10000000 529 #define CONFIG_ENV_SPI_MODE 0 530 531 /* 532 * General PCI 533 * Memory space is mapped 1-1, but I/O space must start from 0. 534 */ 535 536 #ifdef CONFIG_PCI 537 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 538 #ifdef CONFIG_PCIE1 539 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 540 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 541 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 542 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 543 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 544 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 545 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 546 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 547 #endif 548 549 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 550 #ifdef CONFIG_PCIE2 551 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 552 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 553 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 554 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 555 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 556 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 557 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 558 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 559 #endif 560 561 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 562 #ifdef CONFIG_PCIE3 563 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 564 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 565 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 566 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 567 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 568 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 569 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 570 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 571 #endif 572 573 /* controller 4, Base address 203000 */ 574 #ifdef CONFIG_PCIE4 575 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 576 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 577 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 578 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 579 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 580 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 581 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 582 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 583 #endif 584 585 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 586 #define CONFIG_E1000 587 588 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 589 #define CONFIG_DOS_PARTITION 590 #endif /* CONFIG_PCI */ 591 592 /* SATA */ 593 #define CONFIG_FSL_SATA_V2 594 #ifdef CONFIG_FSL_SATA_V2 595 #define CONFIG_LIBATA 596 #define CONFIG_FSL_SATA 597 598 #define CONFIG_SYS_SATA_MAX_DEVICE 1 599 #define CONFIG_SATA1 600 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 601 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 602 603 #define CONFIG_LBA48 604 #define CONFIG_CMD_SATA 605 #define CONFIG_DOS_PARTITION 606 #define CONFIG_CMD_EXT2 607 #endif 608 609 /* 610 * USB 611 */ 612 #define CONFIG_HAS_FSL_DR_USB 613 614 #ifdef CONFIG_HAS_FSL_DR_USB 615 #define CONFIG_USB_EHCI 616 617 #ifdef CONFIG_USB_EHCI 618 #define CONFIG_CMD_USB 619 #define CONFIG_USB_STORAGE 620 #define CONFIG_USB_EHCI_FSL 621 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 622 #define CONFIG_CMD_EXT2 623 #endif 624 #endif 625 626 #define CONFIG_MMC 627 628 #ifdef CONFIG_MMC 629 #define CONFIG_FSL_ESDHC 630 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 631 #define CONFIG_CMD_MMC 632 #define CONFIG_GENERIC_MMC 633 #define CONFIG_CMD_EXT2 634 #define CONFIG_CMD_FAT 635 #define CONFIG_DOS_PARTITION 636 #endif 637 638 /* Qman/Bman */ 639 #ifndef CONFIG_NOBQFMAN 640 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 641 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 642 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 643 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 644 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 645 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 646 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 647 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 648 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 649 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 650 CONFIG_SYS_BMAN_CENA_SIZE) 651 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 652 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 653 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 654 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 655 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 656 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 657 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 658 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 659 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 660 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 661 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 662 CONFIG_SYS_QMAN_CENA_SIZE) 663 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 664 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 665 666 #define CONFIG_SYS_DPAA_FMAN 667 #define CONFIG_SYS_DPAA_PME 668 669 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 670 #define CONFIG_QE 671 #define CONFIG_U_QE 672 #endif 673 674 /* Default address of microcode for the Linux Fman driver */ 675 #if defined(CONFIG_SPIFLASH) 676 /* 677 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 678 * env, so we got 0x110000. 679 */ 680 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 681 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 682 #elif defined(CONFIG_SDCARD) 683 /* 684 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 685 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 686 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 687 */ 688 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 689 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 690 #elif defined(CONFIG_NAND) 691 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 692 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 693 #else 694 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 695 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 696 #endif 697 698 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 699 #if defined(CONFIG_SPIFLASH) 700 #define CONFIG_SYS_QE_FW_ADDR 0x130000 701 #elif defined(CONFIG_SDCARD) 702 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 703 #elif defined(CONFIG_NAND) 704 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 705 #else 706 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 707 #endif 708 #endif 709 710 711 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 712 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 713 #endif /* CONFIG_NOBQFMAN */ 714 715 #ifdef CONFIG_SYS_DPAA_FMAN 716 #define CONFIG_FMAN_ENET 717 #define CONFIG_PHY_VITESSE 718 #define CONFIG_PHY_REALTEK 719 #endif 720 721 #ifdef CONFIG_FMAN_ENET 722 #if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB) 723 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 724 #endif 725 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 726 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 727 728 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 729 #ifdef CONFIG_T1040RDB 730 #define CONFIG_VSC9953 731 #define CONFIG_VSC9953_CMD 732 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 733 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 734 #endif 735 736 #define CONFIG_MII /* MII PHY management */ 737 #define CONFIG_ETHPRIME "FM1@DTSEC4" 738 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 739 #endif 740 741 /* 742 * Environment 743 */ 744 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 745 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 746 747 /* 748 * Command line configuration. 749 */ 750 #include <config_cmd_default.h> 751 752 #ifdef CONFIG_T1042RDB_PI 753 #define CONFIG_CMD_DATE 754 #endif 755 #define CONFIG_CMD_DHCP 756 #define CONFIG_CMD_ELF 757 #define CONFIG_CMD_ERRATA 758 #define CONFIG_CMD_GREPENV 759 #define CONFIG_CMD_IRQ 760 #define CONFIG_CMD_I2C 761 #define CONFIG_CMD_MII 762 #define CONFIG_CMD_PING 763 #define CONFIG_CMD_REGINFO 764 #define CONFIG_CMD_SETEXPR 765 766 #ifdef CONFIG_PCI 767 #define CONFIG_CMD_PCI 768 #define CONFIG_CMD_NET 769 #endif 770 771 /* Hash command with SHA acceleration supported in hardware */ 772 #ifdef CONFIG_FSL_CAAM 773 #define CONFIG_CMD_HASH 774 #define CONFIG_SHA_HW_ACCEL 775 #endif 776 777 /* 778 * Miscellaneous configurable options 779 */ 780 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 781 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 782 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 783 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 784 #ifdef CONFIG_CMD_KGDB 785 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 786 #else 787 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 788 #endif 789 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 790 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 791 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 792 793 /* 794 * For booting Linux, the board info and command line data 795 * have to be in the first 64 MB of memory, since this is 796 * the maximum mapped by the Linux kernel during initialization. 797 */ 798 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 799 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 800 801 #ifdef CONFIG_CMD_KGDB 802 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 803 #endif 804 805 /* 806 * Dynamic MTD Partition support with mtdparts 807 */ 808 #ifndef CONFIG_SYS_NO_FLASH 809 #define CONFIG_MTD_DEVICE 810 #define CONFIG_MTD_PARTITIONS 811 #define CONFIG_CMD_MTDPARTS 812 #define CONFIG_FLASH_CFI_MTD 813 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 814 "spi0=spife110000.0" 815 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 816 "128k(dtb),96m(fs),-(user);"\ 817 "fff800000.flash:2m(uboot),9m(kernel),"\ 818 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 819 "2m(uboot),9m(kernel),128k(dtb),-(user)" 820 #endif 821 822 /* 823 * Environment Configuration 824 */ 825 #define CONFIG_ROOTPATH "/opt/nfsroot" 826 #define CONFIG_BOOTFILE "uImage" 827 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 828 829 /* default location for tftp and bootm */ 830 #define CONFIG_LOADADDR 1000000 831 832 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ 833 834 #define CONFIG_BAUDRATE 115200 835 836 #define __USB_PHY_TYPE utmi 837 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 838 839 #ifdef CONFIG_T1040RDB 840 #define FDTFILE "t1040rdb/t1040rdb.dtb" 841 #elif defined(CONFIG_T1042RDB_PI) 842 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 843 #elif defined(CONFIG_T1042RDB) 844 #define FDTFILE "t1042rdb/t1042rdb.dtb" 845 #endif 846 847 #ifdef CONFIG_FSL_DIU_FB 848 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 849 #else 850 #define DIU_ENVIRONMENT 851 #endif 852 853 #define CONFIG_EXTRA_ENV_SETTINGS \ 854 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 855 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 856 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 857 "netdev=eth0\0" \ 858 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 859 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 860 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 861 "tftpflash=tftpboot $loadaddr $uboot && " \ 862 "protect off $ubootaddr +$filesize && " \ 863 "erase $ubootaddr +$filesize && " \ 864 "cp.b $loadaddr $ubootaddr $filesize && " \ 865 "protect on $ubootaddr +$filesize && " \ 866 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 867 "consoledev=ttyS0\0" \ 868 "ramdiskaddr=2000000\0" \ 869 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 870 "fdtaddr=c00000\0" \ 871 "fdtfile=" __stringify(FDTFILE) "\0" \ 872 "bdev=sda3\0" 873 874 #define CONFIG_LINUX \ 875 "setenv bootargs root=/dev/ram rw " \ 876 "console=$consoledev,$baudrate $othbootargs;" \ 877 "setenv ramdiskaddr 0x02000000;" \ 878 "setenv fdtaddr 0x00c00000;" \ 879 "setenv loadaddr 0x1000000;" \ 880 "bootm $loadaddr $ramdiskaddr $fdtaddr" 881 882 #define CONFIG_HDBOOT \ 883 "setenv bootargs root=/dev/$bdev rw " \ 884 "console=$consoledev,$baudrate $othbootargs;" \ 885 "tftp $loadaddr $bootfile;" \ 886 "tftp $fdtaddr $fdtfile;" \ 887 "bootm $loadaddr - $fdtaddr" 888 889 #define CONFIG_NFSBOOTCOMMAND \ 890 "setenv bootargs root=/dev/nfs rw " \ 891 "nfsroot=$serverip:$rootpath " \ 892 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 893 "console=$consoledev,$baudrate $othbootargs;" \ 894 "tftp $loadaddr $bootfile;" \ 895 "tftp $fdtaddr $fdtfile;" \ 896 "bootm $loadaddr - $fdtaddr" 897 898 #define CONFIG_RAMBOOTCOMMAND \ 899 "setenv bootargs root=/dev/ram rw " \ 900 "console=$consoledev,$baudrate $othbootargs;" \ 901 "tftp $ramdiskaddr $ramdiskfile;" \ 902 "tftp $loadaddr $bootfile;" \ 903 "tftp $fdtaddr $fdtfile;" \ 904 "bootm $loadaddr $ramdiskaddr $fdtaddr" 905 906 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 907 908 #ifdef CONFIG_SECURE_BOOT 909 #include <asm/fsl_secure_boot.h> 910 #define CONFIG_CMD_BLOB 911 #endif 912 913 #endif /* __CONFIG_H */ 914