1 /*
2  * Copyright (c) 2014 Google, Inc
3  *
4  * From Coreboot src/southbridge/intel/bd82x6x/pch.h
5  *
6  * Copyright (C) 2008-2009 coresystems GmbH
7  * Copyright (C) 2012 The Chromium OS Authors.  All rights reserved.
8  *
9  * SPDX-License-Identifier:	GPL-2.0
10  */
11 
12 #ifndef _ASM_ARCH_PCH_H
13 #define _ASM_ARCH_PCH_H
14 
15 #include <pci.h>
16 
17 /* PCH types */
18 #define PCH_TYPE_CPT	0x1c /* CougarPoint */
19 #define PCH_TYPE_PPT	0x1e /* IvyBridge */
20 
21 /* PCH stepping values for LPC device */
22 #define PCH_STEP_A0	0
23 #define PCH_STEP_A1	1
24 #define PCH_STEP_B0	2
25 #define PCH_STEP_B1	3
26 #define PCH_STEP_B2	4
27 #define PCH_STEP_B3	5
28 #define DEFAULT_GPIOBASE	0x0480
29 #define DEFAULT_PMBASE		0x0500
30 
31 #define SMBUS_IO_BASE		0x0400
32 
33 int pch_silicon_revision(void);
34 int pch_silicon_type(void);
35 int pch_silicon_supported(int type, int rev);
36 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
37 
38 #define MAINBOARD_POWER_OFF	0
39 #define MAINBOARD_POWER_ON	1
40 #define MAINBOARD_POWER_KEEP	2
41 
42 /* PCI Configuration Space (D30:F0): PCI2PCI */
43 #define PSTS	0x06
44 #define SMLT	0x1b
45 #define SECSTS	0x1e
46 #define INTR	0x3c
47 #define BCTRL	0x3e
48 #define   SBR	(1 << 6)
49 #define   SEE	(1 << 1)
50 #define   PERE	(1 << 0)
51 
52 #define PCH_EHCI1_DEV		PCI_BDF(0, 0x1d, 0)
53 #define PCH_EHCI2_DEV		PCI_BDF(0, 0x1a, 0)
54 #define PCH_XHCI_DEV		PCI_BDF(0, 0x14, 0)
55 #define PCH_ME_DEV		PCI_BDF(0, 0x16, 0)
56 #define PCH_PCIE_DEV_SLOT	28
57 
58 #define PCH_DEV			PCI_BDF(0, 0, 0)
59 #define PCH_VIDEO_DEV		PCI_BDF(0, 2, 0)
60 
61 /* PCI Configuration Space (D31:F0): LPC */
62 #define PCH_LPC_DEV		PCI_BDF(0, 0x1f, 0)
63 #define SERIRQ_CNTL		0x64
64 
65 #define GEN_PMCON_1		0xa0
66 #define GEN_PMCON_2		0xa2
67 #define GEN_PMCON_3		0xa4
68 #define ETR3			0xac
69 #define  ETR3_CWORWRE		(1 << 18)
70 #define  ETR3_CF9GR		(1 << 20)
71 
72 /* GEN_PMCON_3 bits */
73 #define RTC_BATTERY_DEAD	(1 << 2)
74 #define RTC_POWER_FAILED	(1 << 1)
75 #define SLEEP_AFTER_POWER_FAIL	(1 << 0)
76 
77 #define PMBASE			0x40
78 #define ACPI_CNTL		0x44
79 #define BIOS_CNTL		0xDC
80 #define GPIO_BASE		0x48 /* LPC GPIO Base Address Register */
81 #define GPIO_CNTL		0x4C /* LPC GPIO Control Register */
82 #define GPIO_ROUT		0xb8
83 
84 #define PIRQA_ROUT		0x60
85 #define PIRQB_ROUT		0x61
86 #define PIRQC_ROUT		0x62
87 #define PIRQD_ROUT		0x63
88 #define PIRQE_ROUT		0x68
89 #define PIRQF_ROUT		0x69
90 #define PIRQG_ROUT		0x6A
91 #define PIRQH_ROUT		0x6B
92 
93 #define GEN_PMCON_1		0xa0
94 #define GEN_PMCON_2		0xa2
95 #define GEN_PMCON_3		0xa4
96 #define ETR3			0xac
97 #define  ETR3_CWORWRE		(1 << 18)
98 #define  ETR3_CF9GR		(1 << 20)
99 
100 #define PMBASE			0x40
101 #define ACPI_CNTL		0x44
102 #define BIOS_CNTL		0xDC
103 #define GPIO_BASE		0x48 /* LPC GPIO Base Address Register */
104 #define GPIO_CNTL		0x4C /* LPC GPIO Control Register */
105 #define GPIO_ROUT		0xb8
106 
107 #define LPC_IO_DEC		0x80 /* IO Decode Ranges Register */
108 #define  COMB_DEC_RANGE		(1 << 4)  /* 0x2f8-0x2ff (COM2) */
109 #define  COMA_DEC_RANGE		(0 << 0)  /* 0x3f8-0x3ff (COM1) */
110 #define LPC_EN			0x82 /* LPC IF Enables Register */
111 #define  CNF2_LPC_EN		(1 << 13) /* 0x4e/0x4f */
112 #define  CNF1_LPC_EN		(1 << 12) /* 0x2e/0x2f */
113 #define  MC_LPC_EN		(1 << 11) /* 0x62/0x66 */
114 #define  KBC_LPC_EN		(1 << 10) /* 0x60/0x64 */
115 #define  GAMEH_LPC_EN		(1 << 9)  /* 0x208/0x20f */
116 #define  GAMEL_LPC_EN		(1 << 8)  /* 0x200/0x207 */
117 #define  FDD_LPC_EN		(1 << 3)  /* LPC_IO_DEC[12] */
118 #define  LPT_LPC_EN		(1 << 2)  /* LPC_IO_DEC[9:8] */
119 #define  COMB_LPC_EN		(1 << 1)  /* LPC_IO_DEC[6:4] */
120 #define  COMA_LPC_EN		(1 << 0)  /* LPC_IO_DEC[3:2] */
121 #define LPC_GEN1_DEC		0x84 /* LPC IF Generic Decode Range 1 */
122 #define LPC_GEN2_DEC		0x88 /* LPC IF Generic Decode Range 2 */
123 #define LPC_GEN3_DEC		0x8c /* LPC IF Generic Decode Range 3 */
124 #define LPC_GEN4_DEC		0x90 /* LPC IF Generic Decode Range 4 */
125 #define LPC_GENX_DEC(x)		(0x84 + 4 * (x))
126 #define  GEN_DEC_RANGE_256B	0xfc0000  /* 256 Bytes */
127 #define  GEN_DEC_RANGE_128B	0x7c0000  /* 128 Bytes */
128 #define  GEN_DEC_RANGE_64B	0x3c0000  /* 64 Bytes */
129 #define  GEN_DEC_RANGE_32B	0x1c0000  /* 32 Bytes */
130 #define  GEN_DEC_RANGE_16B	0x0c0000  /* 16 Bytes */
131 #define  GEN_DEC_RANGE_8B	0x040000  /* 8 Bytes */
132 #define  GEN_DEC_RANGE_4B	0x000000  /* 4 Bytes */
133 #define  GEN_DEC_RANGE_EN	(1 << 0)  /* Range Enable */
134 
135 /* PCI Configuration Space (D31:F1): IDE */
136 #define PCH_IDE_DEV		PCI_BDF(0, 0x1f, 1)
137 #define PCH_SATA_DEV		PCI_BDF(0, 0x1f, 2)
138 #define PCH_SATA2_DEV		PCI_BDF(0, 0x1f, 5)
139 
140 #define INTR_LN			0x3c
141 #define IDE_TIM_PRI		0x40	/* IDE timings, primary */
142 #define   IDE_DECODE_ENABLE	(1 << 15)
143 #define   IDE_SITRE		(1 << 14)
144 #define   IDE_ISP_5_CLOCKS	(0 << 12)
145 #define   IDE_ISP_4_CLOCKS	(1 << 12)
146 #define   IDE_ISP_3_CLOCKS	(2 << 12)
147 #define   IDE_RCT_4_CLOCKS	(0 <<  8)
148 #define   IDE_RCT_3_CLOCKS	(1 <<  8)
149 #define   IDE_RCT_2_CLOCKS	(2 <<  8)
150 #define   IDE_RCT_1_CLOCKS	(3 <<  8)
151 #define   IDE_DTE1		(1 <<  7)
152 #define   IDE_PPE1		(1 <<  6)
153 #define   IDE_IE1		(1 <<  5)
154 #define   IDE_TIME1		(1 <<  4)
155 #define   IDE_DTE0		(1 <<  3)
156 #define   IDE_PPE0		(1 <<  2)
157 #define   IDE_IE0		(1 <<  1)
158 #define   IDE_TIME0		(1 <<  0)
159 #define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
160 
161 #define IDE_SDMA_CNT		0x48	/* Synchronous DMA control */
162 #define   IDE_SSDE1		(1 <<  3)
163 #define   IDE_SSDE0		(1 <<  2)
164 #define   IDE_PSDE1		(1 <<  1)
165 #define   IDE_PSDE0		(1 <<  0)
166 
167 #define IDE_SDMA_TIM		0x4a
168 
169 #define IDE_CONFIG		0x54	/* IDE I/O Configuration Register */
170 #define   SIG_MODE_SEC_NORMAL	(0 << 18)
171 #define   SIG_MODE_SEC_TRISTATE	(1 << 18)
172 #define   SIG_MODE_SEC_DRIVELOW	(2 << 18)
173 #define   SIG_MODE_PRI_NORMAL	(0 << 16)
174 #define   SIG_MODE_PRI_TRISTATE	(1 << 16)
175 #define   SIG_MODE_PRI_DRIVELOW	(2 << 16)
176 #define   FAST_SCB1		(1 << 15)
177 #define   FAST_SCB0		(1 << 14)
178 #define   FAST_PCB1		(1 << 13)
179 #define   FAST_PCB0		(1 << 12)
180 #define   SCB1			(1 <<  3)
181 #define   SCB0			(1 <<  2)
182 #define   PCB1			(1 <<  1)
183 #define   PCB0			(1 <<  0)
184 
185 #define SATA_SIRI		0xa0 /* SATA Indexed Register Index */
186 #define SATA_SIRD		0xa4 /* SATA Indexed Register Data */
187 #define SATA_SP			0xd0 /* Scratchpad */
188 
189 /* SATA IOBP Registers */
190 #define SATA_IOBP_SP0G3IR	0xea000151
191 #define SATA_IOBP_SP1G3IR	0xea000051
192 
193 /* PCI Configuration Space (D31:F3): SMBus */
194 #define PCH_SMBUS_DEV		PCI_BDF(0, 0x1f, 3)
195 #define SMB_BASE		0x20
196 #define HOSTC			0x40
197 #define SMB_RCV_SLVA		0x09
198 
199 /* HOSTC bits */
200 #define I2C_EN			(1 << 2)
201 #define SMB_SMI_EN		(1 << 1)
202 #define HST_EN			(1 << 0)
203 
204 /* SMBus I/O bits. */
205 #define SMBHSTSTAT		0x0
206 #define SMBHSTCTL		0x2
207 #define SMBHSTCMD		0x3
208 #define SMBXMITADD		0x4
209 #define SMBHSTDAT0		0x5
210 #define SMBHSTDAT1		0x6
211 #define SMBBLKDAT		0x7
212 #define SMBTRNSADD		0x9
213 #define SMBSLVDATA		0xa
214 #define SMLINK_PIN_CTL		0xe
215 #define SMBUS_PIN_CTL		0xf
216 
217 #define SMBUS_TIMEOUT		(10 * 1000 * 100)
218 
219 
220 /* Root Complex Register Block */
221 #define DEFAULT_RCBA		0xfed1c000
222 #define RCB_REG(reg)		(DEFAULT_RCBA + (reg))
223 
224 #define PCH_RCBA_BASE		0xf0
225 
226 #define VCH		0x0000	/* 32bit */
227 #define VCAP1		0x0004	/* 32bit */
228 #define VCAP2		0x0008	/* 32bit */
229 #define PVC		0x000c	/* 16bit */
230 #define PVS		0x000e	/* 16bit */
231 
232 #define V0CAP		0x0010	/* 32bit */
233 #define V0CTL		0x0014	/* 32bit */
234 #define V0STS		0x001a	/* 16bit */
235 
236 #define V1CAP		0x001c	/* 32bit */
237 #define V1CTL		0x0020	/* 32bit */
238 #define V1STS		0x0026	/* 16bit */
239 
240 #define RCTCL		0x0100	/* 32bit */
241 #define ESD		0x0104	/* 32bit */
242 #define ULD		0x0110	/* 32bit */
243 #define ULBA		0x0118	/* 64bit */
244 
245 #define RP1D		0x0120	/* 32bit */
246 #define RP1BA		0x0128	/* 64bit */
247 #define RP2D		0x0130	/* 32bit */
248 #define RP2BA		0x0138	/* 64bit */
249 #define RP3D		0x0140	/* 32bit */
250 #define RP3BA		0x0148	/* 64bit */
251 #define RP4D		0x0150	/* 32bit */
252 #define RP4BA		0x0158	/* 64bit */
253 #define HDD		0x0160	/* 32bit */
254 #define HDBA		0x0168	/* 64bit */
255 #define RP5D		0x0170	/* 32bit */
256 #define RP5BA		0x0178	/* 64bit */
257 #define RP6D		0x0180	/* 32bit */
258 #define RP6BA		0x0188	/* 64bit */
259 
260 #define RPC		0x0400	/* 32bit */
261 #define RPFN		0x0404	/* 32bit */
262 
263 #define TRSR		0x1e00	/*  8bit */
264 #define TRCR		0x1e10	/* 64bit */
265 #define TWDR		0x1e18	/* 64bit */
266 
267 #define IOTR0		0x1e80	/* 64bit */
268 #define IOTR1		0x1e88	/* 64bit */
269 #define IOTR2		0x1e90	/* 64bit */
270 #define IOTR3		0x1e98	/* 64bit */
271 
272 #define TCTL		0x3000	/*  8bit */
273 
274 #define NOINT		0
275 #define INTA		1
276 #define INTB		2
277 #define INTC		3
278 #define INTD		4
279 
280 #define DIR_IDR		12	/* Interrupt D Pin Offset */
281 #define DIR_ICR		8	/* Interrupt C Pin Offset */
282 #define DIR_IBR		4	/* Interrupt B Pin Offset */
283 #define DIR_IAR		0	/* Interrupt A Pin Offset */
284 
285 #define PIRQA		0
286 #define PIRQB		1
287 #define PIRQC		2
288 #define PIRQD		3
289 #define PIRQE		4
290 #define PIRQF		5
291 #define PIRQG		6
292 #define PIRQH		7
293 
294 /* IO Buffer Programming */
295 #define IOBPIRI		0x2330
296 #define IOBPD		0x2334
297 #define IOBPS		0x2338
298 #define  IOBPS_RW_BX    ((1 << 9)|(1 << 10))
299 #define  IOBPS_WRITE_AX	((1 << 9)|(1 << 10))
300 #define  IOBPS_READ_AX	((1 << 8)|(1 << 9)|(1 << 10))
301 
302 #define D31IP		0x3100	/* 32bit */
303 #define D31IP_TTIP	24	/* Thermal Throttle Pin */
304 #define D31IP_SIP2	20	/* SATA Pin 2 */
305 #define D31IP_SMIP	12	/* SMBUS Pin */
306 #define D31IP_SIP	8	/* SATA Pin */
307 #define D30IP		0x3104	/* 32bit */
308 #define D30IP_PIP	0	/* PCI Bridge Pin */
309 #define D29IP		0x3108	/* 32bit */
310 #define D29IP_E1P	0	/* EHCI #1 Pin */
311 #define D28IP		0x310c	/* 32bit */
312 #define D28IP_P8IP	28	/* PCI Express Port 8 */
313 #define D28IP_P7IP	24	/* PCI Express Port 7 */
314 #define D28IP_P6IP	20	/* PCI Express Port 6 */
315 #define D28IP_P5IP	16	/* PCI Express Port 5 */
316 #define D28IP_P4IP	12	/* PCI Express Port 4 */
317 #define D28IP_P3IP	8	/* PCI Express Port 3 */
318 #define D28IP_P2IP	4	/* PCI Express Port 2 */
319 #define D28IP_P1IP	0	/* PCI Express Port 1 */
320 #define D27IP		0x3110	/* 32bit */
321 #define D27IP_ZIP	0	/* HD Audio Pin */
322 #define D26IP		0x3114	/* 32bit */
323 #define D26IP_E2P	0	/* EHCI #2 Pin */
324 #define D25IP		0x3118	/* 32bit */
325 #define D25IP_LIP	0	/* GbE LAN Pin */
326 #define D22IP		0x3124	/* 32bit */
327 #define D22IP_KTIP	12	/* KT Pin */
328 #define D22IP_IDERIP	8	/* IDE-R Pin */
329 #define D22IP_MEI2IP	4	/* MEI #2 Pin */
330 #define D22IP_MEI1IP	0	/* MEI #1 Pin */
331 #define D20IP		0x3128  /* 32bit */
332 #define D20IP_XHCIIP	0
333 #define D31IR		0x3140	/* 16bit */
334 #define D30IR		0x3142	/* 16bit */
335 #define D29IR		0x3144	/* 16bit */
336 #define D28IR		0x3146	/* 16bit */
337 #define D27IR		0x3148	/* 16bit */
338 #define D26IR		0x314c	/* 16bit */
339 #define D25IR		0x3150	/* 16bit */
340 #define D22IR		0x315c	/* 16bit */
341 #define D20IR		0x3160	/* 16bit */
342 #define OIC		0x31fe	/* 16bit */
343 
344 #define SPI_FREQ_SWSEQ	0x3893
345 #define SPI_DESC_COMP0	0x38b0
346 #define SPI_FREQ_WR_ERA	0x38b4
347 #define SOFT_RESET_CTRL 0x38f4
348 #define SOFT_RESET_DATA 0x38f8
349 
350 #define DIR_ROUTE(a, b, c, d) \
351 		(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
352 			((b) << DIR_IBR) | ((a) << DIR_IAR))
353 
354 #define RC		0x3400	/* 32bit */
355 #define HPTC		0x3404	/* 32bit */
356 #define GCS		0x3410	/* 32bit */
357 #define BUC		0x3414	/* 32bit */
358 #define PCH_DISABLE_GBE		(1 << 5)
359 #define FD		0x3418	/* 32bit */
360 #define DISPBDF		0x3424  /* 16bit */
361 #define FD2		0x3428	/* 32bit */
362 #define CG		0x341c	/* 32bit */
363 
364 /* Function Disable 1 RCBA 0x3418 */
365 #define PCH_DISABLE_ALWAYS	((1 << 0)|(1 << 26))
366 #define PCH_DISABLE_P2P		(1 << 1)
367 #define PCH_DISABLE_SATA1	(1 << 2)
368 #define PCH_DISABLE_SMBUS	(1 << 3)
369 #define PCH_DISABLE_HD_AUDIO	(1 << 4)
370 #define PCH_DISABLE_EHCI2	(1 << 13)
371 #define PCH_DISABLE_LPC		(1 << 14)
372 #define PCH_DISABLE_EHCI1	(1 << 15)
373 #define PCH_DISABLE_PCIE(x)	(1 << (16 + x))
374 #define PCH_DISABLE_THERMAL	(1 << 24)
375 #define PCH_DISABLE_SATA2	(1 << 25)
376 #define PCH_DISABLE_XHCI	(1 << 27)
377 
378 /* Function Disable 2 RCBA 0x3428 */
379 #define PCH_DISABLE_KT		(1 << 4)
380 #define PCH_DISABLE_IDER	(1 << 3)
381 #define PCH_DISABLE_MEI2	(1 << 2)
382 #define PCH_DISABLE_MEI1	(1 << 1)
383 #define PCH_ENABLE_DBDF		(1 << 0)
384 
385 /* ICH7 GPIOBASE */
386 #define GPIO_USE_SEL	0x00
387 #define GP_IO_SEL	0x04
388 #define GP_LVL		0x0c
389 #define GPO_BLINK	0x18
390 #define GPI_INV		0x2c
391 #define GPIO_USE_SEL2	0x30
392 #define GP_IO_SEL2	0x34
393 #define GP_LVL2		0x38
394 #define GPIO_USE_SEL3	0x40
395 #define GP_IO_SEL3	0x44
396 #define GP_LVL3		0x48
397 #define GP_RST_SEL1	0x60
398 #define GP_RST_SEL2	0x64
399 #define GP_RST_SEL3	0x68
400 
401 /* ICH7 PMBASE */
402 #define PM1_STS		0x00
403 #define   WAK_STS	(1 << 15)
404 #define   PCIEXPWAK_STS	(1 << 14)
405 #define   PRBTNOR_STS	(1 << 11)
406 #define   RTC_STS	(1 << 10)
407 #define   PWRBTN_STS	(1 << 8)
408 #define   GBL_STS	(1 << 5)
409 #define   BM_STS	(1 << 4)
410 #define   TMROF_STS	(1 << 0)
411 #define PM1_EN		0x02
412 #define   PCIEXPWAK_DIS	(1 << 14)
413 #define   RTC_EN	(1 << 10)
414 #define   PWRBTN_EN	(1 << 8)
415 #define   GBL_EN	(1 << 5)
416 #define   TMROF_EN	(1 << 0)
417 #define PM1_CNT		0x04
418 #define   SLP_EN	(1 << 13)
419 #define   SLP_TYP	(7 << 10)
420 #define    SLP_TYP_S0	0
421 #define    SLP_TYP_S1	1
422 #define    SLP_TYP_S3	5
423 #define    SLP_TYP_S4	6
424 #define    SLP_TYP_S5	7
425 #define   GBL_RLS	(1 << 2)
426 #define   BM_RLD	(1 << 1)
427 #define   SCI_EN	(1 << 0)
428 #define PM1_TMR		0x08
429 #define PROC_CNT	0x10
430 #define LV2		0x14
431 #define LV3		0x15
432 #define LV4		0x16
433 #define PM2_CNT		0x50 /* mobile only */
434 #define GPE0_STS	0x20
435 #define   PME_B0_STS	(1 << 13)
436 #define   PME_STS	(1 << 11)
437 #define   BATLOW_STS	(1 << 10)
438 #define   PCI_EXP_STS	(1 << 9)
439 #define   RI_STS	(1 << 8)
440 #define   SMB_WAK_STS	(1 << 7)
441 #define   TCOSCI_STS	(1 << 6)
442 #define   SWGPE_STS	(1 << 2)
443 #define   HOT_PLUG_STS	(1 << 1)
444 #define GPE0_EN		0x28
445 #define   PME_B0_EN	(1 << 13)
446 #define   PME_EN	(1 << 11)
447 #define   TCOSCI_EN	(1 << 6)
448 #define SMI_EN		0x30
449 #define   INTEL_USB2_EN	 (1 << 18) /* Intel-Specific USB2 SMI logic */
450 #define   LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */
451 #define   PERIODIC_EN	 (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
452 #define   TCO_EN	 (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
453 #define   MCSMI_EN	 (1 << 11) /* Trap microcontroller range access */
454 #define   BIOS_RLS	 (1 <<  7) /* asserts SCI on bit set */
455 #define   SWSMI_TMR_EN	 (1 <<  6) /* start software smi timer on bit set */
456 #define   APMC_EN	 (1 <<  5) /* Writes to APM_CNT cause SMI# */
457 #define   SLP_SMI_EN	 (1 <<  4) /* Write SLP_EN in PM1_CNT asserts SMI# */
458 #define   LEGACY_USB_EN  (1 <<  3) /* Legacy USB circuit SMI logic */
459 #define   BIOS_EN	 (1 <<  2) /* Assert SMI# on setting GBL_RLS bit */
460 #define   EOS		 (1 <<  1) /* End of SMI (deassert SMI#) */
461 #define   GBL_SMI_EN	 (1 <<  0) /* SMI# generation at all? */
462 #define SMI_STS		0x34
463 #define ALT_GP_SMI_EN	0x38
464 #define ALT_GP_SMI_STS	0x3a
465 #define GPE_CNTL	0x42
466 #define DEVACT_STS	0x44
467 #define SS_CNT		0x50
468 #define C3_RES		0x54
469 #define TCO1_STS	0x64
470 #define   DMISCI_STS	(1 << 9)
471 #define TCO2_STS	0x66
472 
473 int lpc_init(struct pci_controller *hose, pci_dev_t dev);
474 void lpc_enable(pci_dev_t dev);
475 
476 /**
477  * lpc_early_init() - set up LPC serial ports and other early things
478  *
479  * @blob:	Device tree blob
480  * @node:	Offset of LPC node
481  * @dev:	PCH PCI device containing the LPC
482  * @return 0 if OK, -ve on error
483  */
484 int lpc_early_init(const void *blob, int node, pci_dev_t dev);
485 
486 #endif
487