1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__ 9 10 #define CCM_CCOSR 0x020c4060 11 #define CCM_CCGR0 0x020C4068 12 #define CCM_CCGR1 0x020C406c 13 #define CCM_CCGR2 0x020C4070 14 #define CCM_CCGR3 0x020C4074 15 #define CCM_CCGR4 0x020C4078 16 #define CCM_CCGR5 0x020C407c 17 #define CCM_CCGR6 0x020C4080 18 19 #define PMU_MISC2 0x020C8170 20 21 #ifndef __ASSEMBLY__ 22 struct mxc_ccm_reg { 23 u32 ccr; /* 0x0000 */ 24 u32 ccdr; 25 u32 csr; 26 u32 ccsr; 27 u32 cacrr; /* 0x0010*/ 28 u32 cbcdr; 29 u32 cbcmr; 30 u32 cscmr1; 31 u32 cscmr2; /* 0x0020 */ 32 u32 cscdr1; 33 u32 cs1cdr; 34 u32 cs2cdr; 35 u32 cdcdr; /* 0x0030 */ 36 u32 chsccdr; 37 u32 cscdr2; 38 u32 cscdr3; 39 u32 cscdr4; /* 0x0040 */ 40 u32 resv0; 41 u32 cdhipr; 42 u32 cdcr; 43 u32 ctor; /* 0x0050 */ 44 u32 clpcr; 45 u32 cisr; 46 u32 cimr; 47 u32 ccosr; /* 0x0060 */ 48 u32 cgpr; 49 u32 CCGR0; 50 u32 CCGR1; 51 u32 CCGR2; /* 0x0070 */ 52 u32 CCGR3; 53 u32 CCGR4; 54 u32 CCGR5; 55 u32 CCGR6; /* 0x0080 */ 56 u32 CCGR7; 57 u32 cmeor; 58 u32 resv[0xfdd]; 59 u32 analog_pll_sys; /* 0x4000 */ 60 u32 analog_pll_sys_set; 61 u32 analog_pll_sys_clr; 62 u32 analog_pll_sys_tog; 63 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ 64 u32 analog_usb1_pll_480_ctrl_set; 65 u32 analog_usb1_pll_480_ctrl_clr; 66 u32 analog_usb1_pll_480_ctrl_tog; 67 u32 analog_reserved0[4]; 68 u32 analog_pll_528; /* 0x4030 */ 69 u32 analog_pll_528_set; 70 u32 analog_pll_528_clr; 71 u32 analog_pll_528_tog; 72 u32 analog_pll_528_ss; /* 0x4040 */ 73 u32 analog_reserved1[3]; 74 u32 analog_pll_528_num; /* 0x4050 */ 75 u32 analog_reserved2[3]; 76 u32 analog_pll_528_denom; /* 0x4060 */ 77 u32 analog_reserved3[3]; 78 u32 analog_pll_audio; /* 0x4070 */ 79 u32 analog_pll_audio_set; 80 u32 analog_pll_audio_clr; 81 u32 analog_pll_audio_tog; 82 u32 analog_pll_audio_num; /* 0x4080*/ 83 u32 analog_reserved4[3]; 84 u32 analog_pll_audio_denom; /* 0x4090 */ 85 u32 analog_reserved5[3]; 86 u32 analog_pll_video; /* 0x40a0 */ 87 u32 analog_pll_video_set; 88 u32 analog_pll_video_clr; 89 u32 analog_pll_video_tog; 90 u32 analog_pll_video_num; /* 0x40b0 */ 91 u32 analog_reserved6[3]; 92 u32 analog_pll_video_denom; /* 0x40c0 */ 93 u32 analog_reserved7[7]; 94 u32 analog_pll_enet; /* 0x40e0 */ 95 u32 analog_pll_enet_set; 96 u32 analog_pll_enet_clr; 97 u32 analog_pll_enet_tog; 98 u32 analog_pfd_480; /* 0x40f0 */ 99 u32 analog_pfd_480_set; 100 u32 analog_pfd_480_clr; 101 u32 analog_pfd_480_tog; 102 u32 analog_pfd_528; /* 0x4100 */ 103 u32 analog_pfd_528_set; 104 u32 analog_pfd_528_clr; 105 u32 analog_pfd_528_tog; 106 }; 107 #endif 108 109 /* Define the bits in register CCR */ 110 #define MXC_CCM_CCR_RBC_EN (1 << 27) 111 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) 112 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 113 /* CCR_WB does not exist on i.MX6SX/UL */ 114 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 115 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) 116 #define MXC_CCM_CCR_COSC_EN (1 << 12) 117 #ifdef CONFIG_MX6SX 118 #define MXC_CCM_CCR_OSCNT_MASK 0x7F 119 #else 120 #define MXC_CCM_CCR_OSCNT_MASK 0xFF 121 #endif 122 #define MXC_CCM_CCR_OSCNT_OFFSET 0 123 124 /* Define the bits in register CCDR */ 125 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) 126 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) 127 /* Exists on i.MX6QP */ 128 #define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18) 129 130 /* Define the bits in register CSR */ 131 #define MXC_CCM_CSR_COSC_READY (1 << 5) 132 #define MXC_CCM_CSR_REF_EN_B (1 << 0) 133 134 /* Define the bits in register CCSR */ 135 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15) 136 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14) 137 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13) 138 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12) 139 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11) 140 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10) 141 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9) 142 #define MXC_CCM_CCSR_STEP_SEL (1 << 8) 143 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) 144 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) 145 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) 146 147 /* Define the bits in register CACRR */ 148 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 149 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 150 151 /* Define the bits in register CBCDR */ 152 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) 153 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 154 #define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26) 155 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) 156 /* MMDC_CH0 not exists on i.MX6SX */ 157 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) 158 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 159 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) 160 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 161 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) 162 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 163 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) 164 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 165 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) 166 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6) 167 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) 168 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 169 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) 170 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 171 172 /* Define the bits in register CBCMR */ 173 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) 174 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 175 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) 176 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 177 /* LCDIF on i.MX6SX/UL */ 178 #define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23) 179 #define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23 180 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) 181 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 182 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) 183 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 184 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20) 185 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) 186 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 187 #ifndef CONFIG_MX6SX 188 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) 189 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 190 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) 191 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 192 #endif 193 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) 194 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 195 #ifndef CONFIG_MX6SX 196 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) 197 #endif 198 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) 199 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) 200 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 201 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) 202 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 203 /* Exists on i.MX6QP */ 204 #define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1) 205 206 /* Define the bits in register CSCMR1 */ 207 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) 208 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 209 /* QSPI1 exist on i.MX6SX/UL */ 210 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26) 211 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26 212 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) 213 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 214 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) 215 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 216 /* LCFIF2_PODF on i.MX6SX */ 217 #define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20) 218 #define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20 219 /* ACLK_EMI on i.MX6DQ/SDL/DQP */ 220 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) 221 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 222 /* CSCMR1_GPMI/BCH exist on i.MX6UL */ 223 #define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19) 224 #define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18) 225 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) 226 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) 227 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) 228 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) 229 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) 230 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 231 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) 232 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 233 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) 234 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 235 /* QSPI1 exist on i.MX6SX/UL */ 236 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7) 237 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 238 /* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */ 239 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) 240 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 241 242 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F 243 244 /* Define the bits in register CSCMR2 */ 245 #ifdef CONFIG_MX6SX 246 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21) 247 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21 248 #endif 249 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) 250 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 251 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) 252 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) 253 /* CSCMR1_CAN_CLK exists on i.MX6SX/QP */ 254 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8) 255 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 256 257 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2) 258 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2 259 260 /* Define the bits in register CSCDR1 */ 261 #ifndef CONFIG_MX6SX 262 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) 263 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 264 #endif 265 /* CSCDR1_GPMI/BCH exist on i.MX6UL */ 266 #define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22) 267 #define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22 268 #define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19) 269 #define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19 270 271 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) 272 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 273 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) 274 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 275 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) 276 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 277 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) 278 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 279 #ifndef CONFIG_MX6SX 280 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 281 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) 282 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 283 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) 284 #endif 285 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F 286 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 287 /* UART_CLK_SEL exists on i.MX6SL/SX/QP */ 288 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) 289 290 /* Define the bits in register CS1CDR */ 291 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) 292 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 293 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22) 294 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22 295 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) 296 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 297 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) 298 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 299 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) 300 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 301 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F 302 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 303 304 /* Define the bits in register CS2CDR */ 305 /* QSPI2 on i.MX6SX */ 306 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21) 307 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21 308 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) 309 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18) 310 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18 311 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18) 312 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15) 313 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15 314 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) 315 316 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) 317 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 318 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) 319 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) 320 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 321 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) 322 323 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15) 324 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15 325 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15) 326 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16) 327 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16 328 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) 329 330 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ 331 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ 332 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \ 333 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ) 334 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ 335 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ 336 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \ 337 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ) 338 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ 339 ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ 340 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \ 341 MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)) 342 343 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) 344 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 345 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) 346 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 347 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) 348 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 349 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F 350 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 351 352 /* Define the bits in register CDCDR */ 353 #ifndef CONFIG_MX6SX 354 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) 355 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 356 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) 357 #endif 358 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) 359 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 360 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22) 361 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22 362 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) 363 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 364 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) 365 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 366 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) 367 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 368 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) 369 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 370 371 /* Define the bits in register CHSCCDR */ 372 #ifdef CONFIG_MX6SX 373 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15) 374 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15 375 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12) 376 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12 377 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9) 378 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9 379 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6) 380 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6 381 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3) 382 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3 383 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7) 384 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0 385 #else 386 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 387 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 388 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) 389 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 390 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) 391 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 392 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 393 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 394 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) 395 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 396 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) 397 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 398 #endif 399 400 #define CHSCCDR_CLK_SEL_LDB_DI0 3 401 #define CHSCCDR_PODF_DIVIDE_BY_3 2 402 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 403 404 /* Define the bits in register CSCDR2 */ 405 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) 406 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 407 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */ 408 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) 409 /* LCDIF1 on i.MX6SX/UL */ 410 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15) 411 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15 412 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12) 413 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12 414 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9) 415 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9 416 /* LCDIF2 on i.MX6SX */ 417 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6) 418 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6 419 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK (0x7 << 3) 420 #define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET 3 421 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0) 422 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0 423 424 /* All IPU2_DI1 are LCDIF1 on MX6SX */ 425 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) 426 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 427 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) 428 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 429 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) 430 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 431 /* All IPU2_DI0 are LCDIF2 on MX6SX */ 432 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) 433 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 434 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) 435 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 436 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 437 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 438 439 /* Define the bits in register CSCDR3 */ 440 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) 441 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 442 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) 443 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 444 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) 445 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 446 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) 447 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 448 449 /* Define the bits in register CDHIPR */ 450 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) 451 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) 452 #ifndef CONFIG_MX6SX 453 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) 454 #endif 455 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) 456 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) 457 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) 458 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 459 460 /* Define the bits in register CLPCR */ 461 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) 462 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) 463 #ifndef CONFIG_MX6SX 464 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) 465 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) 466 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) 467 #endif 468 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) 469 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) 470 #ifndef CONFIG_MX6SX 471 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) 472 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) 473 #endif 474 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16) 475 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) 476 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) 477 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 478 #define MXC_CCM_CLPCR_VSTBY (1 << 8) 479 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) 480 #define MXC_CCM_CLPCR_SBYOS (1 << 6) 481 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) 482 #ifndef CONFIG_MX6SX 483 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) 484 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 485 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) 486 #endif 487 #define MXC_CCM_CLPCR_LPM_MASK 0x3 488 #define MXC_CCM_CLPCR_LPM_OFFSET 0 489 490 /* Define the bits in register CISR */ 491 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) 492 #ifndef CONFIG_MX6SX 493 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) 494 #endif 495 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) 496 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) 497 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) 498 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) 499 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) 500 #define MXC_CCM_CISR_COSC_READY (1 << 6) 501 #define MXC_CCM_CISR_LRF_PLL 1 502 503 /* Define the bits in register CIMR */ 504 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) 505 #ifndef CONFIG_MX6SX 506 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) 507 #endif 508 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) 509 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) 510 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) 511 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) 512 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) 513 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) 514 #define MXC_CCM_CIMR_MASK_LRF_PLL 1 515 516 /* Define the bits in register CCOSR */ 517 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) 518 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) 519 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 520 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 521 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) 522 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8) 523 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) 524 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) 525 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 526 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF 527 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 528 529 /* Define the bits in registers CGPR */ 530 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16) 531 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) 532 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) 533 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 534 535 /* Define the bits in registers CCGRx */ 536 #define MXC_CCM_CCGR_CG_MASK 3 537 538 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 539 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) 540 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 541 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET) 542 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4 543 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET) 544 #define MXC_CCM_CCGR0_ASRC_OFFSET 6 545 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET) 546 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8 547 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET) 548 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10 549 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET) 550 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12 551 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET) 552 #define MXC_CCM_CCGR0_CAN1_OFFSET 14 553 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET) 554 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16 555 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET) 556 #define MXC_CCM_CCGR0_CAN2_OFFSET 18 557 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET) 558 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20 559 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET) 560 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22 561 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET) 562 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24 563 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET) 564 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26 565 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET) 566 #ifdef CONFIG_MX6SX 567 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30 568 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET) 569 #else 570 #define MXC_CCM_CCGR0_DTCP_OFFSET 28 571 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET) 572 #endif 573 574 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 575 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET) 576 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2 577 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET) 578 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4 579 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET) 580 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6 581 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET) 582 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 583 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET) 584 /* CCGR1_ENET does not exist on i.MX6SX/UL */ 585 #define MXC_CCM_CCGR1_ENET_OFFSET 10 586 #define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET) 587 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 588 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET) 589 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 590 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET) 591 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16 592 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET) 593 #ifdef CONFIG_MX6SX 594 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18 595 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET) 596 #endif 597 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 598 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET) 599 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 600 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) 601 #ifndef CONFIG_MX6SX 602 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24 603 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET) 604 #endif 605 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26 606 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET) 607 #ifdef CONFIG_MX6SX 608 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28 609 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET) 610 #define MXC_CCM_CCGR1_CANFD_OFFSET 30 611 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET) 612 #endif 613 614 #ifndef CONFIG_MX6SX 615 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 616 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) 617 #else 618 #define MXC_CCM_CCGR2_CSI_OFFSET 2 619 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET) 620 #endif 621 #ifndef CONFIG_MX6SX 622 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 623 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) 624 #endif 625 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 626 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) 627 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 628 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) 629 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 630 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) 631 #define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8 632 #define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET) 633 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 634 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) 635 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 636 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET) 637 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16 638 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET) 639 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18 640 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET) 641 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20 642 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) 643 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 644 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) 645 /* i.MX6SX/UL LCD and PXP */ 646 #define MXC_CCM_CCGR2_LCD_OFFSET 28 647 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET) 648 #define MXC_CCM_CCGR2_PXP_OFFSET 30 649 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET) 650 651 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 652 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) 653 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 654 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) 655 656 /* Exist on i.MX6SX */ 657 #define MXC_CCM_CCGR3_M4_OFFSET 2 658 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET) 659 #define MXC_CCM_CCGR3_ENET_OFFSET 4 660 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET) 661 #define MXC_CCM_CCGR3_QSPI_OFFSET 14 662 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET) 663 664 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 665 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) 666 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 667 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) 668 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 669 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) 670 671 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 672 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET) 673 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 674 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET) 675 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10 676 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) 677 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 678 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) 679 680 /* QSPI1 exists on i.MX6SX/UL */ 681 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14 682 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET) 683 684 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 685 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET) 686 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 687 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) 688 689 /* A7_CLKDIV/WDOG1 on i.MX6UL */ 690 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16 691 #define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET) 692 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18 693 #define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET) 694 695 #define MXC_CCM_CCGR3_MLB_OFFSET 18 696 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET) 697 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 698 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) 699 #ifndef CONFIG_MX6SX 700 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 701 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) 702 #endif 703 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 704 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) 705 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 706 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) 707 708 #define MXC_CCM_CCGR3_DISP_AXI_OFFSET 6 709 #define MXC_CCM_CCGR3_DISP_AXI_MASK (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET) 710 #define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET 8 711 #define MXC_CCM_CCGR3_LCDIF2_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET) 712 #define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET 10 713 #define MXC_CCM_CCGR3_LCDIF1_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET) 714 /* AXI on i.MX6UL */ 715 #define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28 716 #define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET) 717 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28 718 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) 719 720 /* GPIO4 on i.MX6UL */ 721 #define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30 722 #define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET) 723 724 #ifndef CONFIG_MX6SX 725 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 726 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) 727 #endif 728 729 #define MXC_CCM_CCGR4_PCIE_OFFSET 0 730 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) 731 /* QSPI2 on i.MX6SX */ 732 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10 733 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET) 734 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 735 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) 736 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 737 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET) 738 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14 739 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET) 740 #define MXC_CCM_CCGR4_PWM1_OFFSET 16 741 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET) 742 #define MXC_CCM_CCGR4_PWM2_OFFSET 18 743 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET) 744 #define MXC_CCM_CCGR4_PWM3_OFFSET 20 745 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET) 746 #define MXC_CCM_CCGR4_PWM4_OFFSET 22 747 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET) 748 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24 749 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET) 750 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26 751 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET) 752 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28 753 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET) 754 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30 755 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET) 756 757 #define MXC_CCM_CCGR5_ROM_OFFSET 0 758 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET) 759 #ifndef CONFIG_MX6SX 760 #define MXC_CCM_CCGR5_SATA_OFFSET 4 761 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET) 762 #endif 763 #define MXC_CCM_CCGR5_SDMA_OFFSET 6 764 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET) 765 #define MXC_CCM_CCGR5_SPBA_OFFSET 12 766 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET) 767 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14 768 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET) 769 #define MXC_CCM_CCGR5_SSI1_OFFSET 18 770 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET) 771 #define MXC_CCM_CCGR5_SSI2_OFFSET 20 772 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET) 773 #define MXC_CCM_CCGR5_SSI3_OFFSET 22 774 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET) 775 #define MXC_CCM_CCGR5_UART_OFFSET 24 776 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET) 777 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 778 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET) 779 #ifdef CONFIG_MX6SX 780 #define MXC_CCM_CCGR5_SAI1_OFFSET 20 781 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET) 782 #define MXC_CCM_CCGR5_SAI2_OFFSET 30 783 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET) 784 #endif 785 786 /* PRG_CLK0 exists on i.MX6QP */ 787 #define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24) 788 789 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0 790 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) 791 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2 792 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) 793 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4 794 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) 795 /* GPMI/BCH on i.MX6UL */ 796 #define MXC_CCM_CCGR6_BCH_OFFSET 6 797 #define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET) 798 #define MXC_CCM_CCGR6_GPMI_OFFSET 8 799 #define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET) 800 801 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6 802 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) 803 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8 804 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) 805 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 806 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) 807 /* The following *CCGR6* exist only i.MX6SX */ 808 #define MXC_CCM_CCGR6_PWM8_OFFSET 16 809 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET) 810 #define MXC_CCM_CCGR6_VADC_OFFSET 20 811 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET) 812 #define MXC_CCM_CCGR6_GIS_OFFSET 22 813 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET) 814 #define MXC_CCM_CCGR6_I2C4_OFFSET 24 815 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET) 816 #define MXC_CCM_CCGR6_PWM5_OFFSET 26 817 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET) 818 #define MXC_CCM_CCGR6_PWM6_OFFSET 28 819 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET) 820 #define MXC_CCM_CCGR6_PWM7_OFFSET 30 821 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET) 822 /* The two does not exist on i.MX6SX */ 823 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 824 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) 825 826 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000 827 #define BP_ANADIG_PLL_SYS_RSVD0 20 828 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 829 #define BF_ANADIG_PLL_SYS_RSVD0(v) \ 830 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) 831 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 832 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 833 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 834 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 835 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 836 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 837 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ 838 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) 839 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 840 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 841 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 842 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 843 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 844 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 845 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 846 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 847 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 848 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 849 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 850 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0 851 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F 852 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ 853 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) 854 855 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 856 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 857 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 858 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ 859 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) 860 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 861 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 862 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 863 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ 864 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) 865 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 866 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 867 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 868 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 869 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 870 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 871 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 872 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 873 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 874 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 875 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 876 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 877 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 878 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 879 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C 880 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ 881 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) 882 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 883 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 884 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ 885 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) 886 887 #define BM_ANADIG_PLL_528_LOCK 0x80000000 888 #define BP_ANADIG_PLL_528_RSVD1 19 889 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 890 #define BF_ANADIG_PLL_528_RSVD1(v) \ 891 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) 892 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 893 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 894 #define BM_ANADIG_PLL_528_BYPASS 0x00010000 895 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 896 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 897 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ 898 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) 899 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 900 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 901 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 902 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 903 #define BM_ANADIG_PLL_528_ENABLE 0x00002000 904 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 905 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 906 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 907 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200 908 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 909 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080 910 #define BP_ANADIG_PLL_528_RSVD0 1 911 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E 912 #define BF_ANADIG_PLL_528_RSVD0(v) \ 913 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) 914 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 915 916 #define BP_ANADIG_PLL_528_SS_STOP 16 917 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 918 #define BF_ANADIG_PLL_528_SS_STOP(v) \ 919 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) 920 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 921 #define BP_ANADIG_PLL_528_SS_STEP 0 922 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF 923 #define BF_ANADIG_PLL_528_SS_STEP(v) \ 924 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) 925 926 #define BP_ANADIG_PLL_528_NUM_RSVD0 30 927 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 928 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ 929 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) 930 #define BP_ANADIG_PLL_528_NUM_A 0 931 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF 932 #define BF_ANADIG_PLL_528_NUM_A(v) \ 933 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) 934 935 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30 936 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 937 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ 938 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) 939 #define BP_ANADIG_PLL_528_DENOM_B 0 940 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF 941 #define BF_ANADIG_PLL_528_DENOM_B(v) \ 942 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) 943 944 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 945 #define BP_ANADIG_PLL_AUDIO_RSVD0 22 946 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 947 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ 948 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) 949 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 950 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 951 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 952 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ 953 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) 954 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 955 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 956 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 957 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 958 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 959 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ 960 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) 961 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 962 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 963 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 964 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 965 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 966 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 967 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 968 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 969 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 970 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 971 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 972 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 973 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F 974 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ 975 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) 976 977 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 978 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 979 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ 980 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) 981 #define BP_ANADIG_PLL_AUDIO_NUM_A 0 982 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF 983 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ 984 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) 985 986 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 987 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 988 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ 989 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) 990 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0 991 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF 992 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ 993 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) 994 995 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 996 #define BP_ANADIG_PLL_VIDEO_RSVD0 22 997 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 998 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ 999 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) 1000 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 1001 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19 1002 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000 1003 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \ 1004 (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) 1005 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 1006 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 1007 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 1008 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 1009 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 1010 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ 1011 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) 1012 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 1013 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 1014 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 1015 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 1016 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 1017 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 1018 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 1019 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 1020 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 1021 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 1022 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 1023 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 1024 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F 1025 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ 1026 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) 1027 1028 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 1029 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 1030 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ 1031 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) 1032 #define BP_ANADIG_PLL_VIDEO_NUM_A 0 1033 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF 1034 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ 1035 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) 1036 1037 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 1038 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 1039 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ 1040 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) 1041 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0 1042 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF 1043 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ 1044 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) 1045 1046 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000 1047 #define BP_ANADIG_PLL_ENET_RSVD1 21 1048 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 1049 #define BF_ANADIG_PLL_ENET_RSVD1(v) \ 1050 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) 1051 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000 1052 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 1053 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 1054 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 1055 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 1056 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 1057 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 1058 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 1059 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ 1060 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) 1061 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 1062 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 1063 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 1064 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 1065 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 1066 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 1067 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 1068 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 1069 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 1070 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 1071 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 1072 #define BP_ANADIG_PLL_ENET_RSVD0 2 1073 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C 1074 #define BF_ANADIG_PLL_ENET_RSVD0(v) \ 1075 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) 1076 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0 1077 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 1078 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ 1079 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) 1080 1081 /* ENET2 for i.MX6SX/UL */ 1082 #define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000 1083 #define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C 1084 #define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \ 1085 (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT) 1086 1087 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 1088 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 1089 #define BP_ANADIG_PFD_480_PFD3_FRAC 24 1090 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 1091 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ 1092 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) 1093 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 1094 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 1095 #define BP_ANADIG_PFD_480_PFD2_FRAC 16 1096 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 1097 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ 1098 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) 1099 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 1100 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 1101 #define BP_ANADIG_PFD_480_PFD1_FRAC 8 1102 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 1103 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ 1104 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) 1105 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 1106 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 1107 #define BP_ANADIG_PFD_480_PFD0_FRAC 0 1108 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F 1109 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ 1110 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) 1111 1112 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 1113 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 1114 #define BP_ANADIG_PFD_528_PFD3_FRAC 24 1115 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 1116 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ 1117 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) 1118 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 1119 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 1120 #define BP_ANADIG_PFD_528_PFD2_FRAC 16 1121 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 1122 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ 1123 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) 1124 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 1125 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 1126 #define BP_ANADIG_PFD_528_PFD1_FRAC 8 1127 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 1128 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ 1129 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) 1130 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 1131 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 1132 #define BP_ANADIG_PFD_528_PFD0_FRAC 0 1133 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F 1134 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ 1135 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) 1136 1137 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 1138 1139 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ 1140