1 /* 2 * Configuration settings for the QUIPOS Cairo board. 3 * 4 * Copyright (C) DENX GmbH 5 * 6 * Author : 7 * Albert ARIBAUD <albert.aribaud@3adev.fr> 8 * 9 * Derived from EVM code by 10 * Manikandan Pillai <mani.pillai@ti.com> 11 * Itself derived from Beagle Board and 3430 SDP code by 12 * Richard Woodruff <r-woodruff2@ti.com> 13 * Syed Mohammed Khasim <khasim@ti.com> 14 * 15 * Also derived from include/configs/omap3_beagle.h 16 * 17 * SPDX-License-Identifier: GPL-2.0+ 18 */ 19 20 #ifndef __OMAP3_CAIRO_CONFIG_H 21 #define __OMAP3_CAIRO_CONFIG_H 22 23 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 24 25 /* 26 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 27 * 64 bytes before this address should be set aside for u-boot.img's 28 * header. That is 0x800FFFC0--0x80100000 should not be used for any 29 * other needs. We use this rather than the inherited defines from 30 * ti_armv7_common.h for backwards compatibility. 31 */ 32 #define CONFIG_SYS_TEXT_BASE 0x80100000 33 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 34 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 35 #define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ 36 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 37 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 38 39 #define CONFIG_NAND 40 41 #include <configs/ti_omap3_common.h> 42 43 /* 44 * Display CPU and Board information 45 */ 46 #define CONFIG_DISPLAY_CPUINFO 1 47 #define CONFIG_DISPLAY_BOARDINFO 1 48 49 #define CONFIG_MISC_INIT_R 50 51 #define CONFIG_REVISION_TAG 1 52 #define CONFIG_ENV_OVERWRITE 53 54 /* Enable Multi Bus support for I2C */ 55 #define CONFIG_I2C_MULTI_BUS 1 56 57 /* Probe all devices */ 58 #define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} } 59 60 #define CONFIG_NAND 61 62 /* commands to include */ 63 #define CONFIG_CMD_NAND_LOCK_UNLOCK 64 65 /* 66 * TWL4030 67 */ 68 #define CONFIG_TWL4030_LED 1 69 70 /* 71 * Board NAND Info. 72 */ 73 #define CONFIG_NAND_OMAP_GPMC 74 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 75 /* devices */ 76 /* override default CONFIG_BOOTDELAY */ 77 #undef CONFIG_BOOTDELAY 78 #define CONFIG_BOOTDELAY 0 79 80 #define CONFIG_EXTRA_ENV_SETTINGS \ 81 "machid=ffffffff\0" \ 82 "fdt_high=0x87000000\0" \ 83 "baudrate=115200\0" \ 84 "fec_addr=00:50:C2:7E:90:F0\0" \ 85 "netmask=255.255.255.0\0" \ 86 "ipaddr=192.168.2.9\0" \ 87 "gateway=192.168.2.1\0" \ 88 "serverip=192.168.2.10\0" \ 89 "nfshost=192.168.2.10\0" \ 90 "stdin=serial\0" \ 91 "stdout=serial\0" \ 92 "stderr=serial\0" \ 93 "bootargs_mmc_ramdisk=mem=128M " \ 94 "console=ttyO1,115200n8 " \ 95 "root=/dev/ram0 rw " \ 96 "initrd=0x81600000,16M " \ 97 "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \ 98 "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \ 99 "mmcboot=mmc init; " \ 100 "fatload mmc 0 0x80000000 uImage; " \ 101 "fatload mmc 0 0x81600000 ramdisk.gz; " \ 102 "setenv bootargs ${bootargs_mmc_ramdisk}; " \ 103 "bootm 0x80000000\0" \ 104 "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \ 105 "root=/dev/nfs " \ 106 "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \ 107 "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \ 108 "omap_vout.vid1_static_vrfb_alloc=y\0" \ 109 "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \ 110 "bootm 0x80000000\0" \ 111 "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \ 112 "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \ 113 "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \ 114 "omapfb.rotate_type=1\0" \ 115 "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \ 116 "bootargs ${bootargs_nand}; bootm 0x80000000\0" \ 117 "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 118 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ 119 "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \ 120 "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 121 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \ 122 "mw 60 09 00 1; i2c mw 60 06 10 1\0" \ 123 "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 124 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ 125 "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \ 126 "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 127 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ 128 "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \ 129 "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \ 130 "nand erase 0 20000; " \ 131 "fatload mmc 0 0x81600000 MLO; " \ 132 "nandecc hw; " \ 133 "nand write.i 0x81600000 0 20000;\0" \ 134 "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \ 135 "nand erase 80000 40000; " \ 136 "fatload mmc 0 0x81600000 u-boot.bin; " \ 137 "nandecc sw; " \ 138 "nand write.i 0x81600000 80000 40000;\0" \ 139 "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \ 140 "nand erase 280000 300000; " \ 141 "fatload mmc 0 0x81600000 uImage; " \ 142 "nandecc sw; " \ 143 "nand write.i 0x81600000 280000 300000;\0" \ 144 "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \ 145 "nandecc sw; " \ 146 "nand write.jffs2 0x680000 0xFF ${filesize}; " \ 147 "nand erase 680000 ${filesize}; " \ 148 "nand write.jffs2 81600000 680000 ${filesize};\0" \ 149 "flash_scrub=nand scrub; " \ 150 "run flash_xloader; " \ 151 "run flash_uboot; " \ 152 "run flash_kernel; " \ 153 "run flash_rootfs;\0" \ 154 "flash_all=run ledred; " \ 155 "nand erase.chip; " \ 156 "run ledorange; " \ 157 "run flash_xloader; " \ 158 "run flash_uboot; " \ 159 "run flash_kernel; " \ 160 "run flash_rootfs; " \ 161 "run ledgreen; " \ 162 "run boot_nand; \0" \ 163 164 #define CONFIG_BOOTCOMMAND \ 165 "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \ 166 "else run boot_nand; fi" 167 168 /* 169 * OMAP3 has 12 GP timers, they can be driven by the system clock 170 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 171 * This rate is divided by a local divisor. 172 */ 173 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 174 175 /*----------------------------------------------------------------------- 176 * FLASH and environment organization 177 */ 178 179 /* **** PISMO SUPPORT *** */ 180 #if defined(CONFIG_CMD_NAND) 181 #define CONFIG_SYS_FLASH_BASE NAND_BASE 182 #endif 183 184 /* Monitor at start of flash */ 185 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 186 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 187 188 #define CONFIG_ENV_IS_IN_NAND 1 189 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 190 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 191 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 192 193 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 194 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 195 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 196 197 #define CONFIG_OMAP3_SPI 198 199 #define CONFIG_SYS_CACHELINE_SIZE 64 200 201 /* Defines for SPL */ 202 #define CONFIG_SPL_OMAP3_ID_NAND 203 204 /* NAND boot config */ 205 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 206 #define CONFIG_SYS_NAND_PAGE_COUNT 64 207 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 208 #define CONFIG_SYS_NAND_OOBSIZE 64 209 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 210 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 211 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 212 10, 11, 12, 13} 213 #define CONFIG_SYS_NAND_ECCSIZE 512 214 #define CONFIG_SYS_NAND_ECCBYTES 3 215 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 216 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 217 /* NAND: SPL falcon mode configs */ 218 #ifdef CONFIG_SPL_OS_BOOT 219 #define CONFIG_CMD_SPL_NAND_OFS 0x240000 220 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 221 #define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 222 #endif 223 224 /* env defaults */ 225 #define CONFIG_BOOTFILE "uImage" 226 227 /* Override OMAP3 common serial console configuration from UART3 228 * to UART2. 229 * 230 * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3) 231 * are needed and peripheral clocks for UART2 must be enabled in 232 * function per_clocks_enable(). 233 */ 234 #undef CONFIG_CONS_INDEX 235 #define CONFIG_CONS_INDEX 2 236 #ifdef CONFIG_SPL_BUILD 237 #undef CONFIG_SYS_NS16550_COM3 238 #define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2 239 #undef CONFIG_SERIAL3 240 #define CONFIG_SERIAL2 241 #endif 242 243 /* Provide MACH_TYPE for compatibility with non-DT kernels */ 244 #define MACH_TYPE_OMAP3_CAIRO 3063 245 #define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CAIRO 246 247 /*----------------------------------------------------------------------- 248 * FLASH and environment organization 249 */ 250 251 /* **** PISMO SUPPORT *** */ 252 253 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 254 /* on one chip */ 255 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 256 257 /*----------------------------------------------------------------------- 258 * CFI FLASH driver setup 259 */ 260 /* timeout values are in ticks */ 261 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 262 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 263 264 /* Flash banks JFFS2 should use */ 265 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 266 CONFIG_SYS_MAX_NAND_DEVICE) 267 #define CONFIG_SYS_JFFS2_MEM_NAND 268 /* use flash_info[2] */ 269 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 270 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 271 272 #endif /* __OMAP3_CAIRO_CONFIG_H */ 273