1 /* 2 * Copyright (C) 2014 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS2_COMMON_H 8 #define __LS2_COMMON_H 9 10 11 #define CONFIG_REMAKE_ELF 12 #define CONFIG_FSL_LAYERSCAPE 13 #define CONFIG_FSL_LSCH3 14 #define CONFIG_MP 15 #define CONFIG_GICV3 16 #define CONFIG_FSL_TZPC_BP147 17 18 /* Errata fixes */ 19 #define CONFIG_ARM_ERRATA_828024 20 #define CONFIG_ARM_ERRATA_826974 21 22 #include <asm/arch/ls2080a_stream_id.h> 23 #include <asm/arch/config.h> 24 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) 25 #define CONFIG_SYS_HAS_SERDES 26 #endif 27 28 /* Link Definitions */ 29 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 30 31 /* We need architecture specific misc initializations */ 32 #define CONFIG_ARCH_MISC_INIT 33 34 /* Link Definitions */ 35 #ifdef CONFIG_SPL 36 #define CONFIG_SYS_TEXT_BASE 0x80400000 37 #else 38 #define CONFIG_SYS_TEXT_BASE 0x30100000 39 #endif 40 41 #ifdef CONFIG_EMU 42 #define CONFIG_SYS_NO_FLASH 43 #endif 44 45 #define CONFIG_SUPPORT_RAW_INITRD 46 47 #define CONFIG_SKIP_LOWLEVEL_INIT 48 #define CONFIG_BOARD_EARLY_INIT_F 1 49 50 /* Flat Device Tree Definitions */ 51 #define CONFIG_OF_LIBFDT 52 #define CONFIG_OF_BOARD_SETUP 53 #define CONFIG_OF_STDOUT_VIA_ALIAS 54 55 /* new uImage format support */ 56 #define CONFIG_FIT 57 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 58 59 #ifndef CONFIG_SPL 60 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 61 #endif 62 #ifndef CONFIG_SYS_FSL_DDR4 63 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 64 #define CONFIG_SYS_DDR_RAW_TIMING 65 #endif 66 67 #define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ 68 69 #define CONFIG_VERY_BIG_RAM 70 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 71 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 72 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 73 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL 74 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 75 76 /* 77 * SMP Definitinos 78 */ 79 #define CPU_RELEASE_ADDR secondary_boot_func 80 81 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS 82 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR 83 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL 84 /* 85 * DDR controller use 0 as the base address for binding. 86 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. 87 */ 88 #define CONFIG_SYS_DP_DDR_BASE_PHY 0 89 #define CONFIG_DP_DDR_CTRL 2 90 #define CONFIG_DP_DDR_NUM_CTRLS 1 91 #endif 92 93 /* Generic Timer Definitions */ 94 /* 95 * This is not an accurate number. It is used in start.S. The frequency 96 * will be udpated later when get_bus_freq(0) is available. 97 */ 98 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 99 100 /* Size of malloc() pool */ 101 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 102 103 /* I2C */ 104 #define CONFIG_CMD_I2C 105 #define CONFIG_SYS_I2C 106 #define CONFIG_SYS_I2C_MXC 107 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 108 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 109 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 110 #define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ 111 112 /* Serial Port */ 113 #define CONFIG_CONS_INDEX 1 114 #define CONFIG_SYS_NS16550_SERIAL 115 #define CONFIG_SYS_NS16550_REG_SIZE 1 116 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 117 118 #define CONFIG_BAUDRATE 115200 119 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 120 121 /* IFC */ 122 #define CONFIG_FSL_IFC 123 124 /* 125 * During booting, IFC is mapped at the region of 0x30000000. 126 * But this region is limited to 256MB. To accommodate NOR, promjet 127 * and FPGA. This region is divided as below: 128 * 0x30000000 - 0x37ffffff : 128MB : NOR flash 129 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet 130 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc 131 * 132 * To accommodate bigger NOR flash and other devices, we will map IFC 133 * chip selects to as below: 134 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole 135 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) 136 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB 137 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) 138 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) 139 * 140 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. 141 * CONFIG_SYS_FLASH_BASE has the final address (core view) 142 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) 143 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address 144 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting 145 */ 146 147 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL 148 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 149 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 150 151 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 152 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 153 154 #ifndef CONFIG_SYS_NO_FLASH 155 #define CONFIG_FLASH_CFI_DRIVER 156 #define CONFIG_SYS_FLASH_CFI 157 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 158 #define CONFIG_SYS_FLASH_QUIET_TEST 159 #endif 160 161 #ifndef __ASSEMBLY__ 162 unsigned long long get_qixis_addr(void); 163 #endif 164 #define QIXIS_BASE get_qixis_addr() 165 #define QIXIS_BASE_PHYS 0x20000000 166 #define QIXIS_BASE_PHYS_EARLY 0xC000000 167 #define QIXIS_STAT_PRES1 0xb 168 #define QIXIS_SDID_MASK 0x07 169 #define QIXIS_ESDHC_NO_ADAPTER 0x7 170 171 #define CONFIG_SYS_NAND_BASE 0x530000000ULL 172 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 173 174 /* Debug Server firmware */ 175 #define CONFIG_FSL_DEBUG_SERVER 176 /* 2 sec timeout */ 177 #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000) 178 179 /* MC firmware */ 180 #define CONFIG_FSL_MC_ENET 181 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ 182 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 183 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 184 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 185 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 186 #ifdef CONFIG_LS2085A 187 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 188 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 189 #endif 190 191 /* 192 * Carve out a DDR region which will not be used by u-boot/Linux 193 * 194 * It will be used by MC and Debug Server. The MC region must be 195 * 512MB aligned, so the min size to hide is 512MB. 196 */ 197 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) 198 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024) 199 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) 200 #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) 201 #endif 202 203 /* PCIe */ 204 #define CONFIG_PCIE1 /* PCIE controler 1 */ 205 #define CONFIG_PCIE2 /* PCIE controler 2 */ 206 #define CONFIG_PCIE3 /* PCIE controler 3 */ 207 #define CONFIG_PCIE4 /* PCIE controler 4 */ 208 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 209 #ifdef CONFIG_LS2080A 210 #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" 211 #endif 212 213 #ifdef CONFIG_LS2085A 214 #define FSL_PCIE_COMPAT "fsl,ls2085a-pcie" 215 #endif 216 217 #define CONFIG_SYS_PCI_64BIT 218 219 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 220 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 221 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 222 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 223 224 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 225 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 226 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 227 228 #define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 229 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 230 #define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ 231 232 /* Command line configuration */ 233 #define CONFIG_CMD_CACHE 234 #define CONFIG_CMD_DHCP 235 #define CONFIG_CMD_ENV 236 #define CONFIG_CMD_GREPENV 237 #define CONFIG_CMD_MII 238 #define CONFIG_CMD_PING 239 240 /* Miscellaneous configurable options */ 241 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 242 #define CONFIG_ARCH_EARLY_INIT_R 243 244 /* Physical Memory Map */ 245 /* fixme: these need to be checked against the board */ 246 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 247 248 #define CONFIG_NR_DRAM_BANKS 3 249 250 #define CONFIG_HWCONFIG 251 #define HWCONFIG_BUFFER_SIZE 128 252 253 #define CONFIG_DISPLAY_CPUINFO 254 255 /* Allow to overwrite serial and ethaddr */ 256 #define CONFIG_ENV_OVERWRITE 257 258 /* Initial environment variables */ 259 #define CONFIG_EXTRA_ENV_SETTINGS \ 260 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 261 "loadaddr=0x80100000\0" \ 262 "kernel_addr=0x100000\0" \ 263 "ramdisk_addr=0x800000\0" \ 264 "ramdisk_size=0x2000000\0" \ 265 "fdt_high=0xa0000000\0" \ 266 "initrd_high=0xffffffffffffffff\0" \ 267 "kernel_start=0x581200000\0" \ 268 "kernel_load=0xa0000000\0" \ 269 "kernel_size=0x2800000\0" \ 270 "console=ttyAMA0,38400n8\0" 271 272 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 273 "earlycon=uart8250,mmio,0x21c0500" \ 274 "ramdisk_size=0x2000000 default_hugepagesz=2m" \ 275 " hugepagesz=2m hugepages=16" 276 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ 277 "$kernel_size && bootm $kernel_load" 278 #define CONFIG_BOOTDELAY 10 279 280 /* Monitor Command Prompt */ 281 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 282 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 283 sizeof(CONFIG_SYS_PROMPT) + 16) 284 #define CONFIG_SYS_HUSH_PARSER 285 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 286 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 287 #define CONFIG_SYS_LONGHELP 288 #define CONFIG_CMDLINE_EDITING 1 289 #define CONFIG_AUTO_COMPLETE 290 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 291 292 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 293 294 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 295 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 296 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 297 #define CONFIG_SPL_ENV_SUPPORT 298 #define CONFIG_SPL_FRAMEWORK 299 #define CONFIG_SPL_I2C_SUPPORT 300 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" 301 #define CONFIG_SPL_LIBCOMMON_SUPPORT 302 #define CONFIG_SPL_LIBGENERIC_SUPPORT 303 #define CONFIG_SPL_MAX_SIZE 0x16000 304 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 305 #define CONFIG_SPL_NAND_SUPPORT 306 #define CONFIG_SPL_SERIAL_SUPPORT 307 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) 308 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 309 #define CONFIG_SPL_TEXT_BASE 0x1800a000 310 311 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 312 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST 313 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 314 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 315 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 316 317 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 318 319 320 #endif /* __LS2_COMMON_H */ 321