1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; 26 27 apbmisc: misc@100000 { 28 compatible = "nvidia,tegra194-misc"; 29 reg = <0x0 0x00100000 0x0 0xf000>, 30 <0x0 0x0010f000 0x0 0x1000>; 31 }; 32 33 gpio: gpio@2200000 { 34 compatible = "nvidia,tegra194-gpio"; 35 reg-names = "security", "gpio"; 36 reg = <0x0 0x2200000 0x0 0x10000>, 37 <0x0 0x2210000 0x0 0x10000>; 38 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 86 #interrupt-cells = <2>; 87 interrupt-controller; 88 #gpio-cells = <2>; 89 gpio-controller; 90 gpio-ranges = <&pinmux 0 0 169>; 91 }; 92 93 cbb-noc@2300000 { 94 compatible = "nvidia,tegra194-cbb-noc"; 95 reg = <0x0 0x02300000 0x0 0x1000>; 96 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 98 nvidia,axi2apb = <&axi2apb>; 99 nvidia,apbmisc = <&apbmisc>; 100 status = "okay"; 101 }; 102 103 axi2apb: axi2apb@2390000 { 104 compatible = "nvidia,tegra194-axi2apb"; 105 reg = <0x0 0x2390000 0x0 0x1000>, 106 <0x0 0x23a0000 0x0 0x1000>, 107 <0x0 0x23b0000 0x0 0x1000>, 108 <0x0 0x23c0000 0x0 0x1000>, 109 <0x0 0x23d0000 0x0 0x1000>, 110 <0x0 0x23e0000 0x0 0x1000>; 111 status = "okay"; 112 }; 113 114 pinmux: pinmux@2430000 { 115 compatible = "nvidia,tegra194-pinmux"; 116 reg = <0x0 0x2430000 0x0 0x17000>; 117 status = "okay"; 118 119 pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir { 120 clkreq { 121 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 122 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 123 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 124 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 125 nvidia,tristate = <TEGRA_PIN_DISABLE>; 126 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 127 }; 128 }; 129 130 pex_rst_c5_out_state: pinmux-pex-rst-c5-out { 131 pex_rst { 132 nvidia,pins = "pex_l5_rst_n_pgg1"; 133 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 134 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 135 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 136 nvidia,tristate = <TEGRA_PIN_DISABLE>; 137 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 138 }; 139 }; 140 }; 141 142 ethernet@2490000 { 143 compatible = "nvidia,tegra194-eqos", 144 "nvidia,tegra186-eqos", 145 "snps,dwc-qos-ethernet-4.10"; 146 reg = <0x0 0x02490000 0x0 0x10000>; 147 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 149 <&bpmp TEGRA194_CLK_EQOS_AXI>, 150 <&bpmp TEGRA194_CLK_EQOS_RX>, 151 <&bpmp TEGRA194_CLK_EQOS_TX>, 152 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 153 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 154 resets = <&bpmp TEGRA194_RESET_EQOS>; 155 reset-names = "eqos"; 156 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 157 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 158 interconnect-names = "dma-mem", "write"; 159 iommus = <&smmu TEGRA194_SID_EQOS>; 160 status = "disabled"; 161 162 snps,write-requests = <1>; 163 snps,read-requests = <3>; 164 snps,burst-map = <0x7>; 165 snps,txpbl = <16>; 166 snps,rxpbl = <8>; 167 }; 168 169 gpcdma: dma-controller@2600000 { 170 compatible = "nvidia,tegra194-gpcdma", 171 "nvidia,tegra186-gpcdma"; 172 reg = <0x0 0x2600000 0x0 0x210000>; 173 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 174 reset-names = "gpcdma"; 175 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 207 #dma-cells = <1>; 208 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 209 dma-coherent; 210 dma-channel-mask = <0xfffffffe>; 211 status = "okay"; 212 }; 213 214 aconnect@2900000 { 215 compatible = "nvidia,tegra194-aconnect", 216 "nvidia,tegra210-aconnect"; 217 clocks = <&bpmp TEGRA194_CLK_APE>, 218 <&bpmp TEGRA194_CLK_APB2APE>; 219 clock-names = "ape", "apb2ape"; 220 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 221 status = "disabled"; 222 223 #address-cells = <2>; 224 #size-cells = <2>; 225 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 226 227 tegra_ahub: ahub@2900800 { 228 compatible = "nvidia,tegra194-ahub", 229 "nvidia,tegra186-ahub"; 230 reg = <0x0 0x02900800 0x0 0x800>; 231 clocks = <&bpmp TEGRA194_CLK_AHUB>; 232 clock-names = "ahub"; 233 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 234 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 235 status = "disabled"; 236 237 #address-cells = <2>; 238 #size-cells = <2>; 239 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 240 241 tegra_i2s1: i2s@2901000 { 242 compatible = "nvidia,tegra194-i2s", 243 "nvidia,tegra210-i2s"; 244 reg = <0x0 0x2901000 0x0 0x100>; 245 clocks = <&bpmp TEGRA194_CLK_I2S1>, 246 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 247 clock-names = "i2s", "sync_input"; 248 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 249 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 250 assigned-clock-rates = <1536000>; 251 sound-name-prefix = "I2S1"; 252 status = "disabled"; 253 }; 254 255 tegra_i2s2: i2s@2901100 { 256 compatible = "nvidia,tegra194-i2s", 257 "nvidia,tegra210-i2s"; 258 reg = <0x0 0x2901100 0x0 0x100>; 259 clocks = <&bpmp TEGRA194_CLK_I2S2>, 260 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 261 clock-names = "i2s", "sync_input"; 262 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 263 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 264 assigned-clock-rates = <1536000>; 265 sound-name-prefix = "I2S2"; 266 status = "disabled"; 267 }; 268 269 tegra_i2s3: i2s@2901200 { 270 compatible = "nvidia,tegra194-i2s", 271 "nvidia,tegra210-i2s"; 272 reg = <0x0 0x2901200 0x0 0x100>; 273 clocks = <&bpmp TEGRA194_CLK_I2S3>, 274 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 275 clock-names = "i2s", "sync_input"; 276 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 277 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 278 assigned-clock-rates = <1536000>; 279 sound-name-prefix = "I2S3"; 280 status = "disabled"; 281 }; 282 283 tegra_i2s4: i2s@2901300 { 284 compatible = "nvidia,tegra194-i2s", 285 "nvidia,tegra210-i2s"; 286 reg = <0x0 0x2901300 0x0 0x100>; 287 clocks = <&bpmp TEGRA194_CLK_I2S4>, 288 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 289 clock-names = "i2s", "sync_input"; 290 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 291 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 292 assigned-clock-rates = <1536000>; 293 sound-name-prefix = "I2S4"; 294 status = "disabled"; 295 }; 296 297 tegra_i2s5: i2s@2901400 { 298 compatible = "nvidia,tegra194-i2s", 299 "nvidia,tegra210-i2s"; 300 reg = <0x0 0x2901400 0x0 0x100>; 301 clocks = <&bpmp TEGRA194_CLK_I2S5>, 302 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 303 clock-names = "i2s", "sync_input"; 304 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 305 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 306 assigned-clock-rates = <1536000>; 307 sound-name-prefix = "I2S5"; 308 status = "disabled"; 309 }; 310 311 tegra_i2s6: i2s@2901500 { 312 compatible = "nvidia,tegra194-i2s", 313 "nvidia,tegra210-i2s"; 314 reg = <0x0 0x2901500 0x0 0x100>; 315 clocks = <&bpmp TEGRA194_CLK_I2S6>, 316 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 317 clock-names = "i2s", "sync_input"; 318 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 319 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 320 assigned-clock-rates = <1536000>; 321 sound-name-prefix = "I2S6"; 322 status = "disabled"; 323 }; 324 325 tegra_sfc1: sfc@2902000 { 326 compatible = "nvidia,tegra194-sfc", 327 "nvidia,tegra210-sfc"; 328 reg = <0x0 0x2902000 0x0 0x200>; 329 sound-name-prefix = "SFC1"; 330 status = "disabled"; 331 }; 332 333 tegra_sfc2: sfc@2902200 { 334 compatible = "nvidia,tegra194-sfc", 335 "nvidia,tegra210-sfc"; 336 reg = <0x0 0x2902200 0x0 0x200>; 337 sound-name-prefix = "SFC2"; 338 status = "disabled"; 339 }; 340 341 tegra_sfc3: sfc@2902400 { 342 compatible = "nvidia,tegra194-sfc", 343 "nvidia,tegra210-sfc"; 344 reg = <0x0 0x2902400 0x0 0x200>; 345 sound-name-prefix = "SFC3"; 346 status = "disabled"; 347 }; 348 349 tegra_sfc4: sfc@2902600 { 350 compatible = "nvidia,tegra194-sfc", 351 "nvidia,tegra210-sfc"; 352 reg = <0x0 0x2902600 0x0 0x200>; 353 sound-name-prefix = "SFC4"; 354 status = "disabled"; 355 }; 356 357 tegra_amx1: amx@2903000 { 358 compatible = "nvidia,tegra194-amx"; 359 reg = <0x0 0x2903000 0x0 0x100>; 360 sound-name-prefix = "AMX1"; 361 status = "disabled"; 362 }; 363 364 tegra_amx2: amx@2903100 { 365 compatible = "nvidia,tegra194-amx"; 366 reg = <0x0 0x2903100 0x0 0x100>; 367 sound-name-prefix = "AMX2"; 368 status = "disabled"; 369 }; 370 371 tegra_amx3: amx@2903200 { 372 compatible = "nvidia,tegra194-amx"; 373 reg = <0x0 0x2903200 0x0 0x100>; 374 sound-name-prefix = "AMX3"; 375 status = "disabled"; 376 }; 377 378 tegra_amx4: amx@2903300 { 379 compatible = "nvidia,tegra194-amx"; 380 reg = <0x0 0x2903300 0x0 0x100>; 381 sound-name-prefix = "AMX4"; 382 status = "disabled"; 383 }; 384 385 tegra_adx1: adx@2903800 { 386 compatible = "nvidia,tegra194-adx", 387 "nvidia,tegra210-adx"; 388 reg = <0x0 0x2903800 0x0 0x100>; 389 sound-name-prefix = "ADX1"; 390 status = "disabled"; 391 }; 392 393 tegra_adx2: adx@2903900 { 394 compatible = "nvidia,tegra194-adx", 395 "nvidia,tegra210-adx"; 396 reg = <0x0 0x2903900 0x0 0x100>; 397 sound-name-prefix = "ADX2"; 398 status = "disabled"; 399 }; 400 401 tegra_adx3: adx@2903a00 { 402 compatible = "nvidia,tegra194-adx", 403 "nvidia,tegra210-adx"; 404 reg = <0x0 0x2903a00 0x0 0x100>; 405 sound-name-prefix = "ADX3"; 406 status = "disabled"; 407 }; 408 409 tegra_adx4: adx@2903b00 { 410 compatible = "nvidia,tegra194-adx", 411 "nvidia,tegra210-adx"; 412 reg = <0x0 0x2903b00 0x0 0x100>; 413 sound-name-prefix = "ADX4"; 414 status = "disabled"; 415 }; 416 417 tegra_dmic1: dmic@2904000 { 418 compatible = "nvidia,tegra194-dmic", 419 "nvidia,tegra210-dmic"; 420 reg = <0x0 0x2904000 0x0 0x100>; 421 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 422 clock-names = "dmic"; 423 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 424 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 425 assigned-clock-rates = <3072000>; 426 sound-name-prefix = "DMIC1"; 427 status = "disabled"; 428 }; 429 430 tegra_dmic2: dmic@2904100 { 431 compatible = "nvidia,tegra194-dmic", 432 "nvidia,tegra210-dmic"; 433 reg = <0x0 0x2904100 0x0 0x100>; 434 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 435 clock-names = "dmic"; 436 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 437 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 438 assigned-clock-rates = <3072000>; 439 sound-name-prefix = "DMIC2"; 440 status = "disabled"; 441 }; 442 443 tegra_dmic3: dmic@2904200 { 444 compatible = "nvidia,tegra194-dmic", 445 "nvidia,tegra210-dmic"; 446 reg = <0x0 0x2904200 0x0 0x100>; 447 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 448 clock-names = "dmic"; 449 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 450 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 451 assigned-clock-rates = <3072000>; 452 sound-name-prefix = "DMIC3"; 453 status = "disabled"; 454 }; 455 456 tegra_dmic4: dmic@2904300 { 457 compatible = "nvidia,tegra194-dmic", 458 "nvidia,tegra210-dmic"; 459 reg = <0x0 0x2904300 0x0 0x100>; 460 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 461 clock-names = "dmic"; 462 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 463 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 464 assigned-clock-rates = <3072000>; 465 sound-name-prefix = "DMIC4"; 466 status = "disabled"; 467 }; 468 469 tegra_dspk1: dspk@2905000 { 470 compatible = "nvidia,tegra194-dspk", 471 "nvidia,tegra186-dspk"; 472 reg = <0x0 0x2905000 0x0 0x100>; 473 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 474 clock-names = "dspk"; 475 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 476 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 477 assigned-clock-rates = <12288000>; 478 sound-name-prefix = "DSPK1"; 479 status = "disabled"; 480 }; 481 482 tegra_dspk2: dspk@2905100 { 483 compatible = "nvidia,tegra194-dspk", 484 "nvidia,tegra186-dspk"; 485 reg = <0x0 0x2905100 0x0 0x100>; 486 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 487 clock-names = "dspk"; 488 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 489 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 490 assigned-clock-rates = <12288000>; 491 sound-name-prefix = "DSPK2"; 492 status = "disabled"; 493 }; 494 495 tegra_ope1: processing-engine@2908000 { 496 compatible = "nvidia,tegra194-ope", 497 "nvidia,tegra210-ope"; 498 reg = <0x0 0x2908000 0x0 0x100>; 499 sound-name-prefix = "OPE1"; 500 status = "disabled"; 501 502 #address-cells = <2>; 503 #size-cells = <2>; 504 ranges; 505 506 equalizer@2908100 { 507 compatible = "nvidia,tegra194-peq", 508 "nvidia,tegra210-peq"; 509 reg = <0x0 0x2908100 0x0 0x100>; 510 }; 511 512 dynamic-range-compressor@2908200 { 513 compatible = "nvidia,tegra194-mbdrc", 514 "nvidia,tegra210-mbdrc"; 515 reg = <0x0 0x2908200 0x0 0x200>; 516 }; 517 }; 518 519 tegra_mvc1: mvc@290a000 { 520 compatible = "nvidia,tegra194-mvc", 521 "nvidia,tegra210-mvc"; 522 reg = <0x0 0x290a000 0x0 0x200>; 523 sound-name-prefix = "MVC1"; 524 status = "disabled"; 525 }; 526 527 tegra_mvc2: mvc@290a200 { 528 compatible = "nvidia,tegra194-mvc", 529 "nvidia,tegra210-mvc"; 530 reg = <0x0 0x290a200 0x0 0x200>; 531 sound-name-prefix = "MVC2"; 532 status = "disabled"; 533 }; 534 535 tegra_amixer: amixer@290bb00 { 536 compatible = "nvidia,tegra194-amixer", 537 "nvidia,tegra210-amixer"; 538 reg = <0x0 0x290bb00 0x0 0x800>; 539 sound-name-prefix = "MIXER1"; 540 status = "disabled"; 541 }; 542 543 tegra_admaif: admaif@290f000 { 544 compatible = "nvidia,tegra194-admaif", 545 "nvidia,tegra186-admaif"; 546 reg = <0x0 0x0290f000 0x0 0x1000>; 547 dmas = <&adma 1>, <&adma 1>, 548 <&adma 2>, <&adma 2>, 549 <&adma 3>, <&adma 3>, 550 <&adma 4>, <&adma 4>, 551 <&adma 5>, <&adma 5>, 552 <&adma 6>, <&adma 6>, 553 <&adma 7>, <&adma 7>, 554 <&adma 8>, <&adma 8>, 555 <&adma 9>, <&adma 9>, 556 <&adma 10>, <&adma 10>, 557 <&adma 11>, <&adma 11>, 558 <&adma 12>, <&adma 12>, 559 <&adma 13>, <&adma 13>, 560 <&adma 14>, <&adma 14>, 561 <&adma 15>, <&adma 15>, 562 <&adma 16>, <&adma 16>, 563 <&adma 17>, <&adma 17>, 564 <&adma 18>, <&adma 18>, 565 <&adma 19>, <&adma 19>, 566 <&adma 20>, <&adma 20>; 567 dma-names = "rx1", "tx1", 568 "rx2", "tx2", 569 "rx3", "tx3", 570 "rx4", "tx4", 571 "rx5", "tx5", 572 "rx6", "tx6", 573 "rx7", "tx7", 574 "rx8", "tx8", 575 "rx9", "tx9", 576 "rx10", "tx10", 577 "rx11", "tx11", 578 "rx12", "tx12", 579 "rx13", "tx13", 580 "rx14", "tx14", 581 "rx15", "tx15", 582 "rx16", "tx16", 583 "rx17", "tx17", 584 "rx18", "tx18", 585 "rx19", "tx19", 586 "rx20", "tx20"; 587 status = "disabled"; 588 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 589 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 590 interconnect-names = "dma-mem", "write"; 591 iommus = <&smmu TEGRA194_SID_APE>; 592 }; 593 594 tegra_asrc: asrc@2910000 { 595 compatible = "nvidia,tegra194-asrc", 596 "nvidia,tegra186-asrc"; 597 reg = <0x0 0x2910000 0x0 0x2000>; 598 sound-name-prefix = "ASRC1"; 599 status = "disabled"; 600 }; 601 }; 602 603 adma: dma-controller@2930000 { 604 compatible = "nvidia,tegra194-adma", 605 "nvidia,tegra186-adma"; 606 reg = <0x0 0x02930000 0x0 0x20000>; 607 interrupt-parent = <&agic>; 608 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 640 #dma-cells = <1>; 641 clocks = <&bpmp TEGRA194_CLK_AHUB>; 642 clock-names = "d_audio"; 643 status = "disabled"; 644 }; 645 646 agic: interrupt-controller@2a40000 { 647 compatible = "nvidia,tegra194-agic", 648 "nvidia,tegra210-agic"; 649 #interrupt-cells = <3>; 650 interrupt-controller; 651 reg = <0x0 0x02a41000 0x0 0x1000>, 652 <0x0 0x02a42000 0x0 0x2000>; 653 interrupts = <GIC_SPI 145 654 (GIC_CPU_MASK_SIMPLE(4) | 655 IRQ_TYPE_LEVEL_HIGH)>; 656 clocks = <&bpmp TEGRA194_CLK_APE>; 657 clock-names = "clk"; 658 status = "disabled"; 659 }; 660 }; 661 662 mc: memory-controller@2c00000 { 663 compatible = "nvidia,tegra194-mc"; 664 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 665 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 666 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 667 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 668 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 669 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 670 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 671 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 672 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 673 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 674 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 675 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 676 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 677 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 678 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 679 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 680 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 681 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 682 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 683 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 684 "ch11", "ch12", "ch13", "ch14", "ch15"; 685 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 686 #interconnect-cells = <1>; 687 status = "disabled"; 688 689 #address-cells = <2>; 690 #size-cells = <2>; 691 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 692 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 693 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 694 695 /* 696 * Bit 39 of addresses passing through the memory 697 * controller selects the XBAR format used when memory 698 * is accessed. This is used to transparently access 699 * memory in the XBAR format used by the discrete GPU 700 * (bit 39 set) or Tegra (bit 39 clear). 701 * 702 * As a consequence, the operating system must ensure 703 * that bit 39 is never used implicitly, for example 704 * via an I/O virtual address mapping of an IOMMU. If 705 * devices require access to the XBAR switch, their 706 * drivers must set this bit explicitly. 707 * 708 * Limit the DMA range for memory clients to [38:0]. 709 */ 710 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 711 712 emc: external-memory-controller@2c60000 { 713 compatible = "nvidia,tegra194-emc"; 714 reg = <0x0 0x02c60000 0x0 0x90000>, 715 <0x0 0x01780000 0x0 0x80000>; 716 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&bpmp TEGRA194_CLK_EMC>; 718 clock-names = "emc"; 719 720 #interconnect-cells = <0>; 721 722 nvidia,bpmp = <&bpmp>; 723 }; 724 }; 725 726 timer@3010000 { 727 compatible = "nvidia,tegra186-timer"; 728 reg = <0x0 0x03010000 0x0 0x000e0000>; 729 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 739 status = "okay"; 740 }; 741 742 uarta: serial@3100000 { 743 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 744 reg = <0x0 0x03100000 0x0 0x40>; 745 reg-shift = <2>; 746 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&bpmp TEGRA194_CLK_UARTA>; 748 clock-names = "serial"; 749 resets = <&bpmp TEGRA194_RESET_UARTA>; 750 reset-names = "serial"; 751 status = "disabled"; 752 }; 753 754 uartb: serial@3110000 { 755 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 756 reg = <0x0 0x03110000 0x0 0x40>; 757 reg-shift = <2>; 758 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&bpmp TEGRA194_CLK_UARTB>; 760 clock-names = "serial"; 761 resets = <&bpmp TEGRA194_RESET_UARTB>; 762 reset-names = "serial"; 763 status = "disabled"; 764 }; 765 766 uartd: serial@3130000 { 767 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 768 reg = <0x0 0x03130000 0x0 0x40>; 769 reg-shift = <2>; 770 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&bpmp TEGRA194_CLK_UARTD>; 772 clock-names = "serial"; 773 resets = <&bpmp TEGRA194_RESET_UARTD>; 774 reset-names = "serial"; 775 status = "disabled"; 776 }; 777 778 uarte: serial@3140000 { 779 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 780 reg = <0x0 0x03140000 0x0 0x40>; 781 reg-shift = <2>; 782 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&bpmp TEGRA194_CLK_UARTE>; 784 clock-names = "serial"; 785 resets = <&bpmp TEGRA194_RESET_UARTE>; 786 reset-names = "serial"; 787 status = "disabled"; 788 }; 789 790 uartf: serial@3150000 { 791 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 792 reg = <0x0 0x03150000 0x0 0x40>; 793 reg-shift = <2>; 794 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&bpmp TEGRA194_CLK_UARTF>; 796 clock-names = "serial"; 797 resets = <&bpmp TEGRA194_RESET_UARTF>; 798 reset-names = "serial"; 799 status = "disabled"; 800 }; 801 802 gen1_i2c: i2c@3160000 { 803 compatible = "nvidia,tegra194-i2c"; 804 reg = <0x0 0x03160000 0x0 0x10000>; 805 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 clocks = <&bpmp TEGRA194_CLK_I2C1>; 809 clock-names = "div-clk"; 810 resets = <&bpmp TEGRA194_RESET_I2C1>; 811 reset-names = "i2c"; 812 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 813 dma-coherent; 814 dmas = <&gpcdma 21>, <&gpcdma 21>; 815 dma-names = "rx", "tx"; 816 status = "disabled"; 817 }; 818 819 uarth: serial@3170000 { 820 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 821 reg = <0x0 0x03170000 0x0 0x40>; 822 reg-shift = <2>; 823 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&bpmp TEGRA194_CLK_UARTH>; 825 clock-names = "serial"; 826 resets = <&bpmp TEGRA194_RESET_UARTH>; 827 reset-names = "serial"; 828 status = "disabled"; 829 }; 830 831 cam_i2c: i2c@3180000 { 832 compatible = "nvidia,tegra194-i2c"; 833 reg = <0x0 0x03180000 0x0 0x10000>; 834 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 clocks = <&bpmp TEGRA194_CLK_I2C3>; 838 clock-names = "div-clk"; 839 resets = <&bpmp TEGRA194_RESET_I2C3>; 840 reset-names = "i2c"; 841 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 842 dma-coherent; 843 dmas = <&gpcdma 23>, <&gpcdma 23>; 844 dma-names = "rx", "tx"; 845 status = "disabled"; 846 }; 847 848 /* shares pads with dpaux1 */ 849 dp_aux_ch1_i2c: i2c@3190000 { 850 compatible = "nvidia,tegra194-i2c"; 851 reg = <0x0 0x03190000 0x0 0x10000>; 852 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 clocks = <&bpmp TEGRA194_CLK_I2C4>; 856 clock-names = "div-clk"; 857 resets = <&bpmp TEGRA194_RESET_I2C4>; 858 reset-names = "i2c"; 859 pinctrl-0 = <&state_dpaux1_i2c>; 860 pinctrl-1 = <&state_dpaux1_off>; 861 pinctrl-names = "default", "idle"; 862 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 863 dma-coherent; 864 dmas = <&gpcdma 26>, <&gpcdma 26>; 865 dma-names = "rx", "tx"; 866 status = "disabled"; 867 }; 868 869 /* shares pads with dpaux0 */ 870 dp_aux_ch0_i2c: i2c@31b0000 { 871 compatible = "nvidia,tegra194-i2c"; 872 reg = <0x0 0x031b0000 0x0 0x10000>; 873 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 clocks = <&bpmp TEGRA194_CLK_I2C6>; 877 clock-names = "div-clk"; 878 resets = <&bpmp TEGRA194_RESET_I2C6>; 879 reset-names = "i2c"; 880 pinctrl-0 = <&state_dpaux0_i2c>; 881 pinctrl-1 = <&state_dpaux0_off>; 882 pinctrl-names = "default", "idle"; 883 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 884 dma-coherent; 885 dmas = <&gpcdma 30>, <&gpcdma 30>; 886 dma-names = "rx", "tx"; 887 status = "disabled"; 888 }; 889 890 /* shares pads with dpaux2 */ 891 dp_aux_ch2_i2c: i2c@31c0000 { 892 compatible = "nvidia,tegra194-i2c"; 893 reg = <0x0 0x031c0000 0x0 0x10000>; 894 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 clocks = <&bpmp TEGRA194_CLK_I2C7>; 898 clock-names = "div-clk"; 899 resets = <&bpmp TEGRA194_RESET_I2C7>; 900 reset-names = "i2c"; 901 pinctrl-0 = <&state_dpaux2_i2c>; 902 pinctrl-1 = <&state_dpaux2_off>; 903 pinctrl-names = "default", "idle"; 904 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 905 dma-coherent; 906 dmas = <&gpcdma 27>, <&gpcdma 27>; 907 dma-names = "rx", "tx"; 908 status = "disabled"; 909 }; 910 911 /* shares pads with dpaux3 */ 912 dp_aux_ch3_i2c: i2c@31e0000 { 913 compatible = "nvidia,tegra194-i2c"; 914 reg = <0x0 0x031e0000 0x0 0x10000>; 915 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 clocks = <&bpmp TEGRA194_CLK_I2C9>; 919 clock-names = "div-clk"; 920 resets = <&bpmp TEGRA194_RESET_I2C9>; 921 reset-names = "i2c"; 922 pinctrl-0 = <&state_dpaux3_i2c>; 923 pinctrl-1 = <&state_dpaux3_off>; 924 pinctrl-names = "default", "idle"; 925 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 926 dma-coherent; 927 dmas = <&gpcdma 31>, <&gpcdma 31>; 928 dma-names = "rx", "tx"; 929 status = "disabled"; 930 }; 931 932 spi@3270000 { 933 compatible = "nvidia,tegra194-qspi"; 934 reg = <0x0 0x3270000 0x0 0x1000>; 935 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 939 <&bpmp TEGRA194_CLK_QSPI0_PM>; 940 clock-names = "qspi", "qspi_out"; 941 resets = <&bpmp TEGRA194_RESET_QSPI0>; 942 status = "disabled"; 943 }; 944 945 pwm1: pwm@3280000 { 946 compatible = "nvidia,tegra194-pwm", 947 "nvidia,tegra186-pwm"; 948 reg = <0x0 0x3280000 0x0 0x10000>; 949 clocks = <&bpmp TEGRA194_CLK_PWM1>; 950 resets = <&bpmp TEGRA194_RESET_PWM1>; 951 reset-names = "pwm"; 952 status = "disabled"; 953 #pwm-cells = <2>; 954 }; 955 956 pwm2: pwm@3290000 { 957 compatible = "nvidia,tegra194-pwm", 958 "nvidia,tegra186-pwm"; 959 reg = <0x0 0x3290000 0x0 0x10000>; 960 clocks = <&bpmp TEGRA194_CLK_PWM2>; 961 resets = <&bpmp TEGRA194_RESET_PWM2>; 962 reset-names = "pwm"; 963 status = "disabled"; 964 #pwm-cells = <2>; 965 }; 966 967 pwm3: pwm@32a0000 { 968 compatible = "nvidia,tegra194-pwm", 969 "nvidia,tegra186-pwm"; 970 reg = <0x0 0x32a0000 0x0 0x10000>; 971 clocks = <&bpmp TEGRA194_CLK_PWM3>; 972 resets = <&bpmp TEGRA194_RESET_PWM3>; 973 reset-names = "pwm"; 974 status = "disabled"; 975 #pwm-cells = <2>; 976 }; 977 978 pwm5: pwm@32c0000 { 979 compatible = "nvidia,tegra194-pwm", 980 "nvidia,tegra186-pwm"; 981 reg = <0x0 0x32c0000 0x0 0x10000>; 982 clocks = <&bpmp TEGRA194_CLK_PWM5>; 983 resets = <&bpmp TEGRA194_RESET_PWM5>; 984 reset-names = "pwm"; 985 status = "disabled"; 986 #pwm-cells = <2>; 987 }; 988 989 pwm6: pwm@32d0000 { 990 compatible = "nvidia,tegra194-pwm", 991 "nvidia,tegra186-pwm"; 992 reg = <0x0 0x32d0000 0x0 0x10000>; 993 clocks = <&bpmp TEGRA194_CLK_PWM6>; 994 resets = <&bpmp TEGRA194_RESET_PWM6>; 995 reset-names = "pwm"; 996 status = "disabled"; 997 #pwm-cells = <2>; 998 }; 999 1000 pwm7: pwm@32e0000 { 1001 compatible = "nvidia,tegra194-pwm", 1002 "nvidia,tegra186-pwm"; 1003 reg = <0x0 0x32e0000 0x0 0x10000>; 1004 clocks = <&bpmp TEGRA194_CLK_PWM7>; 1005 resets = <&bpmp TEGRA194_RESET_PWM7>; 1006 reset-names = "pwm"; 1007 status = "disabled"; 1008 #pwm-cells = <2>; 1009 }; 1010 1011 pwm8: pwm@32f0000 { 1012 compatible = "nvidia,tegra194-pwm", 1013 "nvidia,tegra186-pwm"; 1014 reg = <0x0 0x32f0000 0x0 0x10000>; 1015 clocks = <&bpmp TEGRA194_CLK_PWM8>; 1016 resets = <&bpmp TEGRA194_RESET_PWM8>; 1017 reset-names = "pwm"; 1018 status = "disabled"; 1019 #pwm-cells = <2>; 1020 }; 1021 1022 spi@3300000 { 1023 compatible = "nvidia,tegra194-qspi"; 1024 reg = <0x0 0x3300000 0x0 0x1000>; 1025 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 1029 <&bpmp TEGRA194_CLK_QSPI1_PM>; 1030 clock-names = "qspi", "qspi_out"; 1031 resets = <&bpmp TEGRA194_RESET_QSPI1>; 1032 status = "disabled"; 1033 }; 1034 1035 sdmmc1: mmc@3400000 { 1036 compatible = "nvidia,tegra194-sdhci"; 1037 reg = <0x0 0x03400000 0x0 0x10000>; 1038 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1040 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1041 clock-names = "sdhci", "tmclk"; 1042 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1043 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1044 assigned-clock-parents = 1045 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1046 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1047 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 1048 reset-names = "sdhci"; 1049 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1050 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1051 interconnect-names = "dma-mem", "write"; 1052 iommus = <&smmu TEGRA194_SID_SDMMC1>; 1053 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1054 pinctrl-0 = <&sdmmc1_3v3>; 1055 pinctrl-1 = <&sdmmc1_1v8>; 1056 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 1057 <0x07>; 1058 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1059 <0x07>; 1060 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1061 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1062 <0x07>; 1063 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1064 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1065 nvidia,default-tap = <0x9>; 1066 nvidia,default-trim = <0x5>; 1067 sd-uhs-sdr25; 1068 sd-uhs-sdr50; 1069 sd-uhs-ddr50; 1070 sd-uhs-sdr104; 1071 status = "disabled"; 1072 }; 1073 1074 sdmmc3: mmc@3440000 { 1075 compatible = "nvidia,tegra194-sdhci"; 1076 reg = <0x0 0x03440000 0x0 0x10000>; 1077 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1079 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1080 clock-names = "sdhci", "tmclk"; 1081 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1082 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1083 assigned-clock-parents = 1084 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1085 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1086 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1087 reset-names = "sdhci"; 1088 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1089 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1090 interconnect-names = "dma-mem", "write"; 1091 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1092 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1093 pinctrl-0 = <&sdmmc3_3v3>; 1094 pinctrl-1 = <&sdmmc3_1v8>; 1095 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1096 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1097 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1098 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1099 <0x07>; 1100 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1101 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1102 <0x07>; 1103 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1104 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1105 nvidia,default-tap = <0x9>; 1106 nvidia,default-trim = <0x5>; 1107 sd-uhs-sdr25; 1108 sd-uhs-sdr50; 1109 sd-uhs-ddr50; 1110 sd-uhs-sdr104; 1111 status = "disabled"; 1112 }; 1113 1114 sdmmc4: mmc@3460000 { 1115 compatible = "nvidia,tegra194-sdhci"; 1116 reg = <0x0 0x03460000 0x0 0x10000>; 1117 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1119 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1120 clock-names = "sdhci", "tmclk"; 1121 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1122 <&bpmp TEGRA194_CLK_PLLC4>; 1123 assigned-clock-parents = 1124 <&bpmp TEGRA194_CLK_PLLC4>; 1125 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1126 reset-names = "sdhci"; 1127 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1128 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1129 interconnect-names = "dma-mem", "write"; 1130 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1131 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1132 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1133 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1134 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1135 <0x0a>; 1136 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1137 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1138 <0x0a>; 1139 nvidia,default-tap = <0x8>; 1140 nvidia,default-trim = <0x14>; 1141 nvidia,dqs-trim = <40>; 1142 cap-mmc-highspeed; 1143 mmc-ddr-1_8v; 1144 mmc-hs200-1_8v; 1145 mmc-hs400-1_8v; 1146 mmc-hs400-enhanced-strobe; 1147 supports-cqe; 1148 status = "disabled"; 1149 }; 1150 1151 hda@3510000 { 1152 compatible = "nvidia,tegra194-hda"; 1153 reg = <0x0 0x3510000 0x0 0x10000>; 1154 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1155 clocks = <&bpmp TEGRA194_CLK_HDA>, 1156 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1157 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1158 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1159 resets = <&bpmp TEGRA194_RESET_HDA>, 1160 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1161 reset-names = "hda", "hda2hdmi"; 1162 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1163 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1164 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1165 interconnect-names = "dma-mem", "write"; 1166 iommus = <&smmu TEGRA194_SID_HDA>; 1167 status = "disabled"; 1168 }; 1169 1170 xusb_padctl: padctl@3520000 { 1171 compatible = "nvidia,tegra194-xusb-padctl"; 1172 reg = <0x0 0x03520000 0x0 0x1000>, 1173 <0x0 0x03540000 0x0 0x1000>; 1174 reg-names = "padctl", "ao"; 1175 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1176 1177 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1178 reset-names = "padctl"; 1179 1180 status = "disabled"; 1181 1182 pads { 1183 usb2 { 1184 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1185 clock-names = "trk"; 1186 1187 lanes { 1188 usb2-0 { 1189 nvidia,function = "xusb"; 1190 status = "disabled"; 1191 #phy-cells = <0>; 1192 }; 1193 1194 usb2-1 { 1195 nvidia,function = "xusb"; 1196 status = "disabled"; 1197 #phy-cells = <0>; 1198 }; 1199 1200 usb2-2 { 1201 nvidia,function = "xusb"; 1202 status = "disabled"; 1203 #phy-cells = <0>; 1204 }; 1205 1206 usb2-3 { 1207 nvidia,function = "xusb"; 1208 status = "disabled"; 1209 #phy-cells = <0>; 1210 }; 1211 }; 1212 }; 1213 1214 usb3 { 1215 lanes { 1216 usb3-0 { 1217 nvidia,function = "xusb"; 1218 status = "disabled"; 1219 #phy-cells = <0>; 1220 }; 1221 1222 usb3-1 { 1223 nvidia,function = "xusb"; 1224 status = "disabled"; 1225 #phy-cells = <0>; 1226 }; 1227 1228 usb3-2 { 1229 nvidia,function = "xusb"; 1230 status = "disabled"; 1231 #phy-cells = <0>; 1232 }; 1233 1234 usb3-3 { 1235 nvidia,function = "xusb"; 1236 status = "disabled"; 1237 #phy-cells = <0>; 1238 }; 1239 }; 1240 }; 1241 }; 1242 1243 ports { 1244 usb2-0 { 1245 status = "disabled"; 1246 }; 1247 1248 usb2-1 { 1249 status = "disabled"; 1250 }; 1251 1252 usb2-2 { 1253 status = "disabled"; 1254 }; 1255 1256 usb2-3 { 1257 status = "disabled"; 1258 }; 1259 1260 usb3-0 { 1261 status = "disabled"; 1262 }; 1263 1264 usb3-1 { 1265 status = "disabled"; 1266 }; 1267 1268 usb3-2 { 1269 status = "disabled"; 1270 }; 1271 1272 usb3-3 { 1273 status = "disabled"; 1274 }; 1275 }; 1276 }; 1277 1278 usb@3550000 { 1279 compatible = "nvidia,tegra194-xudc"; 1280 reg = <0x0 0x03550000 0x0 0x8000>, 1281 <0x0 0x03558000 0x0 0x1000>; 1282 reg-names = "base", "fpci"; 1283 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1284 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1285 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1286 <&bpmp TEGRA194_CLK_XUSB_SS>, 1287 <&bpmp TEGRA194_CLK_XUSB_FS>; 1288 clock-names = "dev", "ss", "ss_src", "fs_src"; 1289 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1290 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1291 interconnect-names = "dma-mem", "write"; 1292 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1293 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1294 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1295 power-domain-names = "dev", "ss"; 1296 nvidia,xusb-padctl = <&xusb_padctl>; 1297 dma-coherent; 1298 status = "disabled"; 1299 }; 1300 1301 usb@3610000 { 1302 compatible = "nvidia,tegra194-xusb"; 1303 reg = <0x0 0x03610000 0x0 0x40000>, 1304 <0x0 0x03600000 0x0 0x10000>; 1305 reg-names = "hcd", "fpci"; 1306 1307 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1309 1310 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1311 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1312 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1313 <&bpmp TEGRA194_CLK_XUSB_SS>, 1314 <&bpmp TEGRA194_CLK_CLK_M>, 1315 <&bpmp TEGRA194_CLK_XUSB_FS>, 1316 <&bpmp TEGRA194_CLK_UTMIPLL>, 1317 <&bpmp TEGRA194_CLK_CLK_M>, 1318 <&bpmp TEGRA194_CLK_PLLE>; 1319 clock-names = "xusb_host", "xusb_falcon_src", 1320 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1321 "xusb_fs_src", "pll_u_480m", "clk_m", 1322 "pll_e"; 1323 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1324 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1325 interconnect-names = "dma-mem", "write"; 1326 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1327 1328 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1329 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1330 power-domain-names = "xusb_host", "xusb_ss"; 1331 1332 nvidia,xusb-padctl = <&xusb_padctl>; 1333 status = "disabled"; 1334 }; 1335 1336 fuse@3820000 { 1337 compatible = "nvidia,tegra194-efuse"; 1338 reg = <0x0 0x03820000 0x0 0x10000>; 1339 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1340 clock-names = "fuse"; 1341 }; 1342 1343 gic: interrupt-controller@3881000 { 1344 compatible = "arm,gic-400"; 1345 #interrupt-cells = <3>; 1346 interrupt-controller; 1347 reg = <0x0 0x03881000 0x0 0x1000>, 1348 <0x0 0x03882000 0x0 0x2000>, 1349 <0x0 0x03884000 0x0 0x2000>, 1350 <0x0 0x03886000 0x0 0x2000>; 1351 interrupts = <GIC_PPI 9 1352 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1353 interrupt-parent = <&gic>; 1354 }; 1355 1356 cec@3960000 { 1357 compatible = "nvidia,tegra194-cec"; 1358 reg = <0x0 0x03960000 0x0 0x10000>; 1359 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1360 clocks = <&bpmp TEGRA194_CLK_CEC>; 1361 clock-names = "cec"; 1362 status = "disabled"; 1363 }; 1364 1365 hte_lic: hardware-timestamp@3aa0000 { 1366 compatible = "nvidia,tegra194-gte-lic"; 1367 reg = <0x0 0x3aa0000 0x0 0x10000>; 1368 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1369 nvidia,int-threshold = <1>; 1370 nvidia,slices = <11>; 1371 #timestamp-cells = <1>; 1372 status = "okay"; 1373 }; 1374 1375 hsp_top0: hsp@3c00000 { 1376 compatible = "nvidia,tegra194-hsp"; 1377 reg = <0x0 0x03c00000 0x0 0xa0000>; 1378 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1387 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1388 "shared3", "shared4", "shared5", "shared6", 1389 "shared7"; 1390 #mbox-cells = <2>; 1391 }; 1392 1393 p2u_hsio_0: phy@3e10000 { 1394 compatible = "nvidia,tegra194-p2u"; 1395 reg = <0x0 0x03e10000 0x0 0x10000>; 1396 reg-names = "ctl"; 1397 1398 #phy-cells = <0>; 1399 }; 1400 1401 p2u_hsio_1: phy@3e20000 { 1402 compatible = "nvidia,tegra194-p2u"; 1403 reg = <0x0 0x03e20000 0x0 0x10000>; 1404 reg-names = "ctl"; 1405 1406 #phy-cells = <0>; 1407 }; 1408 1409 p2u_hsio_2: phy@3e30000 { 1410 compatible = "nvidia,tegra194-p2u"; 1411 reg = <0x0 0x03e30000 0x0 0x10000>; 1412 reg-names = "ctl"; 1413 1414 #phy-cells = <0>; 1415 }; 1416 1417 p2u_hsio_3: phy@3e40000 { 1418 compatible = "nvidia,tegra194-p2u"; 1419 reg = <0x0 0x03e40000 0x0 0x10000>; 1420 reg-names = "ctl"; 1421 1422 #phy-cells = <0>; 1423 }; 1424 1425 p2u_hsio_4: phy@3e50000 { 1426 compatible = "nvidia,tegra194-p2u"; 1427 reg = <0x0 0x03e50000 0x0 0x10000>; 1428 reg-names = "ctl"; 1429 1430 #phy-cells = <0>; 1431 }; 1432 1433 p2u_hsio_5: phy@3e60000 { 1434 compatible = "nvidia,tegra194-p2u"; 1435 reg = <0x0 0x03e60000 0x0 0x10000>; 1436 reg-names = "ctl"; 1437 1438 #phy-cells = <0>; 1439 }; 1440 1441 p2u_hsio_6: phy@3e70000 { 1442 compatible = "nvidia,tegra194-p2u"; 1443 reg = <0x0 0x03e70000 0x0 0x10000>; 1444 reg-names = "ctl"; 1445 1446 #phy-cells = <0>; 1447 }; 1448 1449 p2u_hsio_7: phy@3e80000 { 1450 compatible = "nvidia,tegra194-p2u"; 1451 reg = <0x0 0x03e80000 0x0 0x10000>; 1452 reg-names = "ctl"; 1453 1454 #phy-cells = <0>; 1455 }; 1456 1457 p2u_hsio_8: phy@3e90000 { 1458 compatible = "nvidia,tegra194-p2u"; 1459 reg = <0x0 0x03e90000 0x0 0x10000>; 1460 reg-names = "ctl"; 1461 1462 #phy-cells = <0>; 1463 }; 1464 1465 p2u_hsio_9: phy@3ea0000 { 1466 compatible = "nvidia,tegra194-p2u"; 1467 reg = <0x0 0x03ea0000 0x0 0x10000>; 1468 reg-names = "ctl"; 1469 1470 #phy-cells = <0>; 1471 }; 1472 1473 p2u_nvhs_0: phy@3eb0000 { 1474 compatible = "nvidia,tegra194-p2u"; 1475 reg = <0x0 0x03eb0000 0x0 0x10000>; 1476 reg-names = "ctl"; 1477 1478 #phy-cells = <0>; 1479 }; 1480 1481 p2u_nvhs_1: phy@3ec0000 { 1482 compatible = "nvidia,tegra194-p2u"; 1483 reg = <0x0 0x03ec0000 0x0 0x10000>; 1484 reg-names = "ctl"; 1485 1486 #phy-cells = <0>; 1487 }; 1488 1489 p2u_nvhs_2: phy@3ed0000 { 1490 compatible = "nvidia,tegra194-p2u"; 1491 reg = <0x0 0x03ed0000 0x0 0x10000>; 1492 reg-names = "ctl"; 1493 1494 #phy-cells = <0>; 1495 }; 1496 1497 p2u_nvhs_3: phy@3ee0000 { 1498 compatible = "nvidia,tegra194-p2u"; 1499 reg = <0x0 0x03ee0000 0x0 0x10000>; 1500 reg-names = "ctl"; 1501 1502 #phy-cells = <0>; 1503 }; 1504 1505 p2u_nvhs_4: phy@3ef0000 { 1506 compatible = "nvidia,tegra194-p2u"; 1507 reg = <0x0 0x03ef0000 0x0 0x10000>; 1508 reg-names = "ctl"; 1509 1510 #phy-cells = <0>; 1511 }; 1512 1513 p2u_nvhs_5: phy@3f00000 { 1514 compatible = "nvidia,tegra194-p2u"; 1515 reg = <0x0 0x03f00000 0x0 0x10000>; 1516 reg-names = "ctl"; 1517 1518 #phy-cells = <0>; 1519 }; 1520 1521 p2u_nvhs_6: phy@3f10000 { 1522 compatible = "nvidia,tegra194-p2u"; 1523 reg = <0x0 0x03f10000 0x0 0x10000>; 1524 reg-names = "ctl"; 1525 1526 #phy-cells = <0>; 1527 }; 1528 1529 p2u_nvhs_7: phy@3f20000 { 1530 compatible = "nvidia,tegra194-p2u"; 1531 reg = <0x0 0x03f20000 0x0 0x10000>; 1532 reg-names = "ctl"; 1533 1534 #phy-cells = <0>; 1535 }; 1536 1537 p2u_hsio_10: phy@3f30000 { 1538 compatible = "nvidia,tegra194-p2u"; 1539 reg = <0x0 0x03f30000 0x0 0x10000>; 1540 reg-names = "ctl"; 1541 1542 #phy-cells = <0>; 1543 }; 1544 1545 p2u_hsio_11: phy@3f40000 { 1546 compatible = "nvidia,tegra194-p2u"; 1547 reg = <0x0 0x03f40000 0x0 0x10000>; 1548 reg-names = "ctl"; 1549 1550 #phy-cells = <0>; 1551 }; 1552 1553 sce-noc@b600000 { 1554 compatible = "nvidia,tegra194-sce-noc"; 1555 reg = <0x0 0xb600000 0x0 0x1000>; 1556 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1558 nvidia,axi2apb = <&axi2apb>; 1559 nvidia,apbmisc = <&apbmisc>; 1560 status = "okay"; 1561 }; 1562 1563 rce-noc@be00000 { 1564 compatible = "nvidia,tegra194-rce-noc"; 1565 reg = <0x0 0xbe00000 0x0 0x1000>; 1566 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1568 nvidia,axi2apb = <&axi2apb>; 1569 nvidia,apbmisc = <&apbmisc>; 1570 status = "okay"; 1571 }; 1572 1573 hsp_aon: hsp@c150000 { 1574 compatible = "nvidia,tegra194-hsp"; 1575 reg = <0x0 0x0c150000 0x0 0x90000>; 1576 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1580 /* 1581 * Shared interrupt 0 is routed only to AON/SPE, so 1582 * we only have 4 shared interrupts for the CCPLEX. 1583 */ 1584 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1585 #mbox-cells = <2>; 1586 }; 1587 1588 hte_aon: hardware-timestamp@c1e0000 { 1589 compatible = "nvidia,tegra194-gte-aon"; 1590 reg = <0x0 0xc1e0000 0x0 0x10000>; 1591 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1592 nvidia,int-threshold = <1>; 1593 nvidia,slices = <3>; 1594 #timestamp-cells = <1>; 1595 status = "okay"; 1596 }; 1597 1598 gen2_i2c: i2c@c240000 { 1599 compatible = "nvidia,tegra194-i2c"; 1600 reg = <0x0 0x0c240000 0x0 0x10000>; 1601 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1605 clock-names = "div-clk"; 1606 resets = <&bpmp TEGRA194_RESET_I2C2>; 1607 reset-names = "i2c"; 1608 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1609 dma-coherent; 1610 dmas = <&gpcdma 22>, <&gpcdma 22>; 1611 dma-names = "rx", "tx"; 1612 status = "disabled"; 1613 }; 1614 1615 gen8_i2c: i2c@c250000 { 1616 compatible = "nvidia,tegra194-i2c"; 1617 reg = <0x0 0x0c250000 0x0 0x10000>; 1618 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1622 clock-names = "div-clk"; 1623 resets = <&bpmp TEGRA194_RESET_I2C8>; 1624 reset-names = "i2c"; 1625 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1626 dma-coherent; 1627 dmas = <&gpcdma 0>, <&gpcdma 0>; 1628 dma-names = "rx", "tx"; 1629 status = "disabled"; 1630 }; 1631 1632 uartc: serial@c280000 { 1633 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1634 reg = <0x0 0x0c280000 0x0 0x40>; 1635 reg-shift = <2>; 1636 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1637 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1638 clock-names = "serial"; 1639 resets = <&bpmp TEGRA194_RESET_UARTC>; 1640 reset-names = "serial"; 1641 status = "disabled"; 1642 }; 1643 1644 uartg: serial@c290000 { 1645 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1646 reg = <0x0 0x0c290000 0x0 0x40>; 1647 reg-shift = <2>; 1648 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1649 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1650 clock-names = "serial"; 1651 resets = <&bpmp TEGRA194_RESET_UARTG>; 1652 reset-names = "serial"; 1653 status = "disabled"; 1654 }; 1655 1656 rtc: rtc@c2a0000 { 1657 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1658 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1659 interrupt-parent = <&pmc>; 1660 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1661 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1662 clock-names = "rtc"; 1663 status = "disabled"; 1664 }; 1665 1666 gpio_aon: gpio@c2f0000 { 1667 compatible = "nvidia,tegra194-gpio-aon"; 1668 reg-names = "security", "gpio"; 1669 reg = <0x0 0xc2f0000 0x0 0x1000>, 1670 <0x0 0xc2f1000 0x0 0x1000>; 1671 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1675 gpio-controller; 1676 #gpio-cells = <2>; 1677 interrupt-controller; 1678 #interrupt-cells = <2>; 1679 gpio-ranges = <&pinmux_aon 0 0 30>; 1680 }; 1681 1682 pinmux_aon: pinmux@c300000 { 1683 compatible = "nvidia,tegra194-pinmux-aon"; 1684 reg = <0x0 0xc300000 0x0 0x4000>; 1685 1686 status = "okay"; 1687 }; 1688 1689 pwm4: pwm@c340000 { 1690 compatible = "nvidia,tegra194-pwm", 1691 "nvidia,tegra186-pwm"; 1692 reg = <0x0 0xc340000 0x0 0x10000>; 1693 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1694 resets = <&bpmp TEGRA194_RESET_PWM4>; 1695 reset-names = "pwm"; 1696 status = "disabled"; 1697 #pwm-cells = <2>; 1698 }; 1699 1700 pmc: pmc@c360000 { 1701 compatible = "nvidia,tegra194-pmc"; 1702 reg = <0x0 0x0c360000 0x0 0x10000>, 1703 <0x0 0x0c370000 0x0 0x10000>, 1704 <0x0 0x0c380000 0x0 0x10000>, 1705 <0x0 0x0c390000 0x0 0x10000>, 1706 <0x0 0x0c3a0000 0x0 0x10000>; 1707 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1708 1709 #interrupt-cells = <2>; 1710 interrupt-controller; 1711 1712 sdmmc1_1v8: sdmmc1-1v8 { 1713 pins = "sdmmc1-hv"; 1714 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1715 }; 1716 1717 sdmmc1_3v3: sdmmc1-3v3 { 1718 pins = "sdmmc1-hv"; 1719 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1720 }; 1721 1722 sdmmc3_1v8: sdmmc3-1v8 { 1723 pins = "sdmmc3-hv"; 1724 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1725 }; 1726 1727 sdmmc3_3v3: sdmmc3-3v3 { 1728 pins = "sdmmc3-hv"; 1729 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1730 }; 1731 }; 1732 1733 aon-noc@c600000 { 1734 compatible = "nvidia,tegra194-aon-noc"; 1735 reg = <0x0 0xc600000 0x0 0x1000>; 1736 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1738 nvidia,apbmisc = <&apbmisc>; 1739 status = "okay"; 1740 }; 1741 1742 bpmp-noc@d600000 { 1743 compatible = "nvidia,tegra194-bpmp-noc"; 1744 reg = <0x0 0xd600000 0x0 0x1000>; 1745 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1747 nvidia,axi2apb = <&axi2apb>; 1748 nvidia,apbmisc = <&apbmisc>; 1749 status = "okay"; 1750 }; 1751 1752 iommu@10000000 { 1753 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1754 reg = <0x0 0x10000000 0x0 0x800000>; 1755 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1820 stream-match-mask = <0x7f80>; 1821 #global-interrupts = <1>; 1822 #iommu-cells = <1>; 1823 1824 nvidia,memory-controller = <&mc>; 1825 status = "disabled"; 1826 }; 1827 1828 smmu: iommu@12000000 { 1829 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1830 reg = <0x0 0x12000000 0x0 0x800000>, 1831 <0x0 0x11000000 0x0 0x800000>; 1832 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1898 stream-match-mask = <0x7f80>; 1899 #global-interrupts = <2>; 1900 #iommu-cells = <1>; 1901 1902 nvidia,memory-controller = <&mc>; 1903 status = "okay"; 1904 }; 1905 1906 host1x@13e00000 { 1907 compatible = "nvidia,tegra194-host1x"; 1908 reg = <0x0 0x13e00000 0x0 0x10000>, 1909 <0x0 0x13e10000 0x0 0x10000>; 1910 reg-names = "hypervisor", "vm"; 1911 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1913 interrupt-names = "syncpt", "host1x"; 1914 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1915 clock-names = "host1x"; 1916 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1917 reset-names = "host1x"; 1918 1919 #address-cells = <2>; 1920 #size-cells = <2>; 1921 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>; 1922 1923 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1924 interconnect-names = "dma-mem"; 1925 iommus = <&smmu TEGRA194_SID_HOST1X>; 1926 dma-coherent; 1927 1928 /* Context isolation domains */ 1929 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1930 <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1931 <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1932 <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1933 <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1934 <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1935 <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1936 <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1937 1938 nvdec@15140000 { 1939 compatible = "nvidia,tegra194-nvdec"; 1940 reg = <0x0 0x15140000 0x0 0x00040000>; 1941 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1942 clock-names = "nvdec"; 1943 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1944 reset-names = "nvdec"; 1945 1946 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1947 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1948 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1949 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1950 interconnect-names = "dma-mem", "read-1", "write"; 1951 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1952 dma-coherent; 1953 1954 nvidia,host1x-class = <0xf5>; 1955 }; 1956 1957 display-hub@15200000 { 1958 compatible = "nvidia,tegra194-display"; 1959 reg = <0x0 0x15200000 0x0 0x00040000>; 1960 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1961 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1962 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1963 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1964 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1965 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1966 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1967 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1968 "wgrp3", "wgrp4", "wgrp5"; 1969 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1970 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1971 clock-names = "disp", "hub"; 1972 status = "disabled"; 1973 1974 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1975 1976 #address-cells = <2>; 1977 #size-cells = <2>; 1978 ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; 1979 1980 display@15200000 { 1981 compatible = "nvidia,tegra194-dc"; 1982 reg = <0x0 0x15200000 0x0 0x10000>; 1983 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1984 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1985 clock-names = "dc"; 1986 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1987 reset-names = "dc"; 1988 1989 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1990 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1991 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1992 interconnect-names = "dma-mem", "read-1"; 1993 1994 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1995 nvidia,head = <0>; 1996 }; 1997 1998 display@15210000 { 1999 compatible = "nvidia,tegra194-dc"; 2000 reg = <0x0 0x15210000 0x0 0x10000>; 2001 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 2002 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 2003 clock-names = "dc"; 2004 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 2005 reset-names = "dc"; 2006 2007 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 2008 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2009 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2010 interconnect-names = "dma-mem", "read-1"; 2011 2012 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2013 nvidia,head = <1>; 2014 }; 2015 2016 display@15220000 { 2017 compatible = "nvidia,tegra194-dc"; 2018 reg = <0x0 0x15220000 0x0 0x10000>; 2019 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2020 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 2021 clock-names = "dc"; 2022 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 2023 reset-names = "dc"; 2024 2025 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2026 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2027 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2028 interconnect-names = "dma-mem", "read-1"; 2029 2030 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2031 nvidia,head = <2>; 2032 }; 2033 2034 display@15230000 { 2035 compatible = "nvidia,tegra194-dc"; 2036 reg = <0x0 0x15230000 0x0 0x10000>; 2037 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2038 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 2039 clock-names = "dc"; 2040 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 2041 reset-names = "dc"; 2042 2043 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2044 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2045 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2046 interconnect-names = "dma-mem", "read-1"; 2047 2048 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2049 nvidia,head = <3>; 2050 }; 2051 }; 2052 2053 vic@15340000 { 2054 compatible = "nvidia,tegra194-vic"; 2055 reg = <0x0 0x15340000 0x0 0x00040000>; 2056 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2057 clocks = <&bpmp TEGRA194_CLK_VIC>; 2058 clock-names = "vic"; 2059 resets = <&bpmp TEGRA194_RESET_VIC>; 2060 reset-names = "vic"; 2061 2062 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2063 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2064 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2065 interconnect-names = "dma-mem", "write"; 2066 iommus = <&smmu TEGRA194_SID_VIC>; 2067 dma-coherent; 2068 }; 2069 2070 nvjpg@15380000 { 2071 compatible = "nvidia,tegra194-nvjpg"; 2072 reg = <0x0 0x15380000 0x0 0x40000>; 2073 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2074 clock-names = "nvjpg"; 2075 resets = <&bpmp TEGRA194_RESET_NVJPG>; 2076 reset-names = "nvjpg"; 2077 2078 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2079 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2080 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2081 interconnect-names = "dma-mem", "write"; 2082 iommus = <&smmu TEGRA194_SID_NVJPG>; 2083 dma-coherent; 2084 }; 2085 2086 nvdec@15480000 { 2087 compatible = "nvidia,tegra194-nvdec"; 2088 reg = <0x0 0x15480000 0x0 0x00040000>; 2089 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 2090 clock-names = "nvdec"; 2091 resets = <&bpmp TEGRA194_RESET_NVDEC>; 2092 reset-names = "nvdec"; 2093 2094 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 2095 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 2096 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 2097 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 2098 interconnect-names = "dma-mem", "read-1", "write"; 2099 iommus = <&smmu TEGRA194_SID_NVDEC>; 2100 dma-coherent; 2101 2102 nvidia,host1x-class = <0xf0>; 2103 }; 2104 2105 nvenc@154c0000 { 2106 compatible = "nvidia,tegra194-nvenc"; 2107 reg = <0x0 0x154c0000 0x0 0x40000>; 2108 clocks = <&bpmp TEGRA194_CLK_NVENC>; 2109 clock-names = "nvenc"; 2110 resets = <&bpmp TEGRA194_RESET_NVENC>; 2111 reset-names = "nvenc"; 2112 2113 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2114 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2115 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2116 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2117 interconnect-names = "dma-mem", "read-1", "write"; 2118 iommus = <&smmu TEGRA194_SID_NVENC>; 2119 dma-coherent; 2120 2121 nvidia,host1x-class = <0x21>; 2122 }; 2123 2124 dpaux0: dpaux@155c0000 { 2125 compatible = "nvidia,tegra194-dpaux"; 2126 reg = <0x0 0x155c0000 0x0 0x10000>; 2127 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 2128 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 2129 <&bpmp TEGRA194_CLK_PLLDP>; 2130 clock-names = "dpaux", "parent"; 2131 resets = <&bpmp TEGRA194_RESET_DPAUX>; 2132 reset-names = "dpaux"; 2133 status = "disabled"; 2134 2135 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2136 2137 state_dpaux0_aux: pinmux-aux { 2138 groups = "dpaux-io"; 2139 function = "aux"; 2140 }; 2141 2142 state_dpaux0_i2c: pinmux-i2c { 2143 groups = "dpaux-io"; 2144 function = "i2c"; 2145 }; 2146 2147 state_dpaux0_off: pinmux-off { 2148 groups = "dpaux-io"; 2149 function = "off"; 2150 }; 2151 2152 i2c-bus { 2153 #address-cells = <1>; 2154 #size-cells = <0>; 2155 }; 2156 }; 2157 2158 dpaux1: dpaux@155d0000 { 2159 compatible = "nvidia,tegra194-dpaux"; 2160 reg = <0x0 0x155d0000 0x0 0x10000>; 2161 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2162 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 2163 <&bpmp TEGRA194_CLK_PLLDP>; 2164 clock-names = "dpaux", "parent"; 2165 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2166 reset-names = "dpaux"; 2167 status = "disabled"; 2168 2169 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2170 2171 state_dpaux1_aux: pinmux-aux { 2172 groups = "dpaux-io"; 2173 function = "aux"; 2174 }; 2175 2176 state_dpaux1_i2c: pinmux-i2c { 2177 groups = "dpaux-io"; 2178 function = "i2c"; 2179 }; 2180 2181 state_dpaux1_off: pinmux-off { 2182 groups = "dpaux-io"; 2183 function = "off"; 2184 }; 2185 2186 i2c-bus { 2187 #address-cells = <1>; 2188 #size-cells = <0>; 2189 }; 2190 }; 2191 2192 dpaux2: dpaux@155e0000 { 2193 compatible = "nvidia,tegra194-dpaux"; 2194 reg = <0x0 0x155e0000 0x0 0x10000>; 2195 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2196 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2197 <&bpmp TEGRA194_CLK_PLLDP>; 2198 clock-names = "dpaux", "parent"; 2199 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2200 reset-names = "dpaux"; 2201 status = "disabled"; 2202 2203 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2204 2205 state_dpaux2_aux: pinmux-aux { 2206 groups = "dpaux-io"; 2207 function = "aux"; 2208 }; 2209 2210 state_dpaux2_i2c: pinmux-i2c { 2211 groups = "dpaux-io"; 2212 function = "i2c"; 2213 }; 2214 2215 state_dpaux2_off: pinmux-off { 2216 groups = "dpaux-io"; 2217 function = "off"; 2218 }; 2219 2220 i2c-bus { 2221 #address-cells = <1>; 2222 #size-cells = <0>; 2223 }; 2224 }; 2225 2226 dpaux3: dpaux@155f0000 { 2227 compatible = "nvidia,tegra194-dpaux"; 2228 reg = <0x0 0x155f0000 0x0 0x10000>; 2229 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2230 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2231 <&bpmp TEGRA194_CLK_PLLDP>; 2232 clock-names = "dpaux", "parent"; 2233 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2234 reset-names = "dpaux"; 2235 status = "disabled"; 2236 2237 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2238 2239 state_dpaux3_aux: pinmux-aux { 2240 groups = "dpaux-io"; 2241 function = "aux"; 2242 }; 2243 2244 state_dpaux3_i2c: pinmux-i2c { 2245 groups = "dpaux-io"; 2246 function = "i2c"; 2247 }; 2248 2249 state_dpaux3_off: pinmux-off { 2250 groups = "dpaux-io"; 2251 function = "off"; 2252 }; 2253 2254 i2c-bus { 2255 #address-cells = <1>; 2256 #size-cells = <0>; 2257 }; 2258 }; 2259 2260 nvenc@15a80000 { 2261 compatible = "nvidia,tegra194-nvenc"; 2262 reg = <0x0 0x15a80000 0x0 0x00040000>; 2263 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2264 clock-names = "nvenc"; 2265 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2266 reset-names = "nvenc"; 2267 2268 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2269 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2270 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2271 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2272 interconnect-names = "dma-mem", "read-1", "write"; 2273 iommus = <&smmu TEGRA194_SID_NVENC1>; 2274 dma-coherent; 2275 2276 nvidia,host1x-class = <0x22>; 2277 }; 2278 2279 sor0: sor@15b00000 { 2280 compatible = "nvidia,tegra194-sor"; 2281 reg = <0x0 0x15b00000 0x0 0x40000>; 2282 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2283 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2284 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2285 <&bpmp TEGRA194_CLK_PLLD>, 2286 <&bpmp TEGRA194_CLK_PLLDP>, 2287 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2288 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2289 clock-names = "sor", "out", "parent", "dp", "safe", 2290 "pad"; 2291 resets = <&bpmp TEGRA194_RESET_SOR0>; 2292 reset-names = "sor"; 2293 pinctrl-0 = <&state_dpaux0_aux>; 2294 pinctrl-1 = <&state_dpaux0_i2c>; 2295 pinctrl-2 = <&state_dpaux0_off>; 2296 pinctrl-names = "aux", "i2c", "off"; 2297 status = "disabled"; 2298 2299 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2300 nvidia,interface = <0>; 2301 }; 2302 2303 sor1: sor@15b40000 { 2304 compatible = "nvidia,tegra194-sor"; 2305 reg = <0x0 0x15b40000 0x0 0x40000>; 2306 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2307 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2308 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2309 <&bpmp TEGRA194_CLK_PLLD2>, 2310 <&bpmp TEGRA194_CLK_PLLDP>, 2311 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2312 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2313 clock-names = "sor", "out", "parent", "dp", "safe", 2314 "pad"; 2315 resets = <&bpmp TEGRA194_RESET_SOR1>; 2316 reset-names = "sor"; 2317 pinctrl-0 = <&state_dpaux1_aux>; 2318 pinctrl-1 = <&state_dpaux1_i2c>; 2319 pinctrl-2 = <&state_dpaux1_off>; 2320 pinctrl-names = "aux", "i2c", "off"; 2321 status = "disabled"; 2322 2323 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2324 nvidia,interface = <1>; 2325 }; 2326 2327 sor2: sor@15b80000 { 2328 compatible = "nvidia,tegra194-sor"; 2329 reg = <0x0 0x15b80000 0x0 0x40000>; 2330 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2331 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2332 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2333 <&bpmp TEGRA194_CLK_PLLD3>, 2334 <&bpmp TEGRA194_CLK_PLLDP>, 2335 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2336 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2337 clock-names = "sor", "out", "parent", "dp", "safe", 2338 "pad"; 2339 resets = <&bpmp TEGRA194_RESET_SOR2>; 2340 reset-names = "sor"; 2341 pinctrl-0 = <&state_dpaux2_aux>; 2342 pinctrl-1 = <&state_dpaux2_i2c>; 2343 pinctrl-2 = <&state_dpaux2_off>; 2344 pinctrl-names = "aux", "i2c", "off"; 2345 status = "disabled"; 2346 2347 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2348 nvidia,interface = <2>; 2349 }; 2350 2351 sor3: sor@15bc0000 { 2352 compatible = "nvidia,tegra194-sor"; 2353 reg = <0x0 0x15bc0000 0x0 0x40000>; 2354 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2355 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2356 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2357 <&bpmp TEGRA194_CLK_PLLD4>, 2358 <&bpmp TEGRA194_CLK_PLLDP>, 2359 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2360 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2361 clock-names = "sor", "out", "parent", "dp", "safe", 2362 "pad"; 2363 resets = <&bpmp TEGRA194_RESET_SOR3>; 2364 reset-names = "sor"; 2365 pinctrl-0 = <&state_dpaux3_aux>; 2366 pinctrl-1 = <&state_dpaux3_i2c>; 2367 pinctrl-2 = <&state_dpaux3_off>; 2368 pinctrl-names = "aux", "i2c", "off"; 2369 status = "disabled"; 2370 2371 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2372 nvidia,interface = <3>; 2373 }; 2374 }; 2375 2376 pcie@14100000 { 2377 compatible = "nvidia,tegra194-pcie"; 2378 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2379 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2380 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2381 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2382 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2383 reg-names = "appl", "config", "atu_dma", "dbi"; 2384 2385 status = "disabled"; 2386 2387 #address-cells = <3>; 2388 #size-cells = <2>; 2389 device_type = "pci"; 2390 num-lanes = <1>; 2391 linux,pci-domain = <1>; 2392 2393 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2394 clock-names = "core"; 2395 2396 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2397 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2398 reset-names = "apb", "core"; 2399 2400 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2401 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2402 interrupt-names = "intr", "msi"; 2403 2404 #interrupt-cells = <1>; 2405 interrupt-map-mask = <0 0 0 0>; 2406 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2407 2408 nvidia,bpmp = <&bpmp 1>; 2409 2410 nvidia,aspm-cmrt-us = <60>; 2411 nvidia,aspm-pwr-on-t-us = <20>; 2412 nvidia,aspm-l0s-entrance-latency-us = <3>; 2413 2414 bus-range = <0x0 0xff>; 2415 2416 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2417 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2418 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2419 2420 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2421 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2422 interconnect-names = "dma-mem", "write"; 2423 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2424 iommu-map-mask = <0x0>; 2425 dma-coherent; 2426 }; 2427 2428 pcie@14120000 { 2429 compatible = "nvidia,tegra194-pcie"; 2430 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2431 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2432 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2433 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2434 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2435 reg-names = "appl", "config", "atu_dma", "dbi"; 2436 2437 status = "disabled"; 2438 2439 #address-cells = <3>; 2440 #size-cells = <2>; 2441 device_type = "pci"; 2442 num-lanes = <1>; 2443 linux,pci-domain = <2>; 2444 2445 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2446 clock-names = "core"; 2447 2448 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2449 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2450 reset-names = "apb", "core"; 2451 2452 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2453 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2454 interrupt-names = "intr", "msi"; 2455 2456 #interrupt-cells = <1>; 2457 interrupt-map-mask = <0 0 0 0>; 2458 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2459 2460 nvidia,bpmp = <&bpmp 2>; 2461 2462 nvidia,aspm-cmrt-us = <60>; 2463 nvidia,aspm-pwr-on-t-us = <20>; 2464 nvidia,aspm-l0s-entrance-latency-us = <3>; 2465 2466 bus-range = <0x0 0xff>; 2467 2468 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2469 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2470 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2471 2472 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2473 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2474 interconnect-names = "dma-mem", "write"; 2475 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2476 iommu-map-mask = <0x0>; 2477 dma-coherent; 2478 }; 2479 2480 pcie@14140000 { 2481 compatible = "nvidia,tegra194-pcie"; 2482 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2483 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2484 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2485 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2486 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2487 reg-names = "appl", "config", "atu_dma", "dbi"; 2488 2489 status = "disabled"; 2490 2491 #address-cells = <3>; 2492 #size-cells = <2>; 2493 device_type = "pci"; 2494 num-lanes = <1>; 2495 linux,pci-domain = <3>; 2496 2497 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2498 clock-names = "core"; 2499 2500 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2501 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2502 reset-names = "apb", "core"; 2503 2504 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2505 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2506 interrupt-names = "intr", "msi"; 2507 2508 #interrupt-cells = <1>; 2509 interrupt-map-mask = <0 0 0 0>; 2510 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2511 2512 nvidia,bpmp = <&bpmp 3>; 2513 2514 nvidia,aspm-cmrt-us = <60>; 2515 nvidia,aspm-pwr-on-t-us = <20>; 2516 nvidia,aspm-l0s-entrance-latency-us = <3>; 2517 2518 bus-range = <0x0 0xff>; 2519 2520 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2521 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2522 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2523 2524 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2525 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2526 interconnect-names = "dma-mem", "write"; 2527 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2528 iommu-map-mask = <0x0>; 2529 dma-coherent; 2530 }; 2531 2532 pcie@14160000 { 2533 compatible = "nvidia,tegra194-pcie"; 2534 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2535 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2536 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2537 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2538 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2539 reg-names = "appl", "config", "atu_dma", "dbi"; 2540 2541 status = "disabled"; 2542 2543 #address-cells = <3>; 2544 #size-cells = <2>; 2545 device_type = "pci"; 2546 num-lanes = <4>; 2547 linux,pci-domain = <4>; 2548 2549 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2550 clock-names = "core"; 2551 2552 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2553 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2554 reset-names = "apb", "core"; 2555 2556 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2557 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2558 interrupt-names = "intr", "msi"; 2559 2560 #interrupt-cells = <1>; 2561 interrupt-map-mask = <0 0 0 0>; 2562 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2563 2564 nvidia,bpmp = <&bpmp 4>; 2565 2566 nvidia,aspm-cmrt-us = <60>; 2567 nvidia,aspm-pwr-on-t-us = <20>; 2568 nvidia,aspm-l0s-entrance-latency-us = <3>; 2569 2570 bus-range = <0x0 0xff>; 2571 2572 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2573 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2574 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2575 2576 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2577 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2578 interconnect-names = "dma-mem", "write"; 2579 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2580 iommu-map-mask = <0x0>; 2581 dma-coherent; 2582 }; 2583 2584 pcie-ep@14160000 { 2585 compatible = "nvidia,tegra194-pcie-ep"; 2586 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2587 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2588 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2589 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2590 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2591 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2592 2593 status = "disabled"; 2594 2595 num-lanes = <4>; 2596 num-ib-windows = <2>; 2597 num-ob-windows = <8>; 2598 2599 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2600 clock-names = "core"; 2601 2602 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2603 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2604 reset-names = "apb", "core"; 2605 2606 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2607 interrupt-names = "intr"; 2608 2609 nvidia,bpmp = <&bpmp 4>; 2610 2611 nvidia,aspm-cmrt-us = <60>; 2612 nvidia,aspm-pwr-on-t-us = <20>; 2613 nvidia,aspm-l0s-entrance-latency-us = <3>; 2614 2615 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2616 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2617 interconnect-names = "dma-mem", "write"; 2618 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2619 iommu-map-mask = <0x0>; 2620 dma-coherent; 2621 }; 2622 2623 pcie@14180000 { 2624 compatible = "nvidia,tegra194-pcie"; 2625 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2626 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2627 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2628 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2629 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2630 reg-names = "appl", "config", "atu_dma", "dbi"; 2631 2632 status = "disabled"; 2633 2634 #address-cells = <3>; 2635 #size-cells = <2>; 2636 device_type = "pci"; 2637 num-lanes = <8>; 2638 linux,pci-domain = <0>; 2639 2640 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2641 clock-names = "core"; 2642 2643 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2644 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2645 reset-names = "apb", "core"; 2646 2647 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2648 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2649 interrupt-names = "intr", "msi"; 2650 2651 #interrupt-cells = <1>; 2652 interrupt-map-mask = <0 0 0 0>; 2653 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2654 2655 nvidia,bpmp = <&bpmp 0>; 2656 2657 nvidia,aspm-cmrt-us = <60>; 2658 nvidia,aspm-pwr-on-t-us = <20>; 2659 nvidia,aspm-l0s-entrance-latency-us = <3>; 2660 2661 bus-range = <0x0 0xff>; 2662 2663 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2664 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2665 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2666 2667 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2668 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2669 interconnect-names = "dma-mem", "write"; 2670 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2671 iommu-map-mask = <0x0>; 2672 dma-coherent; 2673 }; 2674 2675 pcie-ep@14180000 { 2676 compatible = "nvidia,tegra194-pcie-ep"; 2677 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2678 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2679 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2680 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2681 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2682 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2683 2684 status = "disabled"; 2685 2686 num-lanes = <8>; 2687 num-ib-windows = <2>; 2688 num-ob-windows = <8>; 2689 2690 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2691 clock-names = "core"; 2692 2693 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2694 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2695 reset-names = "apb", "core"; 2696 2697 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2698 interrupt-names = "intr"; 2699 2700 nvidia,bpmp = <&bpmp 0>; 2701 2702 nvidia,aspm-cmrt-us = <60>; 2703 nvidia,aspm-pwr-on-t-us = <20>; 2704 nvidia,aspm-l0s-entrance-latency-us = <3>; 2705 2706 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2707 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2708 interconnect-names = "dma-mem", "write"; 2709 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2710 iommu-map-mask = <0x0>; 2711 dma-coherent; 2712 }; 2713 2714 pcie@141a0000 { 2715 compatible = "nvidia,tegra194-pcie"; 2716 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2717 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2718 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2719 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2720 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2721 reg-names = "appl", "config", "atu_dma", "dbi"; 2722 2723 status = "disabled"; 2724 2725 #address-cells = <3>; 2726 #size-cells = <2>; 2727 device_type = "pci"; 2728 num-lanes = <8>; 2729 linux,pci-domain = <5>; 2730 2731 pinctrl-names = "default"; 2732 pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>; 2733 2734 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2735 clock-names = "core"; 2736 2737 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2738 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2739 reset-names = "apb", "core"; 2740 2741 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2742 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2743 interrupt-names = "intr", "msi"; 2744 2745 nvidia,bpmp = <&bpmp 5>; 2746 2747 #interrupt-cells = <1>; 2748 interrupt-map-mask = <0 0 0 0>; 2749 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2750 2751 nvidia,aspm-cmrt-us = <60>; 2752 nvidia,aspm-pwr-on-t-us = <20>; 2753 nvidia,aspm-l0s-entrance-latency-us = <3>; 2754 2755 bus-range = <0x0 0xff>; 2756 2757 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2758 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2759 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2760 2761 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2762 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2763 interconnect-names = "dma-mem", "write"; 2764 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2765 iommu-map-mask = <0x0>; 2766 dma-coherent; 2767 }; 2768 2769 pcie-ep@141a0000 { 2770 compatible = "nvidia,tegra194-pcie-ep"; 2771 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2772 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2773 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2774 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2775 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2776 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2777 2778 status = "disabled"; 2779 2780 num-lanes = <8>; 2781 num-ib-windows = <2>; 2782 num-ob-windows = <8>; 2783 2784 pinctrl-names = "default"; 2785 pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>; 2786 2787 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2788 clock-names = "core"; 2789 2790 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2791 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2792 reset-names = "apb", "core"; 2793 2794 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2795 interrupt-names = "intr"; 2796 2797 nvidia,bpmp = <&bpmp 5>; 2798 2799 nvidia,aspm-cmrt-us = <60>; 2800 nvidia,aspm-pwr-on-t-us = <20>; 2801 nvidia,aspm-l0s-entrance-latency-us = <3>; 2802 2803 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2804 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2805 interconnect-names = "dma-mem", "write"; 2806 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2807 iommu-map-mask = <0x0>; 2808 dma-coherent; 2809 }; 2810 2811 gpu@17000000 { 2812 compatible = "nvidia,gv11b"; 2813 reg = <0x0 0x17000000 0x0 0x1000000>, 2814 <0x0 0x18000000 0x0 0x1000000>; 2815 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2816 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2817 interrupt-names = "stall", "nonstall"; 2818 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2819 <&bpmp TEGRA194_CLK_GPU_PWR>, 2820 <&bpmp TEGRA194_CLK_FUSE>; 2821 clock-names = "gpu", "pwr", "fuse"; 2822 resets = <&bpmp TEGRA194_RESET_GPU>; 2823 reset-names = "gpu"; 2824 dma-coherent; 2825 2826 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2827 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2828 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2829 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2830 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2831 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2832 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2833 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2834 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2835 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2836 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2837 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2838 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2839 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2840 "read-1", "read-1-hp", "write-1", 2841 "read-2", "read-2-hp", "write-2", 2842 "read-3", "read-3-hp", "write-3"; 2843 }; 2844 }; 2845 2846 sram@40000000 { 2847 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2848 reg = <0x0 0x40000000 0x0 0x50000>; 2849 2850 #address-cells = <1>; 2851 #size-cells = <1>; 2852 ranges = <0x0 0x0 0x40000000 0x50000>; 2853 2854 no-memory-wc; 2855 2856 cpu_bpmp_tx: sram@4e000 { 2857 reg = <0x4e000 0x1000>; 2858 label = "cpu-bpmp-tx"; 2859 pool; 2860 }; 2861 2862 cpu_bpmp_rx: sram@4f000 { 2863 reg = <0x4f000 0x1000>; 2864 label = "cpu-bpmp-rx"; 2865 pool; 2866 }; 2867 }; 2868 2869 bpmp: bpmp { 2870 compatible = "nvidia,tegra186-bpmp"; 2871 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2872 TEGRA_HSP_DB_MASTER_BPMP>; 2873 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2874 #clock-cells = <1>; 2875 #reset-cells = <1>; 2876 #power-domain-cells = <1>; 2877 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2878 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2879 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2880 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2881 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2882 iommus = <&smmu TEGRA194_SID_BPMP>; 2883 2884 bpmp_i2c: i2c { 2885 compatible = "nvidia,tegra186-bpmp-i2c"; 2886 nvidia,bpmp-bus-id = <5>; 2887 #address-cells = <1>; 2888 #size-cells = <0>; 2889 }; 2890 2891 bpmp_thermal: thermal { 2892 compatible = "nvidia,tegra186-bpmp-thermal"; 2893 #thermal-sensor-cells = <1>; 2894 }; 2895 }; 2896 2897 cpus { 2898 compatible = "nvidia,tegra194-ccplex"; 2899 nvidia,bpmp = <&bpmp>; 2900 #address-cells = <1>; 2901 #size-cells = <0>; 2902 2903 cpu0_0: cpu@0 { 2904 compatible = "nvidia,tegra194-carmel"; 2905 device_type = "cpu"; 2906 reg = <0x000>; 2907 enable-method = "psci"; 2908 i-cache-size = <131072>; 2909 i-cache-line-size = <64>; 2910 i-cache-sets = <512>; 2911 d-cache-size = <65536>; 2912 d-cache-line-size = <64>; 2913 d-cache-sets = <256>; 2914 next-level-cache = <&l2c_0>; 2915 }; 2916 2917 cpu0_1: cpu@1 { 2918 compatible = "nvidia,tegra194-carmel"; 2919 device_type = "cpu"; 2920 reg = <0x001>; 2921 enable-method = "psci"; 2922 i-cache-size = <131072>; 2923 i-cache-line-size = <64>; 2924 i-cache-sets = <512>; 2925 d-cache-size = <65536>; 2926 d-cache-line-size = <64>; 2927 d-cache-sets = <256>; 2928 next-level-cache = <&l2c_0>; 2929 }; 2930 2931 cpu1_0: cpu@100 { 2932 compatible = "nvidia,tegra194-carmel"; 2933 device_type = "cpu"; 2934 reg = <0x100>; 2935 enable-method = "psci"; 2936 i-cache-size = <131072>; 2937 i-cache-line-size = <64>; 2938 i-cache-sets = <512>; 2939 d-cache-size = <65536>; 2940 d-cache-line-size = <64>; 2941 d-cache-sets = <256>; 2942 next-level-cache = <&l2c_1>; 2943 }; 2944 2945 cpu1_1: cpu@101 { 2946 compatible = "nvidia,tegra194-carmel"; 2947 device_type = "cpu"; 2948 reg = <0x101>; 2949 enable-method = "psci"; 2950 i-cache-size = <131072>; 2951 i-cache-line-size = <64>; 2952 i-cache-sets = <512>; 2953 d-cache-size = <65536>; 2954 d-cache-line-size = <64>; 2955 d-cache-sets = <256>; 2956 next-level-cache = <&l2c_1>; 2957 }; 2958 2959 cpu2_0: cpu@200 { 2960 compatible = "nvidia,tegra194-carmel"; 2961 device_type = "cpu"; 2962 reg = <0x200>; 2963 enable-method = "psci"; 2964 i-cache-size = <131072>; 2965 i-cache-line-size = <64>; 2966 i-cache-sets = <512>; 2967 d-cache-size = <65536>; 2968 d-cache-line-size = <64>; 2969 d-cache-sets = <256>; 2970 next-level-cache = <&l2c_2>; 2971 }; 2972 2973 cpu2_1: cpu@201 { 2974 compatible = "nvidia,tegra194-carmel"; 2975 device_type = "cpu"; 2976 reg = <0x201>; 2977 enable-method = "psci"; 2978 i-cache-size = <131072>; 2979 i-cache-line-size = <64>; 2980 i-cache-sets = <512>; 2981 d-cache-size = <65536>; 2982 d-cache-line-size = <64>; 2983 d-cache-sets = <256>; 2984 next-level-cache = <&l2c_2>; 2985 }; 2986 2987 cpu3_0: cpu@300 { 2988 compatible = "nvidia,tegra194-carmel"; 2989 device_type = "cpu"; 2990 reg = <0x300>; 2991 enable-method = "psci"; 2992 i-cache-size = <131072>; 2993 i-cache-line-size = <64>; 2994 i-cache-sets = <512>; 2995 d-cache-size = <65536>; 2996 d-cache-line-size = <64>; 2997 d-cache-sets = <256>; 2998 next-level-cache = <&l2c_3>; 2999 }; 3000 3001 cpu3_1: cpu@301 { 3002 compatible = "nvidia,tegra194-carmel"; 3003 device_type = "cpu"; 3004 reg = <0x301>; 3005 enable-method = "psci"; 3006 i-cache-size = <131072>; 3007 i-cache-line-size = <64>; 3008 i-cache-sets = <512>; 3009 d-cache-size = <65536>; 3010 d-cache-line-size = <64>; 3011 d-cache-sets = <256>; 3012 next-level-cache = <&l2c_3>; 3013 }; 3014 3015 cpu-map { 3016 cluster0 { 3017 core0 { 3018 cpu = <&cpu0_0>; 3019 }; 3020 3021 core1 { 3022 cpu = <&cpu0_1>; 3023 }; 3024 }; 3025 3026 cluster1 { 3027 core0 { 3028 cpu = <&cpu1_0>; 3029 }; 3030 3031 core1 { 3032 cpu = <&cpu1_1>; 3033 }; 3034 }; 3035 3036 cluster2 { 3037 core0 { 3038 cpu = <&cpu2_0>; 3039 }; 3040 3041 core1 { 3042 cpu = <&cpu2_1>; 3043 }; 3044 }; 3045 3046 cluster3 { 3047 core0 { 3048 cpu = <&cpu3_0>; 3049 }; 3050 3051 core1 { 3052 cpu = <&cpu3_1>; 3053 }; 3054 }; 3055 }; 3056 3057 l2c_0: l2-cache0 { 3058 compatible = "cache"; 3059 cache-unified; 3060 cache-size = <2097152>; 3061 cache-line-size = <64>; 3062 cache-sets = <2048>; 3063 cache-level = <2>; 3064 next-level-cache = <&l3c>; 3065 }; 3066 3067 l2c_1: l2-cache1 { 3068 compatible = "cache"; 3069 cache-unified; 3070 cache-size = <2097152>; 3071 cache-line-size = <64>; 3072 cache-sets = <2048>; 3073 cache-level = <2>; 3074 next-level-cache = <&l3c>; 3075 }; 3076 3077 l2c_2: l2-cache2 { 3078 compatible = "cache"; 3079 cache-unified; 3080 cache-size = <2097152>; 3081 cache-line-size = <64>; 3082 cache-sets = <2048>; 3083 cache-level = <2>; 3084 next-level-cache = <&l3c>; 3085 }; 3086 3087 l2c_3: l2-cache3 { 3088 compatible = "cache"; 3089 cache-unified; 3090 cache-size = <2097152>; 3091 cache-line-size = <64>; 3092 cache-sets = <2048>; 3093 cache-level = <2>; 3094 next-level-cache = <&l3c>; 3095 }; 3096 3097 l3c: l3-cache { 3098 compatible = "cache"; 3099 cache-unified; 3100 cache-size = <4194304>; 3101 cache-line-size = <64>; 3102 cache-level = <3>; 3103 cache-sets = <4096>; 3104 }; 3105 }; 3106 3107 pmu { 3108 compatible = "nvidia,carmel-pmu"; 3109 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 3117 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 3118 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 3119 }; 3120 3121 psci { 3122 compatible = "arm,psci-1.0"; 3123 status = "okay"; 3124 method = "smc"; 3125 }; 3126 3127 tcu: serial { 3128 compatible = "nvidia,tegra194-tcu"; 3129 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3130 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3131 mbox-names = "rx", "tx"; 3132 }; 3133 3134 sound { 3135 status = "disabled"; 3136 3137 clocks = <&bpmp TEGRA194_CLK_PLLA>, 3138 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3139 clock-names = "pll_a", "plla_out0"; 3140 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 3141 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 3142 <&bpmp TEGRA194_CLK_AUD_MCLK>; 3143 assigned-clock-parents = <0>, 3144 <&bpmp TEGRA194_CLK_PLLA>, 3145 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3146 /* 3147 * PLLA supports dynamic ramp. Below initial rate is chosen 3148 * for this to work and oscillate between base rates required 3149 * for 8x and 11.025x sample rate streams. 3150 */ 3151 assigned-clock-rates = <258000000>; 3152 }; 3153 3154 thermal-zones { 3155 cpu-thermal { 3156 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3157 status = "disabled"; 3158 }; 3159 3160 gpu-thermal { 3161 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3162 status = "disabled"; 3163 }; 3164 3165 aux-thermal { 3166 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3167 status = "disabled"; 3168 }; 3169 3170 pllx-thermal { 3171 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3172 status = "disabled"; 3173 }; 3174 3175 ao-thermal { 3176 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3177 status = "disabled"; 3178 }; 3179 3180 tj-thermal { 3181 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3182 status = "disabled"; 3183 }; 3184 }; 3185 3186 timer { 3187 compatible = "arm,armv8-timer"; 3188 interrupts = <GIC_PPI 13 3189 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3190 <GIC_PPI 14 3191 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3192 <GIC_PPI 11 3193 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3194 <GIC_PPI 10 3195 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3196 interrupt-parent = <&gic>; 3197 always-on; 3198 }; 3199}; 3200