1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x0 0x0 0x0 0x40000000>; 25 26 apbmisc: misc@100000 { 27 compatible = "nvidia,tegra194-misc"; 28 reg = <0x00100000 0xf000>, 29 <0x0010f000 0x1000>; 30 }; 31 32 gpio: gpio@2200000 { 33 compatible = "nvidia,tegra194-gpio"; 34 reg-names = "security", "gpio"; 35 reg = <0x2200000 0x10000>, 36 <0x2210000 0x10000>; 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85 #interrupt-cells = <2>; 86 interrupt-controller; 87 #gpio-cells = <2>; 88 gpio-controller; 89 }; 90 91 cbb-noc@2300000 { 92 compatible = "nvidia,tegra194-cbb-noc"; 93 reg = <0x02300000 0x1000>; 94 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 96 nvidia,axi2apb = <&axi2apb>; 97 nvidia,apbmisc = <&apbmisc>; 98 status = "okay"; 99 }; 100 101 axi2apb: axi2apb@2390000 { 102 compatible = "nvidia,tegra194-axi2apb"; 103 reg = <0x2390000 0x1000>, 104 <0x23a0000 0x1000>, 105 <0x23b0000 0x1000>, 106 <0x23c0000 0x1000>, 107 <0x23d0000 0x1000>, 108 <0x23e0000 0x1000>; 109 status = "okay"; 110 }; 111 112 ethernet@2490000 { 113 compatible = "nvidia,tegra194-eqos", 114 "nvidia,tegra186-eqos", 115 "snps,dwc-qos-ethernet-4.10"; 116 reg = <0x02490000 0x10000>; 117 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 118 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 119 <&bpmp TEGRA194_CLK_EQOS_AXI>, 120 <&bpmp TEGRA194_CLK_EQOS_RX>, 121 <&bpmp TEGRA194_CLK_EQOS_TX>, 122 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 123 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 124 resets = <&bpmp TEGRA194_RESET_EQOS>; 125 reset-names = "eqos"; 126 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 127 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 128 interconnect-names = "dma-mem", "write"; 129 iommus = <&smmu TEGRA194_SID_EQOS>; 130 status = "disabled"; 131 132 snps,write-requests = <1>; 133 snps,read-requests = <3>; 134 snps,burst-map = <0x7>; 135 snps,txpbl = <16>; 136 snps,rxpbl = <8>; 137 }; 138 139 gpcdma: dma-controller@2600000 { 140 compatible = "nvidia,tegra194-gpcdma", 141 "nvidia,tegra186-gpcdma"; 142 reg = <0x2600000 0x210000>; 143 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 144 reset-names = "gpcdma"; 145 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 176 #dma-cells = <1>; 177 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 178 dma-coherent; 179 status = "okay"; 180 }; 181 182 aconnect@2900000 { 183 compatible = "nvidia,tegra194-aconnect", 184 "nvidia,tegra210-aconnect"; 185 clocks = <&bpmp TEGRA194_CLK_APE>, 186 <&bpmp TEGRA194_CLK_APB2APE>; 187 clock-names = "ape", "apb2ape"; 188 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 ranges = <0x02900000 0x02900000 0x200000>; 192 status = "disabled"; 193 194 adma: dma-controller@2930000 { 195 compatible = "nvidia,tegra194-adma", 196 "nvidia,tegra186-adma"; 197 reg = <0x02930000 0x20000>; 198 interrupt-parent = <&agic>; 199 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 231 #dma-cells = <1>; 232 clocks = <&bpmp TEGRA194_CLK_AHUB>; 233 clock-names = "d_audio"; 234 status = "disabled"; 235 }; 236 237 agic: interrupt-controller@2a40000 { 238 compatible = "nvidia,tegra194-agic", 239 "nvidia,tegra210-agic"; 240 #interrupt-cells = <3>; 241 interrupt-controller; 242 reg = <0x02a41000 0x1000>, 243 <0x02a42000 0x2000>; 244 interrupts = <GIC_SPI 145 245 (GIC_CPU_MASK_SIMPLE(4) | 246 IRQ_TYPE_LEVEL_HIGH)>; 247 clocks = <&bpmp TEGRA194_CLK_APE>; 248 clock-names = "clk"; 249 status = "disabled"; 250 }; 251 252 tegra_ahub: ahub@2900800 { 253 compatible = "nvidia,tegra194-ahub", 254 "nvidia,tegra186-ahub"; 255 reg = <0x02900800 0x800>; 256 clocks = <&bpmp TEGRA194_CLK_AHUB>; 257 clock-names = "ahub"; 258 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 259 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 ranges = <0x02900800 0x02900800 0x11800>; 263 status = "disabled"; 264 265 tegra_admaif: admaif@290f000 { 266 compatible = "nvidia,tegra194-admaif", 267 "nvidia,tegra186-admaif"; 268 reg = <0x0290f000 0x1000>; 269 dmas = <&adma 1>, <&adma 1>, 270 <&adma 2>, <&adma 2>, 271 <&adma 3>, <&adma 3>, 272 <&adma 4>, <&adma 4>, 273 <&adma 5>, <&adma 5>, 274 <&adma 6>, <&adma 6>, 275 <&adma 7>, <&adma 7>, 276 <&adma 8>, <&adma 8>, 277 <&adma 9>, <&adma 9>, 278 <&adma 10>, <&adma 10>, 279 <&adma 11>, <&adma 11>, 280 <&adma 12>, <&adma 12>, 281 <&adma 13>, <&adma 13>, 282 <&adma 14>, <&adma 14>, 283 <&adma 15>, <&adma 15>, 284 <&adma 16>, <&adma 16>, 285 <&adma 17>, <&adma 17>, 286 <&adma 18>, <&adma 18>, 287 <&adma 19>, <&adma 19>, 288 <&adma 20>, <&adma 20>; 289 dma-names = "rx1", "tx1", 290 "rx2", "tx2", 291 "rx3", "tx3", 292 "rx4", "tx4", 293 "rx5", "tx5", 294 "rx6", "tx6", 295 "rx7", "tx7", 296 "rx8", "tx8", 297 "rx9", "tx9", 298 "rx10", "tx10", 299 "rx11", "tx11", 300 "rx12", "tx12", 301 "rx13", "tx13", 302 "rx14", "tx14", 303 "rx15", "tx15", 304 "rx16", "tx16", 305 "rx17", "tx17", 306 "rx18", "tx18", 307 "rx19", "tx19", 308 "rx20", "tx20"; 309 status = "disabled"; 310 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 311 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 312 interconnect-names = "dma-mem", "write"; 313 iommus = <&smmu TEGRA194_SID_APE>; 314 }; 315 316 tegra_i2s1: i2s@2901000 { 317 compatible = "nvidia,tegra194-i2s", 318 "nvidia,tegra210-i2s"; 319 reg = <0x2901000 0x100>; 320 clocks = <&bpmp TEGRA194_CLK_I2S1>, 321 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 322 clock-names = "i2s", "sync_input"; 323 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 324 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 325 assigned-clock-rates = <1536000>; 326 sound-name-prefix = "I2S1"; 327 status = "disabled"; 328 }; 329 330 tegra_i2s2: i2s@2901100 { 331 compatible = "nvidia,tegra194-i2s", 332 "nvidia,tegra210-i2s"; 333 reg = <0x2901100 0x100>; 334 clocks = <&bpmp TEGRA194_CLK_I2S2>, 335 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 336 clock-names = "i2s", "sync_input"; 337 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 338 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 339 assigned-clock-rates = <1536000>; 340 sound-name-prefix = "I2S2"; 341 status = "disabled"; 342 }; 343 344 tegra_i2s3: i2s@2901200 { 345 compatible = "nvidia,tegra194-i2s", 346 "nvidia,tegra210-i2s"; 347 reg = <0x2901200 0x100>; 348 clocks = <&bpmp TEGRA194_CLK_I2S3>, 349 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 350 clock-names = "i2s", "sync_input"; 351 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 352 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 353 assigned-clock-rates = <1536000>; 354 sound-name-prefix = "I2S3"; 355 status = "disabled"; 356 }; 357 358 tegra_i2s4: i2s@2901300 { 359 compatible = "nvidia,tegra194-i2s", 360 "nvidia,tegra210-i2s"; 361 reg = <0x2901300 0x100>; 362 clocks = <&bpmp TEGRA194_CLK_I2S4>, 363 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 364 clock-names = "i2s", "sync_input"; 365 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 366 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 367 assigned-clock-rates = <1536000>; 368 sound-name-prefix = "I2S4"; 369 status = "disabled"; 370 }; 371 372 tegra_i2s5: i2s@2901400 { 373 compatible = "nvidia,tegra194-i2s", 374 "nvidia,tegra210-i2s"; 375 reg = <0x2901400 0x100>; 376 clocks = <&bpmp TEGRA194_CLK_I2S5>, 377 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 378 clock-names = "i2s", "sync_input"; 379 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 380 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 381 assigned-clock-rates = <1536000>; 382 sound-name-prefix = "I2S5"; 383 status = "disabled"; 384 }; 385 386 tegra_i2s6: i2s@2901500 { 387 compatible = "nvidia,tegra194-i2s", 388 "nvidia,tegra210-i2s"; 389 reg = <0x2901500 0x100>; 390 clocks = <&bpmp TEGRA194_CLK_I2S6>, 391 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 392 clock-names = "i2s", "sync_input"; 393 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 394 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 395 assigned-clock-rates = <1536000>; 396 sound-name-prefix = "I2S6"; 397 status = "disabled"; 398 }; 399 400 tegra_dmic1: dmic@2904000 { 401 compatible = "nvidia,tegra194-dmic", 402 "nvidia,tegra210-dmic"; 403 reg = <0x2904000 0x100>; 404 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 405 clock-names = "dmic"; 406 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 407 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 408 assigned-clock-rates = <3072000>; 409 sound-name-prefix = "DMIC1"; 410 status = "disabled"; 411 }; 412 413 tegra_dmic2: dmic@2904100 { 414 compatible = "nvidia,tegra194-dmic", 415 "nvidia,tegra210-dmic"; 416 reg = <0x2904100 0x100>; 417 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 418 clock-names = "dmic"; 419 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 420 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 421 assigned-clock-rates = <3072000>; 422 sound-name-prefix = "DMIC2"; 423 status = "disabled"; 424 }; 425 426 tegra_dmic3: dmic@2904200 { 427 compatible = "nvidia,tegra194-dmic", 428 "nvidia,tegra210-dmic"; 429 reg = <0x2904200 0x100>; 430 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 431 clock-names = "dmic"; 432 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 433 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 434 assigned-clock-rates = <3072000>; 435 sound-name-prefix = "DMIC3"; 436 status = "disabled"; 437 }; 438 439 tegra_dmic4: dmic@2904300 { 440 compatible = "nvidia,tegra194-dmic", 441 "nvidia,tegra210-dmic"; 442 reg = <0x2904300 0x100>; 443 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 444 clock-names = "dmic"; 445 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 446 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 447 assigned-clock-rates = <3072000>; 448 sound-name-prefix = "DMIC4"; 449 status = "disabled"; 450 }; 451 452 tegra_dspk1: dspk@2905000 { 453 compatible = "nvidia,tegra194-dspk", 454 "nvidia,tegra186-dspk"; 455 reg = <0x2905000 0x100>; 456 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 457 clock-names = "dspk"; 458 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 459 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 460 assigned-clock-rates = <12288000>; 461 sound-name-prefix = "DSPK1"; 462 status = "disabled"; 463 }; 464 465 tegra_dspk2: dspk@2905100 { 466 compatible = "nvidia,tegra194-dspk", 467 "nvidia,tegra186-dspk"; 468 reg = <0x2905100 0x100>; 469 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 470 clock-names = "dspk"; 471 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 472 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 473 assigned-clock-rates = <12288000>; 474 sound-name-prefix = "DSPK2"; 475 status = "disabled"; 476 }; 477 478 tegra_sfc1: sfc@2902000 { 479 compatible = "nvidia,tegra194-sfc", 480 "nvidia,tegra210-sfc"; 481 reg = <0x2902000 0x200>; 482 sound-name-prefix = "SFC1"; 483 status = "disabled"; 484 }; 485 486 tegra_sfc2: sfc@2902200 { 487 compatible = "nvidia,tegra194-sfc", 488 "nvidia,tegra210-sfc"; 489 reg = <0x2902200 0x200>; 490 sound-name-prefix = "SFC2"; 491 status = "disabled"; 492 }; 493 494 tegra_sfc3: sfc@2902400 { 495 compatible = "nvidia,tegra194-sfc", 496 "nvidia,tegra210-sfc"; 497 reg = <0x2902400 0x200>; 498 sound-name-prefix = "SFC3"; 499 status = "disabled"; 500 }; 501 502 tegra_sfc4: sfc@2902600 { 503 compatible = "nvidia,tegra194-sfc", 504 "nvidia,tegra210-sfc"; 505 reg = <0x2902600 0x200>; 506 sound-name-prefix = "SFC4"; 507 status = "disabled"; 508 }; 509 510 tegra_mvc1: mvc@290a000 { 511 compatible = "nvidia,tegra194-mvc", 512 "nvidia,tegra210-mvc"; 513 reg = <0x290a000 0x200>; 514 sound-name-prefix = "MVC1"; 515 status = "disabled"; 516 }; 517 518 tegra_mvc2: mvc@290a200 { 519 compatible = "nvidia,tegra194-mvc", 520 "nvidia,tegra210-mvc"; 521 reg = <0x290a200 0x200>; 522 sound-name-prefix = "MVC2"; 523 status = "disabled"; 524 }; 525 526 tegra_amx1: amx@2903000 { 527 compatible = "nvidia,tegra194-amx"; 528 reg = <0x2903000 0x100>; 529 sound-name-prefix = "AMX1"; 530 status = "disabled"; 531 }; 532 533 tegra_amx2: amx@2903100 { 534 compatible = "nvidia,tegra194-amx"; 535 reg = <0x2903100 0x100>; 536 sound-name-prefix = "AMX2"; 537 status = "disabled"; 538 }; 539 540 tegra_amx3: amx@2903200 { 541 compatible = "nvidia,tegra194-amx"; 542 reg = <0x2903200 0x100>; 543 sound-name-prefix = "AMX3"; 544 status = "disabled"; 545 }; 546 547 tegra_amx4: amx@2903300 { 548 compatible = "nvidia,tegra194-amx"; 549 reg = <0x2903300 0x100>; 550 sound-name-prefix = "AMX4"; 551 status = "disabled"; 552 }; 553 554 tegra_adx1: adx@2903800 { 555 compatible = "nvidia,tegra194-adx", 556 "nvidia,tegra210-adx"; 557 reg = <0x2903800 0x100>; 558 sound-name-prefix = "ADX1"; 559 status = "disabled"; 560 }; 561 562 tegra_adx2: adx@2903900 { 563 compatible = "nvidia,tegra194-adx", 564 "nvidia,tegra210-adx"; 565 reg = <0x2903900 0x100>; 566 sound-name-prefix = "ADX2"; 567 status = "disabled"; 568 }; 569 570 tegra_adx3: adx@2903a00 { 571 compatible = "nvidia,tegra194-adx", 572 "nvidia,tegra210-adx"; 573 reg = <0x2903a00 0x100>; 574 sound-name-prefix = "ADX3"; 575 status = "disabled"; 576 }; 577 578 tegra_adx4: adx@2903b00 { 579 compatible = "nvidia,tegra194-adx", 580 "nvidia,tegra210-adx"; 581 reg = <0x2903b00 0x100>; 582 sound-name-prefix = "ADX4"; 583 status = "disabled"; 584 }; 585 586 tegra_ope1: processing-engine@2908000 { 587 compatible = "nvidia,tegra194-ope", 588 "nvidia,tegra210-ope"; 589 reg = <0x2908000 0x100>; 590 #address-cells = <1>; 591 #size-cells = <1>; 592 ranges; 593 sound-name-prefix = "OPE1"; 594 status = "disabled"; 595 596 equalizer@2908100 { 597 compatible = "nvidia,tegra194-peq", 598 "nvidia,tegra210-peq"; 599 reg = <0x2908100 0x100>; 600 }; 601 602 dynamic-range-compressor@2908200 { 603 compatible = "nvidia,tegra194-mbdrc", 604 "nvidia,tegra210-mbdrc"; 605 reg = <0x2908200 0x200>; 606 }; 607 }; 608 609 tegra_amixer: amixer@290bb00 { 610 compatible = "nvidia,tegra194-amixer", 611 "nvidia,tegra210-amixer"; 612 reg = <0x290bb00 0x800>; 613 sound-name-prefix = "MIXER1"; 614 status = "disabled"; 615 }; 616 617 tegra_asrc: asrc@2910000 { 618 compatible = "nvidia,tegra194-asrc", 619 "nvidia,tegra186-asrc"; 620 reg = <0x2910000 0x2000>; 621 sound-name-prefix = "ASRC1"; 622 status = "disabled"; 623 }; 624 }; 625 }; 626 627 pinmux: pinmux@2430000 { 628 compatible = "nvidia,tegra194-pinmux"; 629 reg = <0x2430000 0x17000>, 630 <0xc300000 0x4000>; 631 632 status = "okay"; 633 634 pex_rst_c5_out_state: pex_rst_c5_out { 635 pex_rst { 636 nvidia,pins = "pex_l5_rst_n_pgg1"; 637 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 638 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 639 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 640 nvidia,tristate = <TEGRA_PIN_DISABLE>; 641 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 642 }; 643 }; 644 645 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 646 clkreq { 647 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 648 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 649 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 650 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 651 nvidia,tristate = <TEGRA_PIN_DISABLE>; 652 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 653 }; 654 }; 655 }; 656 657 mc: memory-controller@2c00000 { 658 compatible = "nvidia,tegra194-mc"; 659 reg = <0x02c00000 0x10000>, /* MC-SID */ 660 <0x02c10000 0x10000>, /* MC Broadcast*/ 661 <0x02c20000 0x10000>, /* MC0 */ 662 <0x02c30000 0x10000>, /* MC1 */ 663 <0x02c40000 0x10000>, /* MC2 */ 664 <0x02c50000 0x10000>, /* MC3 */ 665 <0x02b80000 0x10000>, /* MC4 */ 666 <0x02b90000 0x10000>, /* MC5 */ 667 <0x02ba0000 0x10000>, /* MC6 */ 668 <0x02bb0000 0x10000>, /* MC7 */ 669 <0x01700000 0x10000>, /* MC8 */ 670 <0x01710000 0x10000>, /* MC9 */ 671 <0x01720000 0x10000>, /* MC10 */ 672 <0x01730000 0x10000>, /* MC11 */ 673 <0x01740000 0x10000>, /* MC12 */ 674 <0x01750000 0x10000>, /* MC13 */ 675 <0x01760000 0x10000>, /* MC14 */ 676 <0x01770000 0x10000>; /* MC15 */ 677 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 678 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 679 "ch11", "ch12", "ch13", "ch14", "ch15"; 680 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 681 #interconnect-cells = <1>; 682 status = "disabled"; 683 684 #address-cells = <2>; 685 #size-cells = <2>; 686 687 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 688 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 689 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 690 691 /* 692 * Bit 39 of addresses passing through the memory 693 * controller selects the XBAR format used when memory 694 * is accessed. This is used to transparently access 695 * memory in the XBAR format used by the discrete GPU 696 * (bit 39 set) or Tegra (bit 39 clear). 697 * 698 * As a consequence, the operating system must ensure 699 * that bit 39 is never used implicitly, for example 700 * via an I/O virtual address mapping of an IOMMU. If 701 * devices require access to the XBAR switch, their 702 * drivers must set this bit explicitly. 703 * 704 * Limit the DMA range for memory clients to [38:0]. 705 */ 706 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 707 708 emc: external-memory-controller@2c60000 { 709 compatible = "nvidia,tegra194-emc"; 710 reg = <0x0 0x02c60000 0x0 0x90000>, 711 <0x0 0x01780000 0x0 0x80000>; 712 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&bpmp TEGRA194_CLK_EMC>; 714 clock-names = "emc"; 715 716 #interconnect-cells = <0>; 717 718 nvidia,bpmp = <&bpmp>; 719 }; 720 }; 721 722 timer@3010000 { 723 compatible = "nvidia,tegra186-timer"; 724 reg = <0x03010000 0x000e0000>; 725 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 735 status = "okay"; 736 }; 737 738 uarta: serial@3100000 { 739 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 740 reg = <0x03100000 0x40>; 741 reg-shift = <2>; 742 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&bpmp TEGRA194_CLK_UARTA>; 744 clock-names = "serial"; 745 resets = <&bpmp TEGRA194_RESET_UARTA>; 746 reset-names = "serial"; 747 status = "disabled"; 748 }; 749 750 uartb: serial@3110000 { 751 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 752 reg = <0x03110000 0x40>; 753 reg-shift = <2>; 754 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&bpmp TEGRA194_CLK_UARTB>; 756 clock-names = "serial"; 757 resets = <&bpmp TEGRA194_RESET_UARTB>; 758 reset-names = "serial"; 759 status = "disabled"; 760 }; 761 762 uartd: serial@3130000 { 763 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 764 reg = <0x03130000 0x40>; 765 reg-shift = <2>; 766 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&bpmp TEGRA194_CLK_UARTD>; 768 clock-names = "serial"; 769 resets = <&bpmp TEGRA194_RESET_UARTD>; 770 reset-names = "serial"; 771 status = "disabled"; 772 }; 773 774 uarte: serial@3140000 { 775 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 776 reg = <0x03140000 0x40>; 777 reg-shift = <2>; 778 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&bpmp TEGRA194_CLK_UARTE>; 780 clock-names = "serial"; 781 resets = <&bpmp TEGRA194_RESET_UARTE>; 782 reset-names = "serial"; 783 status = "disabled"; 784 }; 785 786 uartf: serial@3150000 { 787 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 788 reg = <0x03150000 0x40>; 789 reg-shift = <2>; 790 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&bpmp TEGRA194_CLK_UARTF>; 792 clock-names = "serial"; 793 resets = <&bpmp TEGRA194_RESET_UARTF>; 794 reset-names = "serial"; 795 status = "disabled"; 796 }; 797 798 gen1_i2c: i2c@3160000 { 799 compatible = "nvidia,tegra194-i2c"; 800 reg = <0x03160000 0x10000>; 801 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 clocks = <&bpmp TEGRA194_CLK_I2C1>; 805 clock-names = "div-clk"; 806 resets = <&bpmp TEGRA194_RESET_I2C1>; 807 reset-names = "i2c"; 808 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 809 dma-coherent; 810 dmas = <&gpcdma 21>, <&gpcdma 21>; 811 dma-names = "rx", "tx"; 812 status = "disabled"; 813 }; 814 815 uarth: serial@3170000 { 816 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 817 reg = <0x03170000 0x40>; 818 reg-shift = <2>; 819 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&bpmp TEGRA194_CLK_UARTH>; 821 clock-names = "serial"; 822 resets = <&bpmp TEGRA194_RESET_UARTH>; 823 reset-names = "serial"; 824 status = "disabled"; 825 }; 826 827 cam_i2c: i2c@3180000 { 828 compatible = "nvidia,tegra194-i2c"; 829 reg = <0x03180000 0x10000>; 830 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 clocks = <&bpmp TEGRA194_CLK_I2C3>; 834 clock-names = "div-clk"; 835 resets = <&bpmp TEGRA194_RESET_I2C3>; 836 reset-names = "i2c"; 837 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 838 dma-coherent; 839 dmas = <&gpcdma 23>, <&gpcdma 23>; 840 dma-names = "rx", "tx"; 841 status = "disabled"; 842 }; 843 844 /* shares pads with dpaux1 */ 845 dp_aux_ch1_i2c: i2c@3190000 { 846 compatible = "nvidia,tegra194-i2c"; 847 reg = <0x03190000 0x10000>; 848 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 clocks = <&bpmp TEGRA194_CLK_I2C4>; 852 clock-names = "div-clk"; 853 resets = <&bpmp TEGRA194_RESET_I2C4>; 854 reset-names = "i2c"; 855 pinctrl-0 = <&state_dpaux1_i2c>; 856 pinctrl-1 = <&state_dpaux1_off>; 857 pinctrl-names = "default", "idle"; 858 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 859 dma-coherent; 860 dmas = <&gpcdma 26>, <&gpcdma 26>; 861 dma-names = "rx", "tx"; 862 status = "disabled"; 863 }; 864 865 /* shares pads with dpaux0 */ 866 dp_aux_ch0_i2c: i2c@31b0000 { 867 compatible = "nvidia,tegra194-i2c"; 868 reg = <0x031b0000 0x10000>; 869 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 clocks = <&bpmp TEGRA194_CLK_I2C6>; 873 clock-names = "div-clk"; 874 resets = <&bpmp TEGRA194_RESET_I2C6>; 875 reset-names = "i2c"; 876 pinctrl-0 = <&state_dpaux0_i2c>; 877 pinctrl-1 = <&state_dpaux0_off>; 878 pinctrl-names = "default", "idle"; 879 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 880 dma-coherent; 881 dmas = <&gpcdma 30>, <&gpcdma 30>; 882 dma-names = "rx", "tx"; 883 status = "disabled"; 884 }; 885 886 /* shares pads with dpaux2 */ 887 dp_aux_ch2_i2c: i2c@31c0000 { 888 compatible = "nvidia,tegra194-i2c"; 889 reg = <0x031c0000 0x10000>; 890 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 clocks = <&bpmp TEGRA194_CLK_I2C7>; 894 clock-names = "div-clk"; 895 resets = <&bpmp TEGRA194_RESET_I2C7>; 896 reset-names = "i2c"; 897 pinctrl-0 = <&state_dpaux2_i2c>; 898 pinctrl-1 = <&state_dpaux2_off>; 899 pinctrl-names = "default", "idle"; 900 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 901 dma-coherent; 902 dmas = <&gpcdma 27>, <&gpcdma 27>; 903 dma-names = "rx", "tx"; 904 status = "disabled"; 905 }; 906 907 /* shares pads with dpaux3 */ 908 dp_aux_ch3_i2c: i2c@31e0000 { 909 compatible = "nvidia,tegra194-i2c"; 910 reg = <0x031e0000 0x10000>; 911 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 clocks = <&bpmp TEGRA194_CLK_I2C9>; 915 clock-names = "div-clk"; 916 resets = <&bpmp TEGRA194_RESET_I2C9>; 917 reset-names = "i2c"; 918 pinctrl-0 = <&state_dpaux3_i2c>; 919 pinctrl-1 = <&state_dpaux3_off>; 920 pinctrl-names = "default", "idle"; 921 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 922 dma-coherent; 923 dmas = <&gpcdma 31>, <&gpcdma 31>; 924 dma-names = "rx", "tx"; 925 status = "disabled"; 926 }; 927 928 spi@3270000 { 929 compatible = "nvidia,tegra194-qspi"; 930 reg = <0x3270000 0x1000>; 931 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 935 <&bpmp TEGRA194_CLK_QSPI0_PM>; 936 clock-names = "qspi", "qspi_out"; 937 resets = <&bpmp TEGRA194_RESET_QSPI0>; 938 reset-names = "qspi"; 939 status = "disabled"; 940 }; 941 942 spi@3300000 { 943 compatible = "nvidia,tegra194-qspi"; 944 reg = <0x3300000 0x1000>; 945 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 949 <&bpmp TEGRA194_CLK_QSPI1_PM>; 950 clock-names = "qspi", "qspi_out"; 951 resets = <&bpmp TEGRA194_RESET_QSPI1>; 952 reset-names = "qspi"; 953 status = "disabled"; 954 }; 955 956 pwm1: pwm@3280000 { 957 compatible = "nvidia,tegra194-pwm", 958 "nvidia,tegra186-pwm"; 959 reg = <0x3280000 0x10000>; 960 clocks = <&bpmp TEGRA194_CLK_PWM1>; 961 resets = <&bpmp TEGRA194_RESET_PWM1>; 962 reset-names = "pwm"; 963 status = "disabled"; 964 #pwm-cells = <2>; 965 }; 966 967 pwm2: pwm@3290000 { 968 compatible = "nvidia,tegra194-pwm", 969 "nvidia,tegra186-pwm"; 970 reg = <0x3290000 0x10000>; 971 clocks = <&bpmp TEGRA194_CLK_PWM2>; 972 resets = <&bpmp TEGRA194_RESET_PWM2>; 973 reset-names = "pwm"; 974 status = "disabled"; 975 #pwm-cells = <2>; 976 }; 977 978 pwm3: pwm@32a0000 { 979 compatible = "nvidia,tegra194-pwm", 980 "nvidia,tegra186-pwm"; 981 reg = <0x32a0000 0x10000>; 982 clocks = <&bpmp TEGRA194_CLK_PWM3>; 983 resets = <&bpmp TEGRA194_RESET_PWM3>; 984 reset-names = "pwm"; 985 status = "disabled"; 986 #pwm-cells = <2>; 987 }; 988 989 pwm5: pwm@32c0000 { 990 compatible = "nvidia,tegra194-pwm", 991 "nvidia,tegra186-pwm"; 992 reg = <0x32c0000 0x10000>; 993 clocks = <&bpmp TEGRA194_CLK_PWM5>; 994 resets = <&bpmp TEGRA194_RESET_PWM5>; 995 reset-names = "pwm"; 996 status = "disabled"; 997 #pwm-cells = <2>; 998 }; 999 1000 pwm6: pwm@32d0000 { 1001 compatible = "nvidia,tegra194-pwm", 1002 "nvidia,tegra186-pwm"; 1003 reg = <0x32d0000 0x10000>; 1004 clocks = <&bpmp TEGRA194_CLK_PWM6>; 1005 resets = <&bpmp TEGRA194_RESET_PWM6>; 1006 reset-names = "pwm"; 1007 status = "disabled"; 1008 #pwm-cells = <2>; 1009 }; 1010 1011 pwm7: pwm@32e0000 { 1012 compatible = "nvidia,tegra194-pwm", 1013 "nvidia,tegra186-pwm"; 1014 reg = <0x32e0000 0x10000>; 1015 clocks = <&bpmp TEGRA194_CLK_PWM7>; 1016 resets = <&bpmp TEGRA194_RESET_PWM7>; 1017 reset-names = "pwm"; 1018 status = "disabled"; 1019 #pwm-cells = <2>; 1020 }; 1021 1022 pwm8: pwm@32f0000 { 1023 compatible = "nvidia,tegra194-pwm", 1024 "nvidia,tegra186-pwm"; 1025 reg = <0x32f0000 0x10000>; 1026 clocks = <&bpmp TEGRA194_CLK_PWM8>; 1027 resets = <&bpmp TEGRA194_RESET_PWM8>; 1028 reset-names = "pwm"; 1029 status = "disabled"; 1030 #pwm-cells = <2>; 1031 }; 1032 1033 sdmmc1: mmc@3400000 { 1034 compatible = "nvidia,tegra194-sdhci"; 1035 reg = <0x03400000 0x10000>; 1036 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1038 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1039 clock-names = "sdhci", "tmclk"; 1040 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1041 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1042 assigned-clock-parents = 1043 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1044 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1045 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 1046 reset-names = "sdhci"; 1047 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1048 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1049 interconnect-names = "dma-mem", "write"; 1050 iommus = <&smmu TEGRA194_SID_SDMMC1>; 1051 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1052 pinctrl-0 = <&sdmmc1_3v3>; 1053 pinctrl-1 = <&sdmmc1_1v8>; 1054 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 1055 <0x07>; 1056 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1057 <0x07>; 1058 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1059 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1060 <0x07>; 1061 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1062 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1063 nvidia,default-tap = <0x9>; 1064 nvidia,default-trim = <0x5>; 1065 sd-uhs-sdr25; 1066 sd-uhs-sdr50; 1067 sd-uhs-ddr50; 1068 sd-uhs-sdr104; 1069 status = "disabled"; 1070 }; 1071 1072 sdmmc3: mmc@3440000 { 1073 compatible = "nvidia,tegra194-sdhci"; 1074 reg = <0x03440000 0x10000>; 1075 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1076 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1077 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1078 clock-names = "sdhci", "tmclk"; 1079 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1080 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1081 assigned-clock-parents = 1082 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1083 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1084 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1085 reset-names = "sdhci"; 1086 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1087 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1088 interconnect-names = "dma-mem", "write"; 1089 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1090 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1091 pinctrl-0 = <&sdmmc3_3v3>; 1092 pinctrl-1 = <&sdmmc3_1v8>; 1093 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1094 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1095 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1096 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1097 <0x07>; 1098 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1099 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1100 <0x07>; 1101 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1102 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1103 nvidia,default-tap = <0x9>; 1104 nvidia,default-trim = <0x5>; 1105 sd-uhs-sdr25; 1106 sd-uhs-sdr50; 1107 sd-uhs-ddr50; 1108 sd-uhs-sdr104; 1109 status = "disabled"; 1110 }; 1111 1112 sdmmc4: mmc@3460000 { 1113 compatible = "nvidia,tegra194-sdhci"; 1114 reg = <0x03460000 0x10000>; 1115 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1117 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1118 clock-names = "sdhci", "tmclk"; 1119 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1120 <&bpmp TEGRA194_CLK_PLLC4>; 1121 assigned-clock-parents = 1122 <&bpmp TEGRA194_CLK_PLLC4>; 1123 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1124 reset-names = "sdhci"; 1125 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1126 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1127 interconnect-names = "dma-mem", "write"; 1128 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1129 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1130 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1131 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1132 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1133 <0x0a>; 1134 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1135 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1136 <0x0a>; 1137 nvidia,default-tap = <0x8>; 1138 nvidia,default-trim = <0x14>; 1139 nvidia,dqs-trim = <40>; 1140 cap-mmc-highspeed; 1141 mmc-ddr-1_8v; 1142 mmc-hs200-1_8v; 1143 mmc-hs400-1_8v; 1144 mmc-hs400-enhanced-strobe; 1145 supports-cqe; 1146 status = "disabled"; 1147 }; 1148 1149 hda@3510000 { 1150 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 1151 reg = <0x3510000 0x10000>; 1152 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1153 clocks = <&bpmp TEGRA194_CLK_HDA>, 1154 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1155 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1156 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1157 resets = <&bpmp TEGRA194_RESET_HDA>, 1158 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1159 reset-names = "hda", "hda2hdmi"; 1160 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1161 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1162 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1163 interconnect-names = "dma-mem", "write"; 1164 iommus = <&smmu TEGRA194_SID_HDA>; 1165 status = "disabled"; 1166 }; 1167 1168 xusb_padctl: padctl@3520000 { 1169 compatible = "nvidia,tegra194-xusb-padctl"; 1170 reg = <0x03520000 0x1000>, 1171 <0x03540000 0x1000>; 1172 reg-names = "padctl", "ao"; 1173 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1174 1175 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1176 reset-names = "padctl"; 1177 1178 status = "disabled"; 1179 1180 pads { 1181 usb2 { 1182 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1183 clock-names = "trk"; 1184 1185 lanes { 1186 usb2-0 { 1187 nvidia,function = "xusb"; 1188 status = "disabled"; 1189 #phy-cells = <0>; 1190 }; 1191 1192 usb2-1 { 1193 nvidia,function = "xusb"; 1194 status = "disabled"; 1195 #phy-cells = <0>; 1196 }; 1197 1198 usb2-2 { 1199 nvidia,function = "xusb"; 1200 status = "disabled"; 1201 #phy-cells = <0>; 1202 }; 1203 1204 usb2-3 { 1205 nvidia,function = "xusb"; 1206 status = "disabled"; 1207 #phy-cells = <0>; 1208 }; 1209 }; 1210 }; 1211 1212 usb3 { 1213 lanes { 1214 usb3-0 { 1215 nvidia,function = "xusb"; 1216 status = "disabled"; 1217 #phy-cells = <0>; 1218 }; 1219 1220 usb3-1 { 1221 nvidia,function = "xusb"; 1222 status = "disabled"; 1223 #phy-cells = <0>; 1224 }; 1225 1226 usb3-2 { 1227 nvidia,function = "xusb"; 1228 status = "disabled"; 1229 #phy-cells = <0>; 1230 }; 1231 1232 usb3-3 { 1233 nvidia,function = "xusb"; 1234 status = "disabled"; 1235 #phy-cells = <0>; 1236 }; 1237 }; 1238 }; 1239 }; 1240 1241 ports { 1242 usb2-0 { 1243 status = "disabled"; 1244 }; 1245 1246 usb2-1 { 1247 status = "disabled"; 1248 }; 1249 1250 usb2-2 { 1251 status = "disabled"; 1252 }; 1253 1254 usb2-3 { 1255 status = "disabled"; 1256 }; 1257 1258 usb3-0 { 1259 status = "disabled"; 1260 }; 1261 1262 usb3-1 { 1263 status = "disabled"; 1264 }; 1265 1266 usb3-2 { 1267 status = "disabled"; 1268 }; 1269 1270 usb3-3 { 1271 status = "disabled"; 1272 }; 1273 }; 1274 }; 1275 1276 usb@3550000 { 1277 compatible = "nvidia,tegra194-xudc"; 1278 reg = <0x03550000 0x8000>, 1279 <0x03558000 0x1000>; 1280 reg-names = "base", "fpci"; 1281 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1282 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1283 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1284 <&bpmp TEGRA194_CLK_XUSB_SS>, 1285 <&bpmp TEGRA194_CLK_XUSB_FS>; 1286 clock-names = "dev", "ss", "ss_src", "fs_src"; 1287 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1288 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1289 interconnect-names = "dma-mem", "write"; 1290 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1291 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1292 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1293 power-domain-names = "dev", "ss"; 1294 nvidia,xusb-padctl = <&xusb_padctl>; 1295 status = "disabled"; 1296 }; 1297 1298 usb@3610000 { 1299 compatible = "nvidia,tegra194-xusb"; 1300 reg = <0x03610000 0x40000>, 1301 <0x03600000 0x10000>; 1302 reg-names = "hcd", "fpci"; 1303 1304 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1306 1307 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1308 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1309 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1310 <&bpmp TEGRA194_CLK_XUSB_SS>, 1311 <&bpmp TEGRA194_CLK_CLK_M>, 1312 <&bpmp TEGRA194_CLK_XUSB_FS>, 1313 <&bpmp TEGRA194_CLK_UTMIPLL>, 1314 <&bpmp TEGRA194_CLK_CLK_M>, 1315 <&bpmp TEGRA194_CLK_PLLE>; 1316 clock-names = "xusb_host", "xusb_falcon_src", 1317 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1318 "xusb_fs_src", "pll_u_480m", "clk_m", 1319 "pll_e"; 1320 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1321 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1322 interconnect-names = "dma-mem", "write"; 1323 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1324 1325 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1326 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1327 power-domain-names = "xusb_host", "xusb_ss"; 1328 1329 nvidia,xusb-padctl = <&xusb_padctl>; 1330 status = "disabled"; 1331 }; 1332 1333 fuse@3820000 { 1334 compatible = "nvidia,tegra194-efuse"; 1335 reg = <0x03820000 0x10000>; 1336 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1337 clock-names = "fuse"; 1338 }; 1339 1340 gic: interrupt-controller@3881000 { 1341 compatible = "arm,gic-400"; 1342 #interrupt-cells = <3>; 1343 interrupt-controller; 1344 reg = <0x03881000 0x1000>, 1345 <0x03882000 0x2000>, 1346 <0x03884000 0x2000>, 1347 <0x03886000 0x2000>; 1348 interrupts = <GIC_PPI 9 1349 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1350 interrupt-parent = <&gic>; 1351 }; 1352 1353 cec@3960000 { 1354 compatible = "nvidia,tegra194-cec"; 1355 reg = <0x03960000 0x10000>; 1356 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1357 clocks = <&bpmp TEGRA194_CLK_CEC>; 1358 clock-names = "cec"; 1359 status = "disabled"; 1360 }; 1361 1362 hte_lic: hardware-timestamp@3aa0000 { 1363 compatible = "nvidia,tegra194-gte-lic"; 1364 reg = <0x3aa0000 0x10000>; 1365 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1366 nvidia,int-threshold = <1>; 1367 nvidia,slices = <11>; 1368 #timestamp-cells = <1>; 1369 status = "okay"; 1370 }; 1371 1372 hsp_top0: hsp@3c00000 { 1373 compatible = "nvidia,tegra194-hsp"; 1374 reg = <0x03c00000 0xa0000>; 1375 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1384 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1385 "shared3", "shared4", "shared5", "shared6", 1386 "shared7"; 1387 #mbox-cells = <2>; 1388 }; 1389 1390 p2u_hsio_0: phy@3e10000 { 1391 compatible = "nvidia,tegra194-p2u"; 1392 reg = <0x03e10000 0x10000>; 1393 reg-names = "ctl"; 1394 1395 #phy-cells = <0>; 1396 }; 1397 1398 p2u_hsio_1: phy@3e20000 { 1399 compatible = "nvidia,tegra194-p2u"; 1400 reg = <0x03e20000 0x10000>; 1401 reg-names = "ctl"; 1402 1403 #phy-cells = <0>; 1404 }; 1405 1406 p2u_hsio_2: phy@3e30000 { 1407 compatible = "nvidia,tegra194-p2u"; 1408 reg = <0x03e30000 0x10000>; 1409 reg-names = "ctl"; 1410 1411 #phy-cells = <0>; 1412 }; 1413 1414 p2u_hsio_3: phy@3e40000 { 1415 compatible = "nvidia,tegra194-p2u"; 1416 reg = <0x03e40000 0x10000>; 1417 reg-names = "ctl"; 1418 1419 #phy-cells = <0>; 1420 }; 1421 1422 p2u_hsio_4: phy@3e50000 { 1423 compatible = "nvidia,tegra194-p2u"; 1424 reg = <0x03e50000 0x10000>; 1425 reg-names = "ctl"; 1426 1427 #phy-cells = <0>; 1428 }; 1429 1430 p2u_hsio_5: phy@3e60000 { 1431 compatible = "nvidia,tegra194-p2u"; 1432 reg = <0x03e60000 0x10000>; 1433 reg-names = "ctl"; 1434 1435 #phy-cells = <0>; 1436 }; 1437 1438 p2u_hsio_6: phy@3e70000 { 1439 compatible = "nvidia,tegra194-p2u"; 1440 reg = <0x03e70000 0x10000>; 1441 reg-names = "ctl"; 1442 1443 #phy-cells = <0>; 1444 }; 1445 1446 p2u_hsio_7: phy@3e80000 { 1447 compatible = "nvidia,tegra194-p2u"; 1448 reg = <0x03e80000 0x10000>; 1449 reg-names = "ctl"; 1450 1451 #phy-cells = <0>; 1452 }; 1453 1454 p2u_hsio_8: phy@3e90000 { 1455 compatible = "nvidia,tegra194-p2u"; 1456 reg = <0x03e90000 0x10000>; 1457 reg-names = "ctl"; 1458 1459 #phy-cells = <0>; 1460 }; 1461 1462 p2u_hsio_9: phy@3ea0000 { 1463 compatible = "nvidia,tegra194-p2u"; 1464 reg = <0x03ea0000 0x10000>; 1465 reg-names = "ctl"; 1466 1467 #phy-cells = <0>; 1468 }; 1469 1470 p2u_nvhs_0: phy@3eb0000 { 1471 compatible = "nvidia,tegra194-p2u"; 1472 reg = <0x03eb0000 0x10000>; 1473 reg-names = "ctl"; 1474 1475 #phy-cells = <0>; 1476 }; 1477 1478 p2u_nvhs_1: phy@3ec0000 { 1479 compatible = "nvidia,tegra194-p2u"; 1480 reg = <0x03ec0000 0x10000>; 1481 reg-names = "ctl"; 1482 1483 #phy-cells = <0>; 1484 }; 1485 1486 p2u_nvhs_2: phy@3ed0000 { 1487 compatible = "nvidia,tegra194-p2u"; 1488 reg = <0x03ed0000 0x10000>; 1489 reg-names = "ctl"; 1490 1491 #phy-cells = <0>; 1492 }; 1493 1494 p2u_nvhs_3: phy@3ee0000 { 1495 compatible = "nvidia,tegra194-p2u"; 1496 reg = <0x03ee0000 0x10000>; 1497 reg-names = "ctl"; 1498 1499 #phy-cells = <0>; 1500 }; 1501 1502 p2u_nvhs_4: phy@3ef0000 { 1503 compatible = "nvidia,tegra194-p2u"; 1504 reg = <0x03ef0000 0x10000>; 1505 reg-names = "ctl"; 1506 1507 #phy-cells = <0>; 1508 }; 1509 1510 p2u_nvhs_5: phy@3f00000 { 1511 compatible = "nvidia,tegra194-p2u"; 1512 reg = <0x03f00000 0x10000>; 1513 reg-names = "ctl"; 1514 1515 #phy-cells = <0>; 1516 }; 1517 1518 p2u_nvhs_6: phy@3f10000 { 1519 compatible = "nvidia,tegra194-p2u"; 1520 reg = <0x03f10000 0x10000>; 1521 reg-names = "ctl"; 1522 1523 #phy-cells = <0>; 1524 }; 1525 1526 p2u_nvhs_7: phy@3f20000 { 1527 compatible = "nvidia,tegra194-p2u"; 1528 reg = <0x03f20000 0x10000>; 1529 reg-names = "ctl"; 1530 1531 #phy-cells = <0>; 1532 }; 1533 1534 p2u_hsio_10: phy@3f30000 { 1535 compatible = "nvidia,tegra194-p2u"; 1536 reg = <0x03f30000 0x10000>; 1537 reg-names = "ctl"; 1538 1539 #phy-cells = <0>; 1540 }; 1541 1542 p2u_hsio_11: phy@3f40000 { 1543 compatible = "nvidia,tegra194-p2u"; 1544 reg = <0x03f40000 0x10000>; 1545 reg-names = "ctl"; 1546 1547 #phy-cells = <0>; 1548 }; 1549 1550 sce-noc@b600000 { 1551 compatible = "nvidia,tegra194-sce-noc"; 1552 reg = <0xb600000 0x1000>; 1553 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1554 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1555 nvidia,axi2apb = <&axi2apb>; 1556 nvidia,apbmisc = <&apbmisc>; 1557 status = "okay"; 1558 }; 1559 1560 rce-noc@be00000 { 1561 compatible = "nvidia,tegra194-rce-noc"; 1562 reg = <0xbe00000 0x1000>; 1563 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1565 nvidia,axi2apb = <&axi2apb>; 1566 nvidia,apbmisc = <&apbmisc>; 1567 status = "okay"; 1568 }; 1569 1570 hsp_aon: hsp@c150000 { 1571 compatible = "nvidia,tegra194-hsp"; 1572 reg = <0x0c150000 0x90000>; 1573 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1577 /* 1578 * Shared interrupt 0 is routed only to AON/SPE, so 1579 * we only have 4 shared interrupts for the CCPLEX. 1580 */ 1581 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1582 #mbox-cells = <2>; 1583 }; 1584 1585 hte_aon: hardware-timestamp@c1e0000 { 1586 compatible = "nvidia,tegra194-gte-aon"; 1587 reg = <0xc1e0000 0x10000>; 1588 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1589 nvidia,int-threshold = <1>; 1590 nvidia,slices = <3>; 1591 #timestamp-cells = <1>; 1592 status = "okay"; 1593 }; 1594 1595 gen2_i2c: i2c@c240000 { 1596 compatible = "nvidia,tegra194-i2c"; 1597 reg = <0x0c240000 0x10000>; 1598 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1602 clock-names = "div-clk"; 1603 resets = <&bpmp TEGRA194_RESET_I2C2>; 1604 reset-names = "i2c"; 1605 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1606 dma-coherent; 1607 dmas = <&gpcdma 22>, <&gpcdma 22>; 1608 dma-names = "rx", "tx"; 1609 status = "disabled"; 1610 }; 1611 1612 gen8_i2c: i2c@c250000 { 1613 compatible = "nvidia,tegra194-i2c"; 1614 reg = <0x0c250000 0x10000>; 1615 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1616 #address-cells = <1>; 1617 #size-cells = <0>; 1618 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1619 clock-names = "div-clk"; 1620 resets = <&bpmp TEGRA194_RESET_I2C8>; 1621 reset-names = "i2c"; 1622 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1623 dma-coherent; 1624 dmas = <&gpcdma 0>, <&gpcdma 0>; 1625 dma-names = "rx", "tx"; 1626 status = "disabled"; 1627 }; 1628 1629 uartc: serial@c280000 { 1630 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1631 reg = <0x0c280000 0x40>; 1632 reg-shift = <2>; 1633 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1634 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1635 clock-names = "serial"; 1636 resets = <&bpmp TEGRA194_RESET_UARTC>; 1637 reset-names = "serial"; 1638 status = "disabled"; 1639 }; 1640 1641 uartg: serial@c290000 { 1642 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1643 reg = <0x0c290000 0x40>; 1644 reg-shift = <2>; 1645 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1646 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1647 clock-names = "serial"; 1648 resets = <&bpmp TEGRA194_RESET_UARTG>; 1649 reset-names = "serial"; 1650 status = "disabled"; 1651 }; 1652 1653 rtc: rtc@c2a0000 { 1654 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1655 reg = <0x0c2a0000 0x10000>; 1656 interrupt-parent = <&pmc>; 1657 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1658 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1659 clock-names = "rtc"; 1660 status = "disabled"; 1661 }; 1662 1663 gpio_aon: gpio@c2f0000 { 1664 compatible = "nvidia,tegra194-gpio-aon"; 1665 reg-names = "security", "gpio"; 1666 reg = <0xc2f0000 0x1000>, 1667 <0xc2f1000 0x1000>; 1668 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1672 gpio-controller; 1673 #gpio-cells = <2>; 1674 interrupt-controller; 1675 #interrupt-cells = <2>; 1676 }; 1677 1678 pwm4: pwm@c340000 { 1679 compatible = "nvidia,tegra194-pwm", 1680 "nvidia,tegra186-pwm"; 1681 reg = <0xc340000 0x10000>; 1682 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1683 resets = <&bpmp TEGRA194_RESET_PWM4>; 1684 reset-names = "pwm"; 1685 status = "disabled"; 1686 #pwm-cells = <2>; 1687 }; 1688 1689 pmc: pmc@c360000 { 1690 compatible = "nvidia,tegra194-pmc"; 1691 reg = <0x0c360000 0x10000>, 1692 <0x0c370000 0x10000>, 1693 <0x0c380000 0x10000>, 1694 <0x0c390000 0x10000>, 1695 <0x0c3a0000 0x10000>; 1696 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1697 1698 #interrupt-cells = <2>; 1699 interrupt-controller; 1700 sdmmc1_3v3: sdmmc1-3v3 { 1701 pins = "sdmmc1-hv"; 1702 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1703 }; 1704 1705 sdmmc1_1v8: sdmmc1-1v8 { 1706 pins = "sdmmc1-hv"; 1707 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1708 }; 1709 sdmmc3_3v3: sdmmc3-3v3 { 1710 pins = "sdmmc3-hv"; 1711 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1712 }; 1713 1714 sdmmc3_1v8: sdmmc3-1v8 { 1715 pins = "sdmmc3-hv"; 1716 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1717 }; 1718 1719 }; 1720 1721 aon-noc@c600000 { 1722 compatible = "nvidia,tegra194-aon-noc"; 1723 reg = <0xc600000 0x1000>; 1724 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1726 nvidia,apbmisc = <&apbmisc>; 1727 status = "okay"; 1728 }; 1729 1730 bpmp-noc@d600000 { 1731 compatible = "nvidia,tegra194-bpmp-noc"; 1732 reg = <0xd600000 0x1000>; 1733 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1735 nvidia,axi2apb = <&axi2apb>; 1736 nvidia,apbmisc = <&apbmisc>; 1737 status = "okay"; 1738 }; 1739 1740 iommu@10000000 { 1741 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1742 reg = <0x10000000 0x800000>; 1743 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1808 stream-match-mask = <0x7f80>; 1809 #global-interrupts = <1>; 1810 #iommu-cells = <1>; 1811 1812 nvidia,memory-controller = <&mc>; 1813 status = "disabled"; 1814 }; 1815 1816 smmu: iommu@12000000 { 1817 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1818 reg = <0x12000000 0x800000>, 1819 <0x11000000 0x800000>; 1820 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1886 stream-match-mask = <0x7f80>; 1887 #global-interrupts = <2>; 1888 #iommu-cells = <1>; 1889 1890 nvidia,memory-controller = <&mc>; 1891 status = "okay"; 1892 }; 1893 1894 host1x@13e00000 { 1895 compatible = "nvidia,tegra194-host1x"; 1896 reg = <0x13e00000 0x10000>, 1897 <0x13e10000 0x10000>; 1898 reg-names = "hypervisor", "vm"; 1899 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1901 interrupt-names = "syncpt", "host1x"; 1902 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1903 clock-names = "host1x"; 1904 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1905 reset-names = "host1x"; 1906 1907 #address-cells = <1>; 1908 #size-cells = <1>; 1909 1910 ranges = <0x14800000 0x14800000 0x02800000>; 1911 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1912 interconnect-names = "dma-mem"; 1913 iommus = <&smmu TEGRA194_SID_HOST1X>; 1914 1915 /* Context isolation domains */ 1916 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1917 <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1918 <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1919 <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1920 <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1921 <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1922 <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1923 <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1924 1925 nvdec@15140000 { 1926 compatible = "nvidia,tegra194-nvdec"; 1927 reg = <0x15140000 0x00040000>; 1928 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1929 clock-names = "nvdec"; 1930 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1931 reset-names = "nvdec"; 1932 1933 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1934 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1935 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1936 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1937 interconnect-names = "dma-mem", "read-1", "write"; 1938 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1939 dma-coherent; 1940 1941 nvidia,host1x-class = <0xf5>; 1942 }; 1943 1944 display-hub@15200000 { 1945 compatible = "nvidia,tegra194-display"; 1946 reg = <0x15200000 0x00040000>; 1947 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1948 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1949 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1950 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1951 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1952 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1953 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1954 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1955 "wgrp3", "wgrp4", "wgrp5"; 1956 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1957 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1958 clock-names = "disp", "hub"; 1959 status = "disabled"; 1960 1961 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1962 1963 #address-cells = <1>; 1964 #size-cells = <1>; 1965 1966 ranges = <0x15200000 0x15200000 0x40000>; 1967 1968 display@15200000 { 1969 compatible = "nvidia,tegra194-dc"; 1970 reg = <0x15200000 0x10000>; 1971 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1972 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1973 clock-names = "dc"; 1974 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1975 reset-names = "dc"; 1976 1977 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1978 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1979 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1980 interconnect-names = "dma-mem", "read-1"; 1981 1982 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1983 nvidia,head = <0>; 1984 }; 1985 1986 display@15210000 { 1987 compatible = "nvidia,tegra194-dc"; 1988 reg = <0x15210000 0x10000>; 1989 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1990 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1991 clock-names = "dc"; 1992 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1993 reset-names = "dc"; 1994 1995 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1996 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1997 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1998 interconnect-names = "dma-mem", "read-1"; 1999 2000 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2001 nvidia,head = <1>; 2002 }; 2003 2004 display@15220000 { 2005 compatible = "nvidia,tegra194-dc"; 2006 reg = <0x15220000 0x10000>; 2007 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2008 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 2009 clock-names = "dc"; 2010 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 2011 reset-names = "dc"; 2012 2013 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2014 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2015 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2016 interconnect-names = "dma-mem", "read-1"; 2017 2018 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2019 nvidia,head = <2>; 2020 }; 2021 2022 display@15230000 { 2023 compatible = "nvidia,tegra194-dc"; 2024 reg = <0x15230000 0x10000>; 2025 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2026 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 2027 clock-names = "dc"; 2028 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 2029 reset-names = "dc"; 2030 2031 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2032 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2033 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2034 interconnect-names = "dma-mem", "read-1"; 2035 2036 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2037 nvidia,head = <3>; 2038 }; 2039 }; 2040 2041 vic@15340000 { 2042 compatible = "nvidia,tegra194-vic"; 2043 reg = <0x15340000 0x00040000>; 2044 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2045 clocks = <&bpmp TEGRA194_CLK_VIC>; 2046 clock-names = "vic"; 2047 resets = <&bpmp TEGRA194_RESET_VIC>; 2048 reset-names = "vic"; 2049 2050 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2051 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2052 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2053 interconnect-names = "dma-mem", "write"; 2054 iommus = <&smmu TEGRA194_SID_VIC>; 2055 dma-coherent; 2056 }; 2057 2058 nvjpg@15380000 { 2059 compatible = "nvidia,tegra194-nvjpg"; 2060 reg = <0x15380000 0x40000>; 2061 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2062 clock-names = "nvjpg"; 2063 resets = <&bpmp TEGRA194_RESET_NVJPG>; 2064 reset-names = "nvjpg"; 2065 2066 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2067 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2068 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2069 interconnect-names = "dma-mem", "write"; 2070 iommus = <&smmu TEGRA194_SID_NVJPG>; 2071 dma-coherent; 2072 }; 2073 2074 nvdec@15480000 { 2075 compatible = "nvidia,tegra194-nvdec"; 2076 reg = <0x15480000 0x00040000>; 2077 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 2078 clock-names = "nvdec"; 2079 resets = <&bpmp TEGRA194_RESET_NVDEC>; 2080 reset-names = "nvdec"; 2081 2082 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 2083 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 2084 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 2085 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 2086 interconnect-names = "dma-mem", "read-1", "write"; 2087 iommus = <&smmu TEGRA194_SID_NVDEC>; 2088 dma-coherent; 2089 2090 nvidia,host1x-class = <0xf0>; 2091 }; 2092 2093 nvenc@154c0000 { 2094 compatible = "nvidia,tegra194-nvenc"; 2095 reg = <0x154c0000 0x40000>; 2096 clocks = <&bpmp TEGRA194_CLK_NVENC>; 2097 clock-names = "nvenc"; 2098 resets = <&bpmp TEGRA194_RESET_NVENC>; 2099 reset-names = "nvenc"; 2100 2101 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2102 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2103 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2104 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2105 interconnect-names = "dma-mem", "read-1", "write"; 2106 iommus = <&smmu TEGRA194_SID_NVENC>; 2107 dma-coherent; 2108 2109 nvidia,host1x-class = <0x21>; 2110 }; 2111 2112 dpaux0: dpaux@155c0000 { 2113 compatible = "nvidia,tegra194-dpaux"; 2114 reg = <0x155c0000 0x10000>; 2115 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 2116 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 2117 <&bpmp TEGRA194_CLK_PLLDP>; 2118 clock-names = "dpaux", "parent"; 2119 resets = <&bpmp TEGRA194_RESET_DPAUX>; 2120 reset-names = "dpaux"; 2121 status = "disabled"; 2122 2123 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2124 2125 state_dpaux0_aux: pinmux-aux { 2126 groups = "dpaux-io"; 2127 function = "aux"; 2128 }; 2129 2130 state_dpaux0_i2c: pinmux-i2c { 2131 groups = "dpaux-io"; 2132 function = "i2c"; 2133 }; 2134 2135 state_dpaux0_off: pinmux-off { 2136 groups = "dpaux-io"; 2137 function = "off"; 2138 }; 2139 2140 i2c-bus { 2141 #address-cells = <1>; 2142 #size-cells = <0>; 2143 }; 2144 }; 2145 2146 dpaux1: dpaux@155d0000 { 2147 compatible = "nvidia,tegra194-dpaux"; 2148 reg = <0x155d0000 0x10000>; 2149 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2150 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 2151 <&bpmp TEGRA194_CLK_PLLDP>; 2152 clock-names = "dpaux", "parent"; 2153 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2154 reset-names = "dpaux"; 2155 status = "disabled"; 2156 2157 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2158 2159 state_dpaux1_aux: pinmux-aux { 2160 groups = "dpaux-io"; 2161 function = "aux"; 2162 }; 2163 2164 state_dpaux1_i2c: pinmux-i2c { 2165 groups = "dpaux-io"; 2166 function = "i2c"; 2167 }; 2168 2169 state_dpaux1_off: pinmux-off { 2170 groups = "dpaux-io"; 2171 function = "off"; 2172 }; 2173 2174 i2c-bus { 2175 #address-cells = <1>; 2176 #size-cells = <0>; 2177 }; 2178 }; 2179 2180 dpaux2: dpaux@155e0000 { 2181 compatible = "nvidia,tegra194-dpaux"; 2182 reg = <0x155e0000 0x10000>; 2183 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2184 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2185 <&bpmp TEGRA194_CLK_PLLDP>; 2186 clock-names = "dpaux", "parent"; 2187 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2188 reset-names = "dpaux"; 2189 status = "disabled"; 2190 2191 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2192 2193 state_dpaux2_aux: pinmux-aux { 2194 groups = "dpaux-io"; 2195 function = "aux"; 2196 }; 2197 2198 state_dpaux2_i2c: pinmux-i2c { 2199 groups = "dpaux-io"; 2200 function = "i2c"; 2201 }; 2202 2203 state_dpaux2_off: pinmux-off { 2204 groups = "dpaux-io"; 2205 function = "off"; 2206 }; 2207 2208 i2c-bus { 2209 #address-cells = <1>; 2210 #size-cells = <0>; 2211 }; 2212 }; 2213 2214 dpaux3: dpaux@155f0000 { 2215 compatible = "nvidia,tegra194-dpaux"; 2216 reg = <0x155f0000 0x10000>; 2217 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2218 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2219 <&bpmp TEGRA194_CLK_PLLDP>; 2220 clock-names = "dpaux", "parent"; 2221 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2222 reset-names = "dpaux"; 2223 status = "disabled"; 2224 2225 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2226 2227 state_dpaux3_aux: pinmux-aux { 2228 groups = "dpaux-io"; 2229 function = "aux"; 2230 }; 2231 2232 state_dpaux3_i2c: pinmux-i2c { 2233 groups = "dpaux-io"; 2234 function = "i2c"; 2235 }; 2236 2237 state_dpaux3_off: pinmux-off { 2238 groups = "dpaux-io"; 2239 function = "off"; 2240 }; 2241 2242 i2c-bus { 2243 #address-cells = <1>; 2244 #size-cells = <0>; 2245 }; 2246 }; 2247 2248 nvenc@15a80000 { 2249 compatible = "nvidia,tegra194-nvenc"; 2250 reg = <0x15a80000 0x00040000>; 2251 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2252 clock-names = "nvenc"; 2253 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2254 reset-names = "nvenc"; 2255 2256 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2257 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2258 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2259 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2260 interconnect-names = "dma-mem", "read-1", "write"; 2261 iommus = <&smmu TEGRA194_SID_NVENC1>; 2262 dma-coherent; 2263 2264 nvidia,host1x-class = <0x22>; 2265 }; 2266 2267 sor0: sor@15b00000 { 2268 compatible = "nvidia,tegra194-sor"; 2269 reg = <0x15b00000 0x40000>; 2270 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2271 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2272 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2273 <&bpmp TEGRA194_CLK_PLLD>, 2274 <&bpmp TEGRA194_CLK_PLLDP>, 2275 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2276 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2277 clock-names = "sor", "out", "parent", "dp", "safe", 2278 "pad"; 2279 resets = <&bpmp TEGRA194_RESET_SOR0>; 2280 reset-names = "sor"; 2281 pinctrl-0 = <&state_dpaux0_aux>; 2282 pinctrl-1 = <&state_dpaux0_i2c>; 2283 pinctrl-2 = <&state_dpaux0_off>; 2284 pinctrl-names = "aux", "i2c", "off"; 2285 status = "disabled"; 2286 2287 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2288 nvidia,interface = <0>; 2289 }; 2290 2291 sor1: sor@15b40000 { 2292 compatible = "nvidia,tegra194-sor"; 2293 reg = <0x15b40000 0x40000>; 2294 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2295 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2296 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2297 <&bpmp TEGRA194_CLK_PLLD2>, 2298 <&bpmp TEGRA194_CLK_PLLDP>, 2299 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2300 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2301 clock-names = "sor", "out", "parent", "dp", "safe", 2302 "pad"; 2303 resets = <&bpmp TEGRA194_RESET_SOR1>; 2304 reset-names = "sor"; 2305 pinctrl-0 = <&state_dpaux1_aux>; 2306 pinctrl-1 = <&state_dpaux1_i2c>; 2307 pinctrl-2 = <&state_dpaux1_off>; 2308 pinctrl-names = "aux", "i2c", "off"; 2309 status = "disabled"; 2310 2311 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2312 nvidia,interface = <1>; 2313 }; 2314 2315 sor2: sor@15b80000 { 2316 compatible = "nvidia,tegra194-sor"; 2317 reg = <0x15b80000 0x40000>; 2318 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2319 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2320 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2321 <&bpmp TEGRA194_CLK_PLLD3>, 2322 <&bpmp TEGRA194_CLK_PLLDP>, 2323 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2324 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2325 clock-names = "sor", "out", "parent", "dp", "safe", 2326 "pad"; 2327 resets = <&bpmp TEGRA194_RESET_SOR2>; 2328 reset-names = "sor"; 2329 pinctrl-0 = <&state_dpaux2_aux>; 2330 pinctrl-1 = <&state_dpaux2_i2c>; 2331 pinctrl-2 = <&state_dpaux2_off>; 2332 pinctrl-names = "aux", "i2c", "off"; 2333 status = "disabled"; 2334 2335 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2336 nvidia,interface = <2>; 2337 }; 2338 2339 sor3: sor@15bc0000 { 2340 compatible = "nvidia,tegra194-sor"; 2341 reg = <0x15bc0000 0x40000>; 2342 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2343 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2344 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2345 <&bpmp TEGRA194_CLK_PLLD4>, 2346 <&bpmp TEGRA194_CLK_PLLDP>, 2347 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2348 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2349 clock-names = "sor", "out", "parent", "dp", "safe", 2350 "pad"; 2351 resets = <&bpmp TEGRA194_RESET_SOR3>; 2352 reset-names = "sor"; 2353 pinctrl-0 = <&state_dpaux3_aux>; 2354 pinctrl-1 = <&state_dpaux3_i2c>; 2355 pinctrl-2 = <&state_dpaux3_off>; 2356 pinctrl-names = "aux", "i2c", "off"; 2357 status = "disabled"; 2358 2359 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2360 nvidia,interface = <3>; 2361 }; 2362 }; 2363 2364 gpu@17000000 { 2365 compatible = "nvidia,gv11b"; 2366 reg = <0x17000000 0x1000000>, 2367 <0x18000000 0x1000000>; 2368 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2369 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2370 interrupt-names = "stall", "nonstall"; 2371 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2372 <&bpmp TEGRA194_CLK_GPU_PWR>, 2373 <&bpmp TEGRA194_CLK_FUSE>; 2374 clock-names = "gpu", "pwr", "fuse"; 2375 resets = <&bpmp TEGRA194_RESET_GPU>; 2376 reset-names = "gpu"; 2377 dma-coherent; 2378 2379 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2380 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2381 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2382 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2383 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2384 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2385 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2386 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2387 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2388 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2389 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2390 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2391 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2392 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2393 "read-1", "read-1-hp", "write-1", 2394 "read-2", "read-2-hp", "write-2", 2395 "read-3", "read-3-hp", "write-3"; 2396 }; 2397 }; 2398 2399 pcie@14100000 { 2400 compatible = "nvidia,tegra194-pcie"; 2401 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2402 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2403 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2404 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2405 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2406 reg-names = "appl", "config", "atu_dma", "dbi"; 2407 2408 status = "disabled"; 2409 2410 #address-cells = <3>; 2411 #size-cells = <2>; 2412 device_type = "pci"; 2413 num-lanes = <1>; 2414 linux,pci-domain = <1>; 2415 2416 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2417 clock-names = "core"; 2418 2419 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2420 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2421 reset-names = "apb", "core"; 2422 2423 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2424 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2425 interrupt-names = "intr", "msi"; 2426 2427 #interrupt-cells = <1>; 2428 interrupt-map-mask = <0 0 0 0>; 2429 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2430 2431 nvidia,bpmp = <&bpmp 1>; 2432 2433 nvidia,aspm-cmrt-us = <60>; 2434 nvidia,aspm-pwr-on-t-us = <20>; 2435 nvidia,aspm-l0s-entrance-latency-us = <3>; 2436 2437 bus-range = <0x0 0xff>; 2438 2439 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2440 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2441 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2442 2443 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2444 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2445 interconnect-names = "dma-mem", "write"; 2446 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2447 iommu-map-mask = <0x0>; 2448 dma-coherent; 2449 }; 2450 2451 pcie@14120000 { 2452 compatible = "nvidia,tegra194-pcie"; 2453 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2454 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2455 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2456 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2457 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2458 reg-names = "appl", "config", "atu_dma", "dbi"; 2459 2460 status = "disabled"; 2461 2462 #address-cells = <3>; 2463 #size-cells = <2>; 2464 device_type = "pci"; 2465 num-lanes = <1>; 2466 linux,pci-domain = <2>; 2467 2468 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2469 clock-names = "core"; 2470 2471 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2472 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2473 reset-names = "apb", "core"; 2474 2475 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2476 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2477 interrupt-names = "intr", "msi"; 2478 2479 #interrupt-cells = <1>; 2480 interrupt-map-mask = <0 0 0 0>; 2481 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2482 2483 nvidia,bpmp = <&bpmp 2>; 2484 2485 nvidia,aspm-cmrt-us = <60>; 2486 nvidia,aspm-pwr-on-t-us = <20>; 2487 nvidia,aspm-l0s-entrance-latency-us = <3>; 2488 2489 bus-range = <0x0 0xff>; 2490 2491 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2492 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2493 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2494 2495 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2496 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2497 interconnect-names = "dma-mem", "write"; 2498 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2499 iommu-map-mask = <0x0>; 2500 dma-coherent; 2501 }; 2502 2503 pcie@14140000 { 2504 compatible = "nvidia,tegra194-pcie"; 2505 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2506 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2507 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2508 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2509 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2510 reg-names = "appl", "config", "atu_dma", "dbi"; 2511 2512 status = "disabled"; 2513 2514 #address-cells = <3>; 2515 #size-cells = <2>; 2516 device_type = "pci"; 2517 num-lanes = <1>; 2518 linux,pci-domain = <3>; 2519 2520 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2521 clock-names = "core"; 2522 2523 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2524 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2525 reset-names = "apb", "core"; 2526 2527 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2528 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2529 interrupt-names = "intr", "msi"; 2530 2531 #interrupt-cells = <1>; 2532 interrupt-map-mask = <0 0 0 0>; 2533 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2534 2535 nvidia,bpmp = <&bpmp 3>; 2536 2537 nvidia,aspm-cmrt-us = <60>; 2538 nvidia,aspm-pwr-on-t-us = <20>; 2539 nvidia,aspm-l0s-entrance-latency-us = <3>; 2540 2541 bus-range = <0x0 0xff>; 2542 2543 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2544 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2545 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2546 2547 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2548 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2549 interconnect-names = "dma-mem", "write"; 2550 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2551 iommu-map-mask = <0x0>; 2552 dma-coherent; 2553 }; 2554 2555 pcie@14160000 { 2556 compatible = "nvidia,tegra194-pcie"; 2557 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2558 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2559 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2560 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2561 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2562 reg-names = "appl", "config", "atu_dma", "dbi"; 2563 2564 status = "disabled"; 2565 2566 #address-cells = <3>; 2567 #size-cells = <2>; 2568 device_type = "pci"; 2569 num-lanes = <4>; 2570 linux,pci-domain = <4>; 2571 2572 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2573 clock-names = "core"; 2574 2575 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2576 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2577 reset-names = "apb", "core"; 2578 2579 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2580 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2581 interrupt-names = "intr", "msi"; 2582 2583 #interrupt-cells = <1>; 2584 interrupt-map-mask = <0 0 0 0>; 2585 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2586 2587 nvidia,bpmp = <&bpmp 4>; 2588 2589 nvidia,aspm-cmrt-us = <60>; 2590 nvidia,aspm-pwr-on-t-us = <20>; 2591 nvidia,aspm-l0s-entrance-latency-us = <3>; 2592 2593 bus-range = <0x0 0xff>; 2594 2595 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2596 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2597 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2598 2599 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2600 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2601 interconnect-names = "dma-mem", "write"; 2602 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2603 iommu-map-mask = <0x0>; 2604 dma-coherent; 2605 }; 2606 2607 pcie@14180000 { 2608 compatible = "nvidia,tegra194-pcie"; 2609 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2610 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2611 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2612 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2613 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2614 reg-names = "appl", "config", "atu_dma", "dbi"; 2615 2616 status = "disabled"; 2617 2618 #address-cells = <3>; 2619 #size-cells = <2>; 2620 device_type = "pci"; 2621 num-lanes = <8>; 2622 linux,pci-domain = <0>; 2623 2624 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2625 clock-names = "core"; 2626 2627 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2628 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2629 reset-names = "apb", "core"; 2630 2631 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2632 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2633 interrupt-names = "intr", "msi"; 2634 2635 #interrupt-cells = <1>; 2636 interrupt-map-mask = <0 0 0 0>; 2637 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2638 2639 nvidia,bpmp = <&bpmp 0>; 2640 2641 nvidia,aspm-cmrt-us = <60>; 2642 nvidia,aspm-pwr-on-t-us = <20>; 2643 nvidia,aspm-l0s-entrance-latency-us = <3>; 2644 2645 bus-range = <0x0 0xff>; 2646 2647 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2648 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2649 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2650 2651 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2652 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2653 interconnect-names = "dma-mem", "write"; 2654 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2655 iommu-map-mask = <0x0>; 2656 dma-coherent; 2657 }; 2658 2659 pcie@141a0000 { 2660 compatible = "nvidia,tegra194-pcie"; 2661 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2662 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2663 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2664 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2665 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2666 reg-names = "appl", "config", "atu_dma", "dbi"; 2667 2668 status = "disabled"; 2669 2670 #address-cells = <3>; 2671 #size-cells = <2>; 2672 device_type = "pci"; 2673 num-lanes = <8>; 2674 linux,pci-domain = <5>; 2675 2676 pinctrl-names = "default"; 2677 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2678 2679 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2680 clock-names = "core"; 2681 2682 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2683 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2684 reset-names = "apb", "core"; 2685 2686 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2687 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2688 interrupt-names = "intr", "msi"; 2689 2690 nvidia,bpmp = <&bpmp 5>; 2691 2692 #interrupt-cells = <1>; 2693 interrupt-map-mask = <0 0 0 0>; 2694 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2695 2696 nvidia,aspm-cmrt-us = <60>; 2697 nvidia,aspm-pwr-on-t-us = <20>; 2698 nvidia,aspm-l0s-entrance-latency-us = <3>; 2699 2700 bus-range = <0x0 0xff>; 2701 2702 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2703 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2704 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2705 2706 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2707 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2708 interconnect-names = "dma-mem", "write"; 2709 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2710 iommu-map-mask = <0x0>; 2711 dma-coherent; 2712 }; 2713 2714 pcie-ep@14160000 { 2715 compatible = "nvidia,tegra194-pcie-ep"; 2716 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2717 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2718 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2719 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2720 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2721 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2722 2723 status = "disabled"; 2724 2725 num-lanes = <4>; 2726 num-ib-windows = <2>; 2727 num-ob-windows = <8>; 2728 2729 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2730 clock-names = "core"; 2731 2732 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2733 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2734 reset-names = "apb", "core"; 2735 2736 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2737 interrupt-names = "intr"; 2738 2739 nvidia,bpmp = <&bpmp 4>; 2740 2741 nvidia,aspm-cmrt-us = <60>; 2742 nvidia,aspm-pwr-on-t-us = <20>; 2743 nvidia,aspm-l0s-entrance-latency-us = <3>; 2744 2745 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2746 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2747 interconnect-names = "dma-mem", "write"; 2748 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2749 iommu-map-mask = <0x0>; 2750 dma-coherent; 2751 }; 2752 2753 pcie-ep@14180000 { 2754 compatible = "nvidia,tegra194-pcie-ep"; 2755 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2756 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2757 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2758 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2759 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2760 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2761 2762 status = "disabled"; 2763 2764 num-lanes = <8>; 2765 num-ib-windows = <2>; 2766 num-ob-windows = <8>; 2767 2768 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2769 clock-names = "core"; 2770 2771 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2772 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2773 reset-names = "apb", "core"; 2774 2775 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2776 interrupt-names = "intr"; 2777 2778 nvidia,bpmp = <&bpmp 0>; 2779 2780 nvidia,aspm-cmrt-us = <60>; 2781 nvidia,aspm-pwr-on-t-us = <20>; 2782 nvidia,aspm-l0s-entrance-latency-us = <3>; 2783 2784 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2785 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2786 interconnect-names = "dma-mem", "write"; 2787 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2788 iommu-map-mask = <0x0>; 2789 dma-coherent; 2790 }; 2791 2792 pcie-ep@141a0000 { 2793 compatible = "nvidia,tegra194-pcie-ep"; 2794 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2795 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2796 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2797 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2798 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2799 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2800 2801 status = "disabled"; 2802 2803 num-lanes = <8>; 2804 num-ib-windows = <2>; 2805 num-ob-windows = <8>; 2806 2807 pinctrl-names = "default"; 2808 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2809 2810 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2811 clock-names = "core"; 2812 2813 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2814 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2815 reset-names = "apb", "core"; 2816 2817 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2818 interrupt-names = "intr"; 2819 2820 nvidia,bpmp = <&bpmp 5>; 2821 2822 nvidia,aspm-cmrt-us = <60>; 2823 nvidia,aspm-pwr-on-t-us = <20>; 2824 nvidia,aspm-l0s-entrance-latency-us = <3>; 2825 2826 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2827 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2828 interconnect-names = "dma-mem", "write"; 2829 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2830 iommu-map-mask = <0x0>; 2831 dma-coherent; 2832 }; 2833 2834 sram@40000000 { 2835 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2836 reg = <0x0 0x40000000 0x0 0x50000>; 2837 #address-cells = <1>; 2838 #size-cells = <1>; 2839 ranges = <0x0 0x0 0x40000000 0x50000>; 2840 no-memory-wc; 2841 2842 cpu_bpmp_tx: sram@4e000 { 2843 reg = <0x4e000 0x1000>; 2844 label = "cpu-bpmp-tx"; 2845 pool; 2846 }; 2847 2848 cpu_bpmp_rx: sram@4f000 { 2849 reg = <0x4f000 0x1000>; 2850 label = "cpu-bpmp-rx"; 2851 pool; 2852 }; 2853 }; 2854 2855 bpmp: bpmp { 2856 compatible = "nvidia,tegra186-bpmp"; 2857 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2858 TEGRA_HSP_DB_MASTER_BPMP>; 2859 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2860 #clock-cells = <1>; 2861 #reset-cells = <1>; 2862 #power-domain-cells = <1>; 2863 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2864 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2865 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2866 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2867 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2868 iommus = <&smmu TEGRA194_SID_BPMP>; 2869 2870 bpmp_i2c: i2c { 2871 compatible = "nvidia,tegra186-bpmp-i2c"; 2872 nvidia,bpmp-bus-id = <5>; 2873 #address-cells = <1>; 2874 #size-cells = <0>; 2875 }; 2876 2877 bpmp_thermal: thermal { 2878 compatible = "nvidia,tegra186-bpmp-thermal"; 2879 #thermal-sensor-cells = <1>; 2880 }; 2881 }; 2882 2883 cpus { 2884 compatible = "nvidia,tegra194-ccplex"; 2885 nvidia,bpmp = <&bpmp>; 2886 #address-cells = <1>; 2887 #size-cells = <0>; 2888 2889 cpu0_0: cpu@0 { 2890 compatible = "nvidia,tegra194-carmel"; 2891 device_type = "cpu"; 2892 reg = <0x000>; 2893 enable-method = "psci"; 2894 i-cache-size = <131072>; 2895 i-cache-line-size = <64>; 2896 i-cache-sets = <512>; 2897 d-cache-size = <65536>; 2898 d-cache-line-size = <64>; 2899 d-cache-sets = <256>; 2900 next-level-cache = <&l2c_0>; 2901 }; 2902 2903 cpu0_1: cpu@1 { 2904 compatible = "nvidia,tegra194-carmel"; 2905 device_type = "cpu"; 2906 reg = <0x001>; 2907 enable-method = "psci"; 2908 i-cache-size = <131072>; 2909 i-cache-line-size = <64>; 2910 i-cache-sets = <512>; 2911 d-cache-size = <65536>; 2912 d-cache-line-size = <64>; 2913 d-cache-sets = <256>; 2914 next-level-cache = <&l2c_0>; 2915 }; 2916 2917 cpu1_0: cpu@100 { 2918 compatible = "nvidia,tegra194-carmel"; 2919 device_type = "cpu"; 2920 reg = <0x100>; 2921 enable-method = "psci"; 2922 i-cache-size = <131072>; 2923 i-cache-line-size = <64>; 2924 i-cache-sets = <512>; 2925 d-cache-size = <65536>; 2926 d-cache-line-size = <64>; 2927 d-cache-sets = <256>; 2928 next-level-cache = <&l2c_1>; 2929 }; 2930 2931 cpu1_1: cpu@101 { 2932 compatible = "nvidia,tegra194-carmel"; 2933 device_type = "cpu"; 2934 reg = <0x101>; 2935 enable-method = "psci"; 2936 i-cache-size = <131072>; 2937 i-cache-line-size = <64>; 2938 i-cache-sets = <512>; 2939 d-cache-size = <65536>; 2940 d-cache-line-size = <64>; 2941 d-cache-sets = <256>; 2942 next-level-cache = <&l2c_1>; 2943 }; 2944 2945 cpu2_0: cpu@200 { 2946 compatible = "nvidia,tegra194-carmel"; 2947 device_type = "cpu"; 2948 reg = <0x200>; 2949 enable-method = "psci"; 2950 i-cache-size = <131072>; 2951 i-cache-line-size = <64>; 2952 i-cache-sets = <512>; 2953 d-cache-size = <65536>; 2954 d-cache-line-size = <64>; 2955 d-cache-sets = <256>; 2956 next-level-cache = <&l2c_2>; 2957 }; 2958 2959 cpu2_1: cpu@201 { 2960 compatible = "nvidia,tegra194-carmel"; 2961 device_type = "cpu"; 2962 reg = <0x201>; 2963 enable-method = "psci"; 2964 i-cache-size = <131072>; 2965 i-cache-line-size = <64>; 2966 i-cache-sets = <512>; 2967 d-cache-size = <65536>; 2968 d-cache-line-size = <64>; 2969 d-cache-sets = <256>; 2970 next-level-cache = <&l2c_2>; 2971 }; 2972 2973 cpu3_0: cpu@300 { 2974 compatible = "nvidia,tegra194-carmel"; 2975 device_type = "cpu"; 2976 reg = <0x300>; 2977 enable-method = "psci"; 2978 i-cache-size = <131072>; 2979 i-cache-line-size = <64>; 2980 i-cache-sets = <512>; 2981 d-cache-size = <65536>; 2982 d-cache-line-size = <64>; 2983 d-cache-sets = <256>; 2984 next-level-cache = <&l2c_3>; 2985 }; 2986 2987 cpu3_1: cpu@301 { 2988 compatible = "nvidia,tegra194-carmel"; 2989 device_type = "cpu"; 2990 reg = <0x301>; 2991 enable-method = "psci"; 2992 i-cache-size = <131072>; 2993 i-cache-line-size = <64>; 2994 i-cache-sets = <512>; 2995 d-cache-size = <65536>; 2996 d-cache-line-size = <64>; 2997 d-cache-sets = <256>; 2998 next-level-cache = <&l2c_3>; 2999 }; 3000 3001 cpu-map { 3002 cluster0 { 3003 core0 { 3004 cpu = <&cpu0_0>; 3005 }; 3006 3007 core1 { 3008 cpu = <&cpu0_1>; 3009 }; 3010 }; 3011 3012 cluster1 { 3013 core0 { 3014 cpu = <&cpu1_0>; 3015 }; 3016 3017 core1 { 3018 cpu = <&cpu1_1>; 3019 }; 3020 }; 3021 3022 cluster2 { 3023 core0 { 3024 cpu = <&cpu2_0>; 3025 }; 3026 3027 core1 { 3028 cpu = <&cpu2_1>; 3029 }; 3030 }; 3031 3032 cluster3 { 3033 core0 { 3034 cpu = <&cpu3_0>; 3035 }; 3036 3037 core1 { 3038 cpu = <&cpu3_1>; 3039 }; 3040 }; 3041 }; 3042 3043 l2c_0: l2-cache0 { 3044 cache-size = <2097152>; 3045 cache-line-size = <64>; 3046 cache-sets = <2048>; 3047 next-level-cache = <&l3c>; 3048 }; 3049 3050 l2c_1: l2-cache1 { 3051 cache-size = <2097152>; 3052 cache-line-size = <64>; 3053 cache-sets = <2048>; 3054 next-level-cache = <&l3c>; 3055 }; 3056 3057 l2c_2: l2-cache2 { 3058 cache-size = <2097152>; 3059 cache-line-size = <64>; 3060 cache-sets = <2048>; 3061 next-level-cache = <&l3c>; 3062 }; 3063 3064 l2c_3: l2-cache3 { 3065 cache-size = <2097152>; 3066 cache-line-size = <64>; 3067 cache-sets = <2048>; 3068 next-level-cache = <&l3c>; 3069 }; 3070 3071 l3c: l3-cache { 3072 cache-size = <4194304>; 3073 cache-line-size = <64>; 3074 cache-sets = <4096>; 3075 }; 3076 }; 3077 3078 pmu { 3079 compatible = "nvidia,carmel-pmu"; 3080 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 3088 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 3089 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 3090 }; 3091 3092 psci { 3093 compatible = "arm,psci-1.0"; 3094 status = "okay"; 3095 method = "smc"; 3096 }; 3097 3098 sound { 3099 status = "disabled"; 3100 3101 clocks = <&bpmp TEGRA194_CLK_PLLA>, 3102 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3103 clock-names = "pll_a", "plla_out0"; 3104 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 3105 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 3106 <&bpmp TEGRA194_CLK_AUD_MCLK>; 3107 assigned-clock-parents = <0>, 3108 <&bpmp TEGRA194_CLK_PLLA>, 3109 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3110 /* 3111 * PLLA supports dynamic ramp. Below initial rate is chosen 3112 * for this to work and oscillate between base rates required 3113 * for 8x and 11.025x sample rate streams. 3114 */ 3115 assigned-clock-rates = <258000000>; 3116 }; 3117 3118 tcu: serial { 3119 compatible = "nvidia,tegra194-tcu"; 3120 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3121 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3122 mbox-names = "rx", "tx"; 3123 }; 3124 3125 thermal-zones { 3126 cpu-thermal { 3127 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3128 status = "disabled"; 3129 }; 3130 3131 gpu-thermal { 3132 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3133 status = "disabled"; 3134 }; 3135 3136 aux-thermal { 3137 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3138 status = "disabled"; 3139 }; 3140 3141 pllx-thermal { 3142 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3143 status = "disabled"; 3144 }; 3145 3146 ao-thermal { 3147 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3148 status = "disabled"; 3149 }; 3150 3151 tj-thermal { 3152 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3153 status = "disabled"; 3154 }; 3155 }; 3156 3157 timer { 3158 compatible = "arm,armv8-timer"; 3159 interrupts = <GIC_PPI 13 3160 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3161 <GIC_PPI 14 3162 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3163 <GIC_PPI 11 3164 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3165 <GIC_PPI 10 3166 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3167 interrupt-parent = <&gic>; 3168 always-on; 3169 }; 3170}; 3171