1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x0 0x0 0x0 0x40000000>; 25 26 apbmisc: misc@100000 { 27 compatible = "nvidia,tegra194-misc"; 28 reg = <0x00100000 0xf000>, 29 <0x0010f000 0x1000>; 30 }; 31 32 gpio: gpio@2200000 { 33 compatible = "nvidia,tegra194-gpio"; 34 reg-names = "security", "gpio"; 35 reg = <0x2200000 0x10000>, 36 <0x2210000 0x10000>; 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85 #interrupt-cells = <2>; 86 interrupt-controller; 87 #gpio-cells = <2>; 88 gpio-controller; 89 }; 90 91 cbb-noc@2300000 { 92 compatible = "nvidia,tegra194-cbb-noc"; 93 reg = <0x02300000 0x1000>; 94 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 96 nvidia,axi2apb = <&axi2apb>; 97 nvidia,apbmisc = <&apbmisc>; 98 status = "okay"; 99 }; 100 101 axi2apb: axi2apb@2390000 { 102 compatible = "nvidia,tegra194-axi2apb"; 103 reg = <0x2390000 0x1000>, 104 <0x23a0000 0x1000>, 105 <0x23b0000 0x1000>, 106 <0x23c0000 0x1000>, 107 <0x23d0000 0x1000>, 108 <0x23e0000 0x1000>; 109 status = "okay"; 110 }; 111 112 ethernet@2490000 { 113 compatible = "nvidia,tegra194-eqos", 114 "nvidia,tegra186-eqos", 115 "snps,dwc-qos-ethernet-4.10"; 116 reg = <0x02490000 0x10000>; 117 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 118 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 119 <&bpmp TEGRA194_CLK_EQOS_AXI>, 120 <&bpmp TEGRA194_CLK_EQOS_RX>, 121 <&bpmp TEGRA194_CLK_EQOS_TX>, 122 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 123 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 124 resets = <&bpmp TEGRA194_RESET_EQOS>; 125 reset-names = "eqos"; 126 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 127 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 128 interconnect-names = "dma-mem", "write"; 129 iommus = <&smmu TEGRA194_SID_EQOS>; 130 status = "disabled"; 131 132 snps,write-requests = <1>; 133 snps,read-requests = <3>; 134 snps,burst-map = <0x7>; 135 snps,txpbl = <16>; 136 snps,rxpbl = <8>; 137 }; 138 139 gpcdma: dma-controller@2600000 { 140 compatible = "nvidia,tegra194-gpcdma", 141 "nvidia,tegra186-gpcdma"; 142 reg = <0x2600000 0x210000>; 143 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 144 reset-names = "gpcdma"; 145 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 176 #dma-cells = <1>; 177 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 178 dma-coherent; 179 status = "okay"; 180 }; 181 182 aconnect@2900000 { 183 compatible = "nvidia,tegra194-aconnect", 184 "nvidia,tegra210-aconnect"; 185 clocks = <&bpmp TEGRA194_CLK_APE>, 186 <&bpmp TEGRA194_CLK_APB2APE>; 187 clock-names = "ape", "apb2ape"; 188 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 ranges = <0x02900000 0x02900000 0x200000>; 192 status = "disabled"; 193 194 adma: dma-controller@2930000 { 195 compatible = "nvidia,tegra194-adma", 196 "nvidia,tegra186-adma"; 197 reg = <0x02930000 0x20000>; 198 interrupt-parent = <&agic>; 199 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 231 #dma-cells = <1>; 232 clocks = <&bpmp TEGRA194_CLK_AHUB>; 233 clock-names = "d_audio"; 234 status = "disabled"; 235 }; 236 237 agic: interrupt-controller@2a40000 { 238 compatible = "nvidia,tegra194-agic", 239 "nvidia,tegra210-agic"; 240 #interrupt-cells = <3>; 241 interrupt-controller; 242 reg = <0x02a41000 0x1000>, 243 <0x02a42000 0x2000>; 244 interrupts = <GIC_SPI 145 245 (GIC_CPU_MASK_SIMPLE(4) | 246 IRQ_TYPE_LEVEL_HIGH)>; 247 clocks = <&bpmp TEGRA194_CLK_APE>; 248 clock-names = "clk"; 249 status = "disabled"; 250 }; 251 252 tegra_ahub: ahub@2900800 { 253 compatible = "nvidia,tegra194-ahub", 254 "nvidia,tegra186-ahub"; 255 reg = <0x02900800 0x800>; 256 clocks = <&bpmp TEGRA194_CLK_AHUB>; 257 clock-names = "ahub"; 258 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 259 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 ranges = <0x02900800 0x02900800 0x11800>; 263 status = "disabled"; 264 265 tegra_admaif: admaif@290f000 { 266 compatible = "nvidia,tegra194-admaif", 267 "nvidia,tegra186-admaif"; 268 reg = <0x0290f000 0x1000>; 269 dmas = <&adma 1>, <&adma 1>, 270 <&adma 2>, <&adma 2>, 271 <&adma 3>, <&adma 3>, 272 <&adma 4>, <&adma 4>, 273 <&adma 5>, <&adma 5>, 274 <&adma 6>, <&adma 6>, 275 <&adma 7>, <&adma 7>, 276 <&adma 8>, <&adma 8>, 277 <&adma 9>, <&adma 9>, 278 <&adma 10>, <&adma 10>, 279 <&adma 11>, <&adma 11>, 280 <&adma 12>, <&adma 12>, 281 <&adma 13>, <&adma 13>, 282 <&adma 14>, <&adma 14>, 283 <&adma 15>, <&adma 15>, 284 <&adma 16>, <&adma 16>, 285 <&adma 17>, <&adma 17>, 286 <&adma 18>, <&adma 18>, 287 <&adma 19>, <&adma 19>, 288 <&adma 20>, <&adma 20>; 289 dma-names = "rx1", "tx1", 290 "rx2", "tx2", 291 "rx3", "tx3", 292 "rx4", "tx4", 293 "rx5", "tx5", 294 "rx6", "tx6", 295 "rx7", "tx7", 296 "rx8", "tx8", 297 "rx9", "tx9", 298 "rx10", "tx10", 299 "rx11", "tx11", 300 "rx12", "tx12", 301 "rx13", "tx13", 302 "rx14", "tx14", 303 "rx15", "tx15", 304 "rx16", "tx16", 305 "rx17", "tx17", 306 "rx18", "tx18", 307 "rx19", "tx19", 308 "rx20", "tx20"; 309 status = "disabled"; 310 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 311 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 312 interconnect-names = "dma-mem", "write"; 313 iommus = <&smmu TEGRA194_SID_APE>; 314 }; 315 316 tegra_i2s1: i2s@2901000 { 317 compatible = "nvidia,tegra194-i2s", 318 "nvidia,tegra210-i2s"; 319 reg = <0x2901000 0x100>; 320 clocks = <&bpmp TEGRA194_CLK_I2S1>, 321 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 322 clock-names = "i2s", "sync_input"; 323 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 324 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 325 assigned-clock-rates = <1536000>; 326 sound-name-prefix = "I2S1"; 327 status = "disabled"; 328 }; 329 330 tegra_i2s2: i2s@2901100 { 331 compatible = "nvidia,tegra194-i2s", 332 "nvidia,tegra210-i2s"; 333 reg = <0x2901100 0x100>; 334 clocks = <&bpmp TEGRA194_CLK_I2S2>, 335 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 336 clock-names = "i2s", "sync_input"; 337 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 338 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 339 assigned-clock-rates = <1536000>; 340 sound-name-prefix = "I2S2"; 341 status = "disabled"; 342 }; 343 344 tegra_i2s3: i2s@2901200 { 345 compatible = "nvidia,tegra194-i2s", 346 "nvidia,tegra210-i2s"; 347 reg = <0x2901200 0x100>; 348 clocks = <&bpmp TEGRA194_CLK_I2S3>, 349 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 350 clock-names = "i2s", "sync_input"; 351 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 352 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 353 assigned-clock-rates = <1536000>; 354 sound-name-prefix = "I2S3"; 355 status = "disabled"; 356 }; 357 358 tegra_i2s4: i2s@2901300 { 359 compatible = "nvidia,tegra194-i2s", 360 "nvidia,tegra210-i2s"; 361 reg = <0x2901300 0x100>; 362 clocks = <&bpmp TEGRA194_CLK_I2S4>, 363 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 364 clock-names = "i2s", "sync_input"; 365 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 366 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 367 assigned-clock-rates = <1536000>; 368 sound-name-prefix = "I2S4"; 369 status = "disabled"; 370 }; 371 372 tegra_i2s5: i2s@2901400 { 373 compatible = "nvidia,tegra194-i2s", 374 "nvidia,tegra210-i2s"; 375 reg = <0x2901400 0x100>; 376 clocks = <&bpmp TEGRA194_CLK_I2S5>, 377 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 378 clock-names = "i2s", "sync_input"; 379 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 380 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 381 assigned-clock-rates = <1536000>; 382 sound-name-prefix = "I2S5"; 383 status = "disabled"; 384 }; 385 386 tegra_i2s6: i2s@2901500 { 387 compatible = "nvidia,tegra194-i2s", 388 "nvidia,tegra210-i2s"; 389 reg = <0x2901500 0x100>; 390 clocks = <&bpmp TEGRA194_CLK_I2S6>, 391 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 392 clock-names = "i2s", "sync_input"; 393 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 394 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 395 assigned-clock-rates = <1536000>; 396 sound-name-prefix = "I2S6"; 397 status = "disabled"; 398 }; 399 400 tegra_dmic1: dmic@2904000 { 401 compatible = "nvidia,tegra194-dmic", 402 "nvidia,tegra210-dmic"; 403 reg = <0x2904000 0x100>; 404 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 405 clock-names = "dmic"; 406 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 407 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 408 assigned-clock-rates = <3072000>; 409 sound-name-prefix = "DMIC1"; 410 status = "disabled"; 411 }; 412 413 tegra_dmic2: dmic@2904100 { 414 compatible = "nvidia,tegra194-dmic", 415 "nvidia,tegra210-dmic"; 416 reg = <0x2904100 0x100>; 417 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 418 clock-names = "dmic"; 419 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 420 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 421 assigned-clock-rates = <3072000>; 422 sound-name-prefix = "DMIC2"; 423 status = "disabled"; 424 }; 425 426 tegra_dmic3: dmic@2904200 { 427 compatible = "nvidia,tegra194-dmic", 428 "nvidia,tegra210-dmic"; 429 reg = <0x2904200 0x100>; 430 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 431 clock-names = "dmic"; 432 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 433 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 434 assigned-clock-rates = <3072000>; 435 sound-name-prefix = "DMIC3"; 436 status = "disabled"; 437 }; 438 439 tegra_dmic4: dmic@2904300 { 440 compatible = "nvidia,tegra194-dmic", 441 "nvidia,tegra210-dmic"; 442 reg = <0x2904300 0x100>; 443 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 444 clock-names = "dmic"; 445 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 446 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 447 assigned-clock-rates = <3072000>; 448 sound-name-prefix = "DMIC4"; 449 status = "disabled"; 450 }; 451 452 tegra_dspk1: dspk@2905000 { 453 compatible = "nvidia,tegra194-dspk", 454 "nvidia,tegra186-dspk"; 455 reg = <0x2905000 0x100>; 456 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 457 clock-names = "dspk"; 458 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 459 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 460 assigned-clock-rates = <12288000>; 461 sound-name-prefix = "DSPK1"; 462 status = "disabled"; 463 }; 464 465 tegra_dspk2: dspk@2905100 { 466 compatible = "nvidia,tegra194-dspk", 467 "nvidia,tegra186-dspk"; 468 reg = <0x2905100 0x100>; 469 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 470 clock-names = "dspk"; 471 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 472 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 473 assigned-clock-rates = <12288000>; 474 sound-name-prefix = "DSPK2"; 475 status = "disabled"; 476 }; 477 478 tegra_sfc1: sfc@2902000 { 479 compatible = "nvidia,tegra194-sfc", 480 "nvidia,tegra210-sfc"; 481 reg = <0x2902000 0x200>; 482 sound-name-prefix = "SFC1"; 483 status = "disabled"; 484 }; 485 486 tegra_sfc2: sfc@2902200 { 487 compatible = "nvidia,tegra194-sfc", 488 "nvidia,tegra210-sfc"; 489 reg = <0x2902200 0x200>; 490 sound-name-prefix = "SFC2"; 491 status = "disabled"; 492 }; 493 494 tegra_sfc3: sfc@2902400 { 495 compatible = "nvidia,tegra194-sfc", 496 "nvidia,tegra210-sfc"; 497 reg = <0x2902400 0x200>; 498 sound-name-prefix = "SFC3"; 499 status = "disabled"; 500 }; 501 502 tegra_sfc4: sfc@2902600 { 503 compatible = "nvidia,tegra194-sfc", 504 "nvidia,tegra210-sfc"; 505 reg = <0x2902600 0x200>; 506 sound-name-prefix = "SFC4"; 507 status = "disabled"; 508 }; 509 510 tegra_mvc1: mvc@290a000 { 511 compatible = "nvidia,tegra194-mvc", 512 "nvidia,tegra210-mvc"; 513 reg = <0x290a000 0x200>; 514 sound-name-prefix = "MVC1"; 515 status = "disabled"; 516 }; 517 518 tegra_mvc2: mvc@290a200 { 519 compatible = "nvidia,tegra194-mvc", 520 "nvidia,tegra210-mvc"; 521 reg = <0x290a200 0x200>; 522 sound-name-prefix = "MVC2"; 523 status = "disabled"; 524 }; 525 526 tegra_amx1: amx@2903000 { 527 compatible = "nvidia,tegra194-amx"; 528 reg = <0x2903000 0x100>; 529 sound-name-prefix = "AMX1"; 530 status = "disabled"; 531 }; 532 533 tegra_amx2: amx@2903100 { 534 compatible = "nvidia,tegra194-amx"; 535 reg = <0x2903100 0x100>; 536 sound-name-prefix = "AMX2"; 537 status = "disabled"; 538 }; 539 540 tegra_amx3: amx@2903200 { 541 compatible = "nvidia,tegra194-amx"; 542 reg = <0x2903200 0x100>; 543 sound-name-prefix = "AMX3"; 544 status = "disabled"; 545 }; 546 547 tegra_amx4: amx@2903300 { 548 compatible = "nvidia,tegra194-amx"; 549 reg = <0x2903300 0x100>; 550 sound-name-prefix = "AMX4"; 551 status = "disabled"; 552 }; 553 554 tegra_adx1: adx@2903800 { 555 compatible = "nvidia,tegra194-adx", 556 "nvidia,tegra210-adx"; 557 reg = <0x2903800 0x100>; 558 sound-name-prefix = "ADX1"; 559 status = "disabled"; 560 }; 561 562 tegra_adx2: adx@2903900 { 563 compatible = "nvidia,tegra194-adx", 564 "nvidia,tegra210-adx"; 565 reg = <0x2903900 0x100>; 566 sound-name-prefix = "ADX2"; 567 status = "disabled"; 568 }; 569 570 tegra_adx3: adx@2903a00 { 571 compatible = "nvidia,tegra194-adx", 572 "nvidia,tegra210-adx"; 573 reg = <0x2903a00 0x100>; 574 sound-name-prefix = "ADX3"; 575 status = "disabled"; 576 }; 577 578 tegra_adx4: adx@2903b00 { 579 compatible = "nvidia,tegra194-adx", 580 "nvidia,tegra210-adx"; 581 reg = <0x2903b00 0x100>; 582 sound-name-prefix = "ADX4"; 583 status = "disabled"; 584 }; 585 586 tegra_ope1: processing-engine@2908000 { 587 compatible = "nvidia,tegra194-ope", 588 "nvidia,tegra210-ope"; 589 reg = <0x2908000 0x100>; 590 #address-cells = <1>; 591 #size-cells = <1>; 592 ranges; 593 sound-name-prefix = "OPE1"; 594 status = "disabled"; 595 596 equalizer@2908100 { 597 compatible = "nvidia,tegra194-peq", 598 "nvidia,tegra210-peq"; 599 reg = <0x2908100 0x100>; 600 }; 601 602 dynamic-range-compressor@2908200 { 603 compatible = "nvidia,tegra194-mbdrc", 604 "nvidia,tegra210-mbdrc"; 605 reg = <0x2908200 0x200>; 606 }; 607 }; 608 609 tegra_amixer: amixer@290bb00 { 610 compatible = "nvidia,tegra194-amixer", 611 "nvidia,tegra210-amixer"; 612 reg = <0x290bb00 0x800>; 613 sound-name-prefix = "MIXER1"; 614 status = "disabled"; 615 }; 616 617 tegra_asrc: asrc@2910000 { 618 compatible = "nvidia,tegra194-asrc", 619 "nvidia,tegra186-asrc"; 620 reg = <0x2910000 0x2000>; 621 sound-name-prefix = "ASRC1"; 622 status = "disabled"; 623 }; 624 }; 625 }; 626 627 pinmux: pinmux@2430000 { 628 compatible = "nvidia,tegra194-pinmux"; 629 reg = <0x2430000 0x17000>, 630 <0xc300000 0x4000>; 631 632 status = "okay"; 633 634 pex_rst_c5_out_state: pex_rst_c5_out { 635 pex_rst { 636 nvidia,pins = "pex_l5_rst_n_pgg1"; 637 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 638 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 639 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 640 nvidia,tristate = <TEGRA_PIN_DISABLE>; 641 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 642 }; 643 }; 644 645 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 646 clkreq { 647 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 648 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 649 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 650 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 651 nvidia,tristate = <TEGRA_PIN_DISABLE>; 652 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 653 }; 654 }; 655 }; 656 657 mc: memory-controller@2c00000 { 658 compatible = "nvidia,tegra194-mc"; 659 reg = <0x02c00000 0x10000>, /* MC-SID */ 660 <0x02c10000 0x10000>, /* MC Broadcast*/ 661 <0x02c20000 0x10000>, /* MC0 */ 662 <0x02c30000 0x10000>, /* MC1 */ 663 <0x02c40000 0x10000>, /* MC2 */ 664 <0x02c50000 0x10000>, /* MC3 */ 665 <0x02b80000 0x10000>, /* MC4 */ 666 <0x02b90000 0x10000>, /* MC5 */ 667 <0x02ba0000 0x10000>, /* MC6 */ 668 <0x02bb0000 0x10000>, /* MC7 */ 669 <0x01700000 0x10000>, /* MC8 */ 670 <0x01710000 0x10000>, /* MC9 */ 671 <0x01720000 0x10000>, /* MC10 */ 672 <0x01730000 0x10000>, /* MC11 */ 673 <0x01740000 0x10000>, /* MC12 */ 674 <0x01750000 0x10000>, /* MC13 */ 675 <0x01760000 0x10000>, /* MC14 */ 676 <0x01770000 0x10000>; /* MC15 */ 677 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 678 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 679 "ch11", "ch12", "ch13", "ch14", "ch15"; 680 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 681 #interconnect-cells = <1>; 682 status = "disabled"; 683 684 #address-cells = <2>; 685 #size-cells = <2>; 686 687 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 688 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 689 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 690 691 /* 692 * Bit 39 of addresses passing through the memory 693 * controller selects the XBAR format used when memory 694 * is accessed. This is used to transparently access 695 * memory in the XBAR format used by the discrete GPU 696 * (bit 39 set) or Tegra (bit 39 clear). 697 * 698 * As a consequence, the operating system must ensure 699 * that bit 39 is never used implicitly, for example 700 * via an I/O virtual address mapping of an IOMMU. If 701 * devices require access to the XBAR switch, their 702 * drivers must set this bit explicitly. 703 * 704 * Limit the DMA range for memory clients to [38:0]. 705 */ 706 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 707 708 emc: external-memory-controller@2c60000 { 709 compatible = "nvidia,tegra194-emc"; 710 reg = <0x0 0x02c60000 0x0 0x90000>, 711 <0x0 0x01780000 0x0 0x80000>; 712 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&bpmp TEGRA194_CLK_EMC>; 714 clock-names = "emc"; 715 716 #interconnect-cells = <0>; 717 718 nvidia,bpmp = <&bpmp>; 719 }; 720 }; 721 722 uarta: serial@3100000 { 723 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 724 reg = <0x03100000 0x40>; 725 reg-shift = <2>; 726 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&bpmp TEGRA194_CLK_UARTA>; 728 clock-names = "serial"; 729 resets = <&bpmp TEGRA194_RESET_UARTA>; 730 reset-names = "serial"; 731 status = "disabled"; 732 }; 733 734 uartb: serial@3110000 { 735 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 736 reg = <0x03110000 0x40>; 737 reg-shift = <2>; 738 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&bpmp TEGRA194_CLK_UARTB>; 740 clock-names = "serial"; 741 resets = <&bpmp TEGRA194_RESET_UARTB>; 742 reset-names = "serial"; 743 status = "disabled"; 744 }; 745 746 uartd: serial@3130000 { 747 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 748 reg = <0x03130000 0x40>; 749 reg-shift = <2>; 750 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&bpmp TEGRA194_CLK_UARTD>; 752 clock-names = "serial"; 753 resets = <&bpmp TEGRA194_RESET_UARTD>; 754 reset-names = "serial"; 755 status = "disabled"; 756 }; 757 758 uarte: serial@3140000 { 759 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 760 reg = <0x03140000 0x40>; 761 reg-shift = <2>; 762 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&bpmp TEGRA194_CLK_UARTE>; 764 clock-names = "serial"; 765 resets = <&bpmp TEGRA194_RESET_UARTE>; 766 reset-names = "serial"; 767 status = "disabled"; 768 }; 769 770 uartf: serial@3150000 { 771 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 772 reg = <0x03150000 0x40>; 773 reg-shift = <2>; 774 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&bpmp TEGRA194_CLK_UARTF>; 776 clock-names = "serial"; 777 resets = <&bpmp TEGRA194_RESET_UARTF>; 778 reset-names = "serial"; 779 status = "disabled"; 780 }; 781 782 gen1_i2c: i2c@3160000 { 783 compatible = "nvidia,tegra194-i2c"; 784 reg = <0x03160000 0x10000>; 785 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 clocks = <&bpmp TEGRA194_CLK_I2C1>; 789 clock-names = "div-clk"; 790 resets = <&bpmp TEGRA194_RESET_I2C1>; 791 reset-names = "i2c"; 792 status = "disabled"; 793 }; 794 795 uarth: serial@3170000 { 796 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 797 reg = <0x03170000 0x40>; 798 reg-shift = <2>; 799 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 800 clocks = <&bpmp TEGRA194_CLK_UARTH>; 801 clock-names = "serial"; 802 resets = <&bpmp TEGRA194_RESET_UARTH>; 803 reset-names = "serial"; 804 status = "disabled"; 805 }; 806 807 cam_i2c: i2c@3180000 { 808 compatible = "nvidia,tegra194-i2c"; 809 reg = <0x03180000 0x10000>; 810 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 clocks = <&bpmp TEGRA194_CLK_I2C3>; 814 clock-names = "div-clk"; 815 resets = <&bpmp TEGRA194_RESET_I2C3>; 816 reset-names = "i2c"; 817 status = "disabled"; 818 }; 819 820 /* shares pads with dpaux1 */ 821 dp_aux_ch1_i2c: i2c@3190000 { 822 compatible = "nvidia,tegra194-i2c"; 823 reg = <0x03190000 0x10000>; 824 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 clocks = <&bpmp TEGRA194_CLK_I2C4>; 828 clock-names = "div-clk"; 829 resets = <&bpmp TEGRA194_RESET_I2C4>; 830 reset-names = "i2c"; 831 pinctrl-0 = <&state_dpaux1_i2c>; 832 pinctrl-1 = <&state_dpaux1_off>; 833 pinctrl-names = "default", "idle"; 834 status = "disabled"; 835 }; 836 837 /* shares pads with dpaux0 */ 838 dp_aux_ch0_i2c: i2c@31b0000 { 839 compatible = "nvidia,tegra194-i2c"; 840 reg = <0x031b0000 0x10000>; 841 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 clocks = <&bpmp TEGRA194_CLK_I2C6>; 845 clock-names = "div-clk"; 846 resets = <&bpmp TEGRA194_RESET_I2C6>; 847 reset-names = "i2c"; 848 pinctrl-0 = <&state_dpaux0_i2c>; 849 pinctrl-1 = <&state_dpaux0_off>; 850 pinctrl-names = "default", "idle"; 851 status = "disabled"; 852 }; 853 854 /* shares pads with dpaux2 */ 855 dp_aux_ch2_i2c: i2c@31c0000 { 856 compatible = "nvidia,tegra194-i2c"; 857 reg = <0x031c0000 0x10000>; 858 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 clocks = <&bpmp TEGRA194_CLK_I2C7>; 862 clock-names = "div-clk"; 863 resets = <&bpmp TEGRA194_RESET_I2C7>; 864 reset-names = "i2c"; 865 pinctrl-0 = <&state_dpaux2_i2c>; 866 pinctrl-1 = <&state_dpaux2_off>; 867 pinctrl-names = "default", "idle"; 868 status = "disabled"; 869 }; 870 871 /* shares pads with dpaux3 */ 872 dp_aux_ch3_i2c: i2c@31e0000 { 873 compatible = "nvidia,tegra194-i2c"; 874 reg = <0x031e0000 0x10000>; 875 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 876 #address-cells = <1>; 877 #size-cells = <0>; 878 clocks = <&bpmp TEGRA194_CLK_I2C9>; 879 clock-names = "div-clk"; 880 resets = <&bpmp TEGRA194_RESET_I2C9>; 881 reset-names = "i2c"; 882 pinctrl-0 = <&state_dpaux3_i2c>; 883 pinctrl-1 = <&state_dpaux3_off>; 884 pinctrl-names = "default", "idle"; 885 status = "disabled"; 886 }; 887 888 spi@3270000 { 889 compatible = "nvidia,tegra194-qspi"; 890 reg = <0x3270000 0x1000>; 891 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 895 <&bpmp TEGRA194_CLK_QSPI0_PM>; 896 clock-names = "qspi", "qspi_out"; 897 resets = <&bpmp TEGRA194_RESET_QSPI0>; 898 reset-names = "qspi"; 899 status = "disabled"; 900 }; 901 902 spi@3300000 { 903 compatible = "nvidia,tegra194-qspi"; 904 reg = <0x3300000 0x1000>; 905 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 909 <&bpmp TEGRA194_CLK_QSPI1_PM>; 910 clock-names = "qspi", "qspi_out"; 911 resets = <&bpmp TEGRA194_RESET_QSPI1>; 912 reset-names = "qspi"; 913 status = "disabled"; 914 }; 915 916 pwm1: pwm@3280000 { 917 compatible = "nvidia,tegra194-pwm", 918 "nvidia,tegra186-pwm"; 919 reg = <0x3280000 0x10000>; 920 clocks = <&bpmp TEGRA194_CLK_PWM1>; 921 clock-names = "pwm"; 922 resets = <&bpmp TEGRA194_RESET_PWM1>; 923 reset-names = "pwm"; 924 status = "disabled"; 925 #pwm-cells = <2>; 926 }; 927 928 pwm2: pwm@3290000 { 929 compatible = "nvidia,tegra194-pwm", 930 "nvidia,tegra186-pwm"; 931 reg = <0x3290000 0x10000>; 932 clocks = <&bpmp TEGRA194_CLK_PWM2>; 933 clock-names = "pwm"; 934 resets = <&bpmp TEGRA194_RESET_PWM2>; 935 reset-names = "pwm"; 936 status = "disabled"; 937 #pwm-cells = <2>; 938 }; 939 940 pwm3: pwm@32a0000 { 941 compatible = "nvidia,tegra194-pwm", 942 "nvidia,tegra186-pwm"; 943 reg = <0x32a0000 0x10000>; 944 clocks = <&bpmp TEGRA194_CLK_PWM3>; 945 clock-names = "pwm"; 946 resets = <&bpmp TEGRA194_RESET_PWM3>; 947 reset-names = "pwm"; 948 status = "disabled"; 949 #pwm-cells = <2>; 950 }; 951 952 pwm5: pwm@32c0000 { 953 compatible = "nvidia,tegra194-pwm", 954 "nvidia,tegra186-pwm"; 955 reg = <0x32c0000 0x10000>; 956 clocks = <&bpmp TEGRA194_CLK_PWM5>; 957 clock-names = "pwm"; 958 resets = <&bpmp TEGRA194_RESET_PWM5>; 959 reset-names = "pwm"; 960 status = "disabled"; 961 #pwm-cells = <2>; 962 }; 963 964 pwm6: pwm@32d0000 { 965 compatible = "nvidia,tegra194-pwm", 966 "nvidia,tegra186-pwm"; 967 reg = <0x32d0000 0x10000>; 968 clocks = <&bpmp TEGRA194_CLK_PWM6>; 969 clock-names = "pwm"; 970 resets = <&bpmp TEGRA194_RESET_PWM6>; 971 reset-names = "pwm"; 972 status = "disabled"; 973 #pwm-cells = <2>; 974 }; 975 976 pwm7: pwm@32e0000 { 977 compatible = "nvidia,tegra194-pwm", 978 "nvidia,tegra186-pwm"; 979 reg = <0x32e0000 0x10000>; 980 clocks = <&bpmp TEGRA194_CLK_PWM7>; 981 clock-names = "pwm"; 982 resets = <&bpmp TEGRA194_RESET_PWM7>; 983 reset-names = "pwm"; 984 status = "disabled"; 985 #pwm-cells = <2>; 986 }; 987 988 pwm8: pwm@32f0000 { 989 compatible = "nvidia,tegra194-pwm", 990 "nvidia,tegra186-pwm"; 991 reg = <0x32f0000 0x10000>; 992 clocks = <&bpmp TEGRA194_CLK_PWM8>; 993 clock-names = "pwm"; 994 resets = <&bpmp TEGRA194_RESET_PWM8>; 995 reset-names = "pwm"; 996 status = "disabled"; 997 #pwm-cells = <2>; 998 }; 999 1000 sdmmc1: mmc@3400000 { 1001 compatible = "nvidia,tegra194-sdhci"; 1002 reg = <0x03400000 0x10000>; 1003 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1005 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1006 clock-names = "sdhci", "tmclk"; 1007 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1008 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1009 assigned-clock-parents = 1010 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1011 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1012 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 1013 reset-names = "sdhci"; 1014 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1015 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1016 interconnect-names = "dma-mem", "write"; 1017 iommus = <&smmu TEGRA194_SID_SDMMC1>; 1018 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1019 pinctrl-0 = <&sdmmc1_3v3>; 1020 pinctrl-1 = <&sdmmc1_1v8>; 1021 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 1022 <0x07>; 1023 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1024 <0x07>; 1025 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1026 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1027 <0x07>; 1028 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1029 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1030 nvidia,default-tap = <0x9>; 1031 nvidia,default-trim = <0x5>; 1032 sd-uhs-sdr25; 1033 sd-uhs-sdr50; 1034 sd-uhs-ddr50; 1035 sd-uhs-sdr104; 1036 status = "disabled"; 1037 }; 1038 1039 sdmmc3: mmc@3440000 { 1040 compatible = "nvidia,tegra194-sdhci"; 1041 reg = <0x03440000 0x10000>; 1042 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1043 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1044 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1045 clock-names = "sdhci", "tmclk"; 1046 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1047 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1048 assigned-clock-parents = 1049 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1050 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1051 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1052 reset-names = "sdhci"; 1053 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1054 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1055 interconnect-names = "dma-mem", "write"; 1056 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1057 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1058 pinctrl-0 = <&sdmmc3_3v3>; 1059 pinctrl-1 = <&sdmmc3_1v8>; 1060 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1061 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1062 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1063 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1064 <0x07>; 1065 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1066 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1067 <0x07>; 1068 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1069 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1070 nvidia,default-tap = <0x9>; 1071 nvidia,default-trim = <0x5>; 1072 sd-uhs-sdr25; 1073 sd-uhs-sdr50; 1074 sd-uhs-ddr50; 1075 sd-uhs-sdr104; 1076 status = "disabled"; 1077 }; 1078 1079 sdmmc4: mmc@3460000 { 1080 compatible = "nvidia,tegra194-sdhci"; 1081 reg = <0x03460000 0x10000>; 1082 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1084 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1085 clock-names = "sdhci", "tmclk"; 1086 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1087 <&bpmp TEGRA194_CLK_PLLC4>; 1088 assigned-clock-parents = 1089 <&bpmp TEGRA194_CLK_PLLC4>; 1090 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1091 reset-names = "sdhci"; 1092 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1093 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1094 interconnect-names = "dma-mem", "write"; 1095 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1096 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1097 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1098 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1099 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1100 <0x0a>; 1101 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1102 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1103 <0x0a>; 1104 nvidia,default-tap = <0x8>; 1105 nvidia,default-trim = <0x14>; 1106 nvidia,dqs-trim = <40>; 1107 cap-mmc-highspeed; 1108 mmc-ddr-1_8v; 1109 mmc-hs200-1_8v; 1110 mmc-hs400-1_8v; 1111 mmc-hs400-enhanced-strobe; 1112 supports-cqe; 1113 status = "disabled"; 1114 }; 1115 1116 hda@3510000 { 1117 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 1118 reg = <0x3510000 0x10000>; 1119 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1120 clocks = <&bpmp TEGRA194_CLK_HDA>, 1121 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1122 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1123 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1124 resets = <&bpmp TEGRA194_RESET_HDA>, 1125 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1126 reset-names = "hda", "hda2hdmi"; 1127 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1128 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1129 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1130 interconnect-names = "dma-mem", "write"; 1131 iommus = <&smmu TEGRA194_SID_HDA>; 1132 status = "disabled"; 1133 }; 1134 1135 xusb_padctl: padctl@3520000 { 1136 compatible = "nvidia,tegra194-xusb-padctl"; 1137 reg = <0x03520000 0x1000>, 1138 <0x03540000 0x1000>; 1139 reg-names = "padctl", "ao"; 1140 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1141 1142 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1143 reset-names = "padctl"; 1144 1145 status = "disabled"; 1146 1147 pads { 1148 usb2 { 1149 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1150 clock-names = "trk"; 1151 1152 lanes { 1153 usb2-0 { 1154 nvidia,function = "xusb"; 1155 status = "disabled"; 1156 #phy-cells = <0>; 1157 }; 1158 1159 usb2-1 { 1160 nvidia,function = "xusb"; 1161 status = "disabled"; 1162 #phy-cells = <0>; 1163 }; 1164 1165 usb2-2 { 1166 nvidia,function = "xusb"; 1167 status = "disabled"; 1168 #phy-cells = <0>; 1169 }; 1170 1171 usb2-3 { 1172 nvidia,function = "xusb"; 1173 status = "disabled"; 1174 #phy-cells = <0>; 1175 }; 1176 }; 1177 }; 1178 1179 usb3 { 1180 lanes { 1181 usb3-0 { 1182 nvidia,function = "xusb"; 1183 status = "disabled"; 1184 #phy-cells = <0>; 1185 }; 1186 1187 usb3-1 { 1188 nvidia,function = "xusb"; 1189 status = "disabled"; 1190 #phy-cells = <0>; 1191 }; 1192 1193 usb3-2 { 1194 nvidia,function = "xusb"; 1195 status = "disabled"; 1196 #phy-cells = <0>; 1197 }; 1198 1199 usb3-3 { 1200 nvidia,function = "xusb"; 1201 status = "disabled"; 1202 #phy-cells = <0>; 1203 }; 1204 }; 1205 }; 1206 }; 1207 1208 ports { 1209 usb2-0 { 1210 status = "disabled"; 1211 }; 1212 1213 usb2-1 { 1214 status = "disabled"; 1215 }; 1216 1217 usb2-2 { 1218 status = "disabled"; 1219 }; 1220 1221 usb2-3 { 1222 status = "disabled"; 1223 }; 1224 1225 usb3-0 { 1226 status = "disabled"; 1227 }; 1228 1229 usb3-1 { 1230 status = "disabled"; 1231 }; 1232 1233 usb3-2 { 1234 status = "disabled"; 1235 }; 1236 1237 usb3-3 { 1238 status = "disabled"; 1239 }; 1240 }; 1241 }; 1242 1243 usb@3550000 { 1244 compatible = "nvidia,tegra194-xudc"; 1245 reg = <0x03550000 0x8000>, 1246 <0x03558000 0x1000>; 1247 reg-names = "base", "fpci"; 1248 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1249 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1250 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1251 <&bpmp TEGRA194_CLK_XUSB_SS>, 1252 <&bpmp TEGRA194_CLK_XUSB_FS>; 1253 clock-names = "dev", "ss", "ss_src", "fs_src"; 1254 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1255 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1256 interconnect-names = "dma-mem", "write"; 1257 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1258 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1259 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1260 power-domain-names = "dev", "ss"; 1261 nvidia,xusb-padctl = <&xusb_padctl>; 1262 status = "disabled"; 1263 }; 1264 1265 usb@3610000 { 1266 compatible = "nvidia,tegra194-xusb"; 1267 reg = <0x03610000 0x40000>, 1268 <0x03600000 0x10000>; 1269 reg-names = "hcd", "fpci"; 1270 1271 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1273 1274 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1275 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1276 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1277 <&bpmp TEGRA194_CLK_XUSB_SS>, 1278 <&bpmp TEGRA194_CLK_CLK_M>, 1279 <&bpmp TEGRA194_CLK_XUSB_FS>, 1280 <&bpmp TEGRA194_CLK_UTMIPLL>, 1281 <&bpmp TEGRA194_CLK_CLK_M>, 1282 <&bpmp TEGRA194_CLK_PLLE>; 1283 clock-names = "xusb_host", "xusb_falcon_src", 1284 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1285 "xusb_fs_src", "pll_u_480m", "clk_m", 1286 "pll_e"; 1287 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1288 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1289 interconnect-names = "dma-mem", "write"; 1290 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1291 1292 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1293 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1294 power-domain-names = "xusb_host", "xusb_ss"; 1295 1296 nvidia,xusb-padctl = <&xusb_padctl>; 1297 status = "disabled"; 1298 }; 1299 1300 fuse@3820000 { 1301 compatible = "nvidia,tegra194-efuse"; 1302 reg = <0x03820000 0x10000>; 1303 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1304 clock-names = "fuse"; 1305 }; 1306 1307 gic: interrupt-controller@3881000 { 1308 compatible = "arm,gic-400"; 1309 #interrupt-cells = <3>; 1310 interrupt-controller; 1311 reg = <0x03881000 0x1000>, 1312 <0x03882000 0x2000>, 1313 <0x03884000 0x2000>, 1314 <0x03886000 0x2000>; 1315 interrupts = <GIC_PPI 9 1316 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1317 interrupt-parent = <&gic>; 1318 }; 1319 1320 cec@3960000 { 1321 compatible = "nvidia,tegra194-cec"; 1322 reg = <0x03960000 0x10000>; 1323 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1324 clocks = <&bpmp TEGRA194_CLK_CEC>; 1325 clock-names = "cec"; 1326 status = "disabled"; 1327 }; 1328 1329 hsp_top0: hsp@3c00000 { 1330 compatible = "nvidia,tegra194-hsp"; 1331 reg = <0x03c00000 0xa0000>; 1332 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1341 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1342 "shared3", "shared4", "shared5", "shared6", 1343 "shared7"; 1344 #mbox-cells = <2>; 1345 }; 1346 1347 p2u_hsio_0: phy@3e10000 { 1348 compatible = "nvidia,tegra194-p2u"; 1349 reg = <0x03e10000 0x10000>; 1350 reg-names = "ctl"; 1351 1352 #phy-cells = <0>; 1353 }; 1354 1355 p2u_hsio_1: phy@3e20000 { 1356 compatible = "nvidia,tegra194-p2u"; 1357 reg = <0x03e20000 0x10000>; 1358 reg-names = "ctl"; 1359 1360 #phy-cells = <0>; 1361 }; 1362 1363 p2u_hsio_2: phy@3e30000 { 1364 compatible = "nvidia,tegra194-p2u"; 1365 reg = <0x03e30000 0x10000>; 1366 reg-names = "ctl"; 1367 1368 #phy-cells = <0>; 1369 }; 1370 1371 p2u_hsio_3: phy@3e40000 { 1372 compatible = "nvidia,tegra194-p2u"; 1373 reg = <0x03e40000 0x10000>; 1374 reg-names = "ctl"; 1375 1376 #phy-cells = <0>; 1377 }; 1378 1379 p2u_hsio_4: phy@3e50000 { 1380 compatible = "nvidia,tegra194-p2u"; 1381 reg = <0x03e50000 0x10000>; 1382 reg-names = "ctl"; 1383 1384 #phy-cells = <0>; 1385 }; 1386 1387 p2u_hsio_5: phy@3e60000 { 1388 compatible = "nvidia,tegra194-p2u"; 1389 reg = <0x03e60000 0x10000>; 1390 reg-names = "ctl"; 1391 1392 #phy-cells = <0>; 1393 }; 1394 1395 p2u_hsio_6: phy@3e70000 { 1396 compatible = "nvidia,tegra194-p2u"; 1397 reg = <0x03e70000 0x10000>; 1398 reg-names = "ctl"; 1399 1400 #phy-cells = <0>; 1401 }; 1402 1403 p2u_hsio_7: phy@3e80000 { 1404 compatible = "nvidia,tegra194-p2u"; 1405 reg = <0x03e80000 0x10000>; 1406 reg-names = "ctl"; 1407 1408 #phy-cells = <0>; 1409 }; 1410 1411 p2u_hsio_8: phy@3e90000 { 1412 compatible = "nvidia,tegra194-p2u"; 1413 reg = <0x03e90000 0x10000>; 1414 reg-names = "ctl"; 1415 1416 #phy-cells = <0>; 1417 }; 1418 1419 p2u_hsio_9: phy@3ea0000 { 1420 compatible = "nvidia,tegra194-p2u"; 1421 reg = <0x03ea0000 0x10000>; 1422 reg-names = "ctl"; 1423 1424 #phy-cells = <0>; 1425 }; 1426 1427 p2u_nvhs_0: phy@3eb0000 { 1428 compatible = "nvidia,tegra194-p2u"; 1429 reg = <0x03eb0000 0x10000>; 1430 reg-names = "ctl"; 1431 1432 #phy-cells = <0>; 1433 }; 1434 1435 p2u_nvhs_1: phy@3ec0000 { 1436 compatible = "nvidia,tegra194-p2u"; 1437 reg = <0x03ec0000 0x10000>; 1438 reg-names = "ctl"; 1439 1440 #phy-cells = <0>; 1441 }; 1442 1443 p2u_nvhs_2: phy@3ed0000 { 1444 compatible = "nvidia,tegra194-p2u"; 1445 reg = <0x03ed0000 0x10000>; 1446 reg-names = "ctl"; 1447 1448 #phy-cells = <0>; 1449 }; 1450 1451 p2u_nvhs_3: phy@3ee0000 { 1452 compatible = "nvidia,tegra194-p2u"; 1453 reg = <0x03ee0000 0x10000>; 1454 reg-names = "ctl"; 1455 1456 #phy-cells = <0>; 1457 }; 1458 1459 p2u_nvhs_4: phy@3ef0000 { 1460 compatible = "nvidia,tegra194-p2u"; 1461 reg = <0x03ef0000 0x10000>; 1462 reg-names = "ctl"; 1463 1464 #phy-cells = <0>; 1465 }; 1466 1467 p2u_nvhs_5: phy@3f00000 { 1468 compatible = "nvidia,tegra194-p2u"; 1469 reg = <0x03f00000 0x10000>; 1470 reg-names = "ctl"; 1471 1472 #phy-cells = <0>; 1473 }; 1474 1475 p2u_nvhs_6: phy@3f10000 { 1476 compatible = "nvidia,tegra194-p2u"; 1477 reg = <0x03f10000 0x10000>; 1478 reg-names = "ctl"; 1479 1480 #phy-cells = <0>; 1481 }; 1482 1483 p2u_nvhs_7: phy@3f20000 { 1484 compatible = "nvidia,tegra194-p2u"; 1485 reg = <0x03f20000 0x10000>; 1486 reg-names = "ctl"; 1487 1488 #phy-cells = <0>; 1489 }; 1490 1491 p2u_hsio_10: phy@3f30000 { 1492 compatible = "nvidia,tegra194-p2u"; 1493 reg = <0x03f30000 0x10000>; 1494 reg-names = "ctl"; 1495 1496 #phy-cells = <0>; 1497 }; 1498 1499 p2u_hsio_11: phy@3f40000 { 1500 compatible = "nvidia,tegra194-p2u"; 1501 reg = <0x03f40000 0x10000>; 1502 reg-names = "ctl"; 1503 1504 #phy-cells = <0>; 1505 }; 1506 1507 sce-noc@b600000 { 1508 compatible = "nvidia,tegra194-sce-noc"; 1509 reg = <0xb600000 0x1000>; 1510 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1512 nvidia,axi2apb = <&axi2apb>; 1513 nvidia,apbmisc = <&apbmisc>; 1514 status = "okay"; 1515 }; 1516 1517 rce-noc@be00000 { 1518 compatible = "nvidia,tegra194-rce-noc"; 1519 reg = <0xbe00000 0x1000>; 1520 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1522 nvidia,axi2apb = <&axi2apb>; 1523 nvidia,apbmisc = <&apbmisc>; 1524 status = "okay"; 1525 }; 1526 1527 hsp_aon: hsp@c150000 { 1528 compatible = "nvidia,tegra194-hsp"; 1529 reg = <0x0c150000 0x90000>; 1530 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1534 /* 1535 * Shared interrupt 0 is routed only to AON/SPE, so 1536 * we only have 4 shared interrupts for the CCPLEX. 1537 */ 1538 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1539 #mbox-cells = <2>; 1540 }; 1541 1542 gen2_i2c: i2c@c240000 { 1543 compatible = "nvidia,tegra194-i2c"; 1544 reg = <0x0c240000 0x10000>; 1545 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1546 #address-cells = <1>; 1547 #size-cells = <0>; 1548 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1549 clock-names = "div-clk"; 1550 resets = <&bpmp TEGRA194_RESET_I2C2>; 1551 reset-names = "i2c"; 1552 status = "disabled"; 1553 }; 1554 1555 gen8_i2c: i2c@c250000 { 1556 compatible = "nvidia,tegra194-i2c"; 1557 reg = <0x0c250000 0x10000>; 1558 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1562 clock-names = "div-clk"; 1563 resets = <&bpmp TEGRA194_RESET_I2C8>; 1564 reset-names = "i2c"; 1565 status = "disabled"; 1566 }; 1567 1568 uartc: serial@c280000 { 1569 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1570 reg = <0x0c280000 0x40>; 1571 reg-shift = <2>; 1572 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1573 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1574 clock-names = "serial"; 1575 resets = <&bpmp TEGRA194_RESET_UARTC>; 1576 reset-names = "serial"; 1577 status = "disabled"; 1578 }; 1579 1580 uartg: serial@c290000 { 1581 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1582 reg = <0x0c290000 0x40>; 1583 reg-shift = <2>; 1584 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1585 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1586 clock-names = "serial"; 1587 resets = <&bpmp TEGRA194_RESET_UARTG>; 1588 reset-names = "serial"; 1589 status = "disabled"; 1590 }; 1591 1592 rtc: rtc@c2a0000 { 1593 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1594 reg = <0x0c2a0000 0x10000>; 1595 interrupt-parent = <&pmc>; 1596 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1597 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1598 clock-names = "rtc"; 1599 status = "disabled"; 1600 }; 1601 1602 gpio_aon: gpio@c2f0000 { 1603 compatible = "nvidia,tegra194-gpio-aon"; 1604 reg-names = "security", "gpio"; 1605 reg = <0xc2f0000 0x1000>, 1606 <0xc2f1000 0x1000>; 1607 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1611 gpio-controller; 1612 #gpio-cells = <2>; 1613 interrupt-controller; 1614 #interrupt-cells = <2>; 1615 }; 1616 1617 pwm4: pwm@c340000 { 1618 compatible = "nvidia,tegra194-pwm", 1619 "nvidia,tegra186-pwm"; 1620 reg = <0xc340000 0x10000>; 1621 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1622 clock-names = "pwm"; 1623 resets = <&bpmp TEGRA194_RESET_PWM4>; 1624 reset-names = "pwm"; 1625 status = "disabled"; 1626 #pwm-cells = <2>; 1627 }; 1628 1629 pmc: pmc@c360000 { 1630 compatible = "nvidia,tegra194-pmc"; 1631 reg = <0x0c360000 0x10000>, 1632 <0x0c370000 0x10000>, 1633 <0x0c380000 0x10000>, 1634 <0x0c390000 0x10000>, 1635 <0x0c3a0000 0x10000>; 1636 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1637 1638 #interrupt-cells = <2>; 1639 interrupt-controller; 1640 sdmmc1_3v3: sdmmc1-3v3 { 1641 pins = "sdmmc1-hv"; 1642 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1643 }; 1644 1645 sdmmc1_1v8: sdmmc1-1v8 { 1646 pins = "sdmmc1-hv"; 1647 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1648 }; 1649 sdmmc3_3v3: sdmmc3-3v3 { 1650 pins = "sdmmc3-hv"; 1651 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1652 }; 1653 1654 sdmmc3_1v8: sdmmc3-1v8 { 1655 pins = "sdmmc3-hv"; 1656 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1657 }; 1658 1659 }; 1660 1661 aon-noc@c600000 { 1662 compatible = "nvidia,tegra194-aon-noc"; 1663 reg = <0xc600000 0x1000>; 1664 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1666 nvidia,apbmisc = <&apbmisc>; 1667 status = "okay"; 1668 }; 1669 1670 bpmp-noc@d600000 { 1671 compatible = "nvidia,tegra194-bpmp-noc"; 1672 reg = <0xd600000 0x1000>; 1673 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1675 nvidia,axi2apb = <&axi2apb>; 1676 nvidia,apbmisc = <&apbmisc>; 1677 status = "okay"; 1678 }; 1679 1680 iommu@10000000 { 1681 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1682 reg = <0x10000000 0x800000>; 1683 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1700 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1716 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1718 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1719 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1720 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1748 stream-match-mask = <0x7f80>; 1749 #global-interrupts = <1>; 1750 #iommu-cells = <1>; 1751 1752 nvidia,memory-controller = <&mc>; 1753 status = "disabled"; 1754 }; 1755 1756 smmu: iommu@12000000 { 1757 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1758 reg = <0x12000000 0x800000>, 1759 <0x11000000 0x800000>; 1760 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1819 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1820 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1821 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1826 stream-match-mask = <0x7f80>; 1827 #global-interrupts = <2>; 1828 #iommu-cells = <1>; 1829 1830 nvidia,memory-controller = <&mc>; 1831 status = "okay"; 1832 }; 1833 1834 host1x@13e00000 { 1835 compatible = "nvidia,tegra194-host1x"; 1836 reg = <0x13e00000 0x10000>, 1837 <0x13e10000 0x10000>; 1838 reg-names = "hypervisor", "vm"; 1839 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1841 interrupt-names = "syncpt", "host1x"; 1842 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1843 clock-names = "host1x"; 1844 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1845 reset-names = "host1x"; 1846 1847 #address-cells = <1>; 1848 #size-cells = <1>; 1849 1850 ranges = <0x15000000 0x15000000 0x01000000>; 1851 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1852 interconnect-names = "dma-mem"; 1853 iommus = <&smmu TEGRA194_SID_HOST1X>; 1854 1855 nvdec@15140000 { 1856 compatible = "nvidia,tegra194-nvdec"; 1857 reg = <0x15140000 0x00040000>; 1858 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1859 clock-names = "nvdec"; 1860 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1861 reset-names = "nvdec"; 1862 1863 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1864 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1865 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1866 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1867 interconnect-names = "dma-mem", "read-1", "write"; 1868 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1869 dma-coherent; 1870 1871 nvidia,host1x-class = <0xf5>; 1872 }; 1873 1874 display-hub@15200000 { 1875 compatible = "nvidia,tegra194-display"; 1876 reg = <0x15200000 0x00040000>; 1877 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1878 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1879 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1880 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1881 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1882 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1883 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1884 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1885 "wgrp3", "wgrp4", "wgrp5"; 1886 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1887 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1888 clock-names = "disp", "hub"; 1889 status = "disabled"; 1890 1891 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1892 1893 #address-cells = <1>; 1894 #size-cells = <1>; 1895 1896 ranges = <0x15200000 0x15200000 0x40000>; 1897 1898 display@15200000 { 1899 compatible = "nvidia,tegra194-dc"; 1900 reg = <0x15200000 0x10000>; 1901 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1902 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1903 clock-names = "dc"; 1904 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1905 reset-names = "dc"; 1906 1907 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1908 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1909 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1910 interconnect-names = "dma-mem", "read-1"; 1911 1912 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1913 nvidia,head = <0>; 1914 }; 1915 1916 display@15210000 { 1917 compatible = "nvidia,tegra194-dc"; 1918 reg = <0x15210000 0x10000>; 1919 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1920 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1921 clock-names = "dc"; 1922 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1923 reset-names = "dc"; 1924 1925 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1926 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1927 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1928 interconnect-names = "dma-mem", "read-1"; 1929 1930 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1931 nvidia,head = <1>; 1932 }; 1933 1934 display@15220000 { 1935 compatible = "nvidia,tegra194-dc"; 1936 reg = <0x15220000 0x10000>; 1937 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1938 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1939 clock-names = "dc"; 1940 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1941 reset-names = "dc"; 1942 1943 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1944 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1945 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1946 interconnect-names = "dma-mem", "read-1"; 1947 1948 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1949 nvidia,head = <2>; 1950 }; 1951 1952 display@15230000 { 1953 compatible = "nvidia,tegra194-dc"; 1954 reg = <0x15230000 0x10000>; 1955 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1956 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1957 clock-names = "dc"; 1958 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1959 reset-names = "dc"; 1960 1961 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1962 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1963 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1964 interconnect-names = "dma-mem", "read-1"; 1965 1966 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1967 nvidia,head = <3>; 1968 }; 1969 }; 1970 1971 vic@15340000 { 1972 compatible = "nvidia,tegra194-vic"; 1973 reg = <0x15340000 0x00040000>; 1974 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1975 clocks = <&bpmp TEGRA194_CLK_VIC>; 1976 clock-names = "vic"; 1977 resets = <&bpmp TEGRA194_RESET_VIC>; 1978 reset-names = "vic"; 1979 1980 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1981 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1982 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1983 interconnect-names = "dma-mem", "write"; 1984 iommus = <&smmu TEGRA194_SID_VIC>; 1985 dma-coherent; 1986 }; 1987 1988 nvjpg@15380000 { 1989 compatible = "nvidia,tegra194-nvjpg"; 1990 reg = <0x15380000 0x40000>; 1991 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 1992 clock-names = "nvjpg"; 1993 resets = <&bpmp TEGRA194_RESET_NVJPG>; 1994 reset-names = "nvjpg"; 1995 1996 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 1997 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 1998 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 1999 interconnect-names = "dma-mem", "write"; 2000 iommus = <&smmu TEGRA194_SID_NVJPG>; 2001 dma-coherent; 2002 }; 2003 2004 nvdec@15480000 { 2005 compatible = "nvidia,tegra194-nvdec"; 2006 reg = <0x15480000 0x00040000>; 2007 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 2008 clock-names = "nvdec"; 2009 resets = <&bpmp TEGRA194_RESET_NVDEC>; 2010 reset-names = "nvdec"; 2011 2012 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 2013 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 2014 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 2015 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 2016 interconnect-names = "dma-mem", "read-1", "write"; 2017 iommus = <&smmu TEGRA194_SID_NVDEC>; 2018 dma-coherent; 2019 2020 nvidia,host1x-class = <0xf0>; 2021 }; 2022 2023 nvenc@154c0000 { 2024 compatible = "nvidia,tegra194-nvenc"; 2025 reg = <0x154c0000 0x40000>; 2026 clocks = <&bpmp TEGRA194_CLK_NVENC>; 2027 clock-names = "nvenc"; 2028 resets = <&bpmp TEGRA194_RESET_NVENC>; 2029 reset-names = "nvenc"; 2030 2031 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2032 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2033 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2034 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2035 interconnect-names = "dma-mem", "read-1", "write"; 2036 iommus = <&smmu TEGRA194_SID_NVENC>; 2037 dma-coherent; 2038 2039 nvidia,host1x-class = <0x21>; 2040 }; 2041 2042 dpaux0: dpaux@155c0000 { 2043 compatible = "nvidia,tegra194-dpaux"; 2044 reg = <0x155c0000 0x10000>; 2045 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 2046 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 2047 <&bpmp TEGRA194_CLK_PLLDP>; 2048 clock-names = "dpaux", "parent"; 2049 resets = <&bpmp TEGRA194_RESET_DPAUX>; 2050 reset-names = "dpaux"; 2051 status = "disabled"; 2052 2053 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2054 2055 state_dpaux0_aux: pinmux-aux { 2056 groups = "dpaux-io"; 2057 function = "aux"; 2058 }; 2059 2060 state_dpaux0_i2c: pinmux-i2c { 2061 groups = "dpaux-io"; 2062 function = "i2c"; 2063 }; 2064 2065 state_dpaux0_off: pinmux-off { 2066 groups = "dpaux-io"; 2067 function = "off"; 2068 }; 2069 2070 i2c-bus { 2071 #address-cells = <1>; 2072 #size-cells = <0>; 2073 }; 2074 }; 2075 2076 dpaux1: dpaux@155d0000 { 2077 compatible = "nvidia,tegra194-dpaux"; 2078 reg = <0x155d0000 0x10000>; 2079 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2080 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 2081 <&bpmp TEGRA194_CLK_PLLDP>; 2082 clock-names = "dpaux", "parent"; 2083 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2084 reset-names = "dpaux"; 2085 status = "disabled"; 2086 2087 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2088 2089 state_dpaux1_aux: pinmux-aux { 2090 groups = "dpaux-io"; 2091 function = "aux"; 2092 }; 2093 2094 state_dpaux1_i2c: pinmux-i2c { 2095 groups = "dpaux-io"; 2096 function = "i2c"; 2097 }; 2098 2099 state_dpaux1_off: pinmux-off { 2100 groups = "dpaux-io"; 2101 function = "off"; 2102 }; 2103 2104 i2c-bus { 2105 #address-cells = <1>; 2106 #size-cells = <0>; 2107 }; 2108 }; 2109 2110 dpaux2: dpaux@155e0000 { 2111 compatible = "nvidia,tegra194-dpaux"; 2112 reg = <0x155e0000 0x10000>; 2113 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2114 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2115 <&bpmp TEGRA194_CLK_PLLDP>; 2116 clock-names = "dpaux", "parent"; 2117 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2118 reset-names = "dpaux"; 2119 status = "disabled"; 2120 2121 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2122 2123 state_dpaux2_aux: pinmux-aux { 2124 groups = "dpaux-io"; 2125 function = "aux"; 2126 }; 2127 2128 state_dpaux2_i2c: pinmux-i2c { 2129 groups = "dpaux-io"; 2130 function = "i2c"; 2131 }; 2132 2133 state_dpaux2_off: pinmux-off { 2134 groups = "dpaux-io"; 2135 function = "off"; 2136 }; 2137 2138 i2c-bus { 2139 #address-cells = <1>; 2140 #size-cells = <0>; 2141 }; 2142 }; 2143 2144 dpaux3: dpaux@155f0000 { 2145 compatible = "nvidia,tegra194-dpaux"; 2146 reg = <0x155f0000 0x10000>; 2147 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2148 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2149 <&bpmp TEGRA194_CLK_PLLDP>; 2150 clock-names = "dpaux", "parent"; 2151 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2152 reset-names = "dpaux"; 2153 status = "disabled"; 2154 2155 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2156 2157 state_dpaux3_aux: pinmux-aux { 2158 groups = "dpaux-io"; 2159 function = "aux"; 2160 }; 2161 2162 state_dpaux3_i2c: pinmux-i2c { 2163 groups = "dpaux-io"; 2164 function = "i2c"; 2165 }; 2166 2167 state_dpaux3_off: pinmux-off { 2168 groups = "dpaux-io"; 2169 function = "off"; 2170 }; 2171 2172 i2c-bus { 2173 #address-cells = <1>; 2174 #size-cells = <0>; 2175 }; 2176 }; 2177 2178 nvenc@15a80000 { 2179 compatible = "nvidia,tegra194-nvenc"; 2180 reg = <0x15a80000 0x00040000>; 2181 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2182 clock-names = "nvenc"; 2183 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2184 reset-names = "nvenc"; 2185 2186 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2187 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2188 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2189 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2190 interconnect-names = "dma-mem", "read-1", "write"; 2191 iommus = <&smmu TEGRA194_SID_NVENC1>; 2192 dma-coherent; 2193 2194 nvidia,host1x-class = <0x22>; 2195 }; 2196 2197 sor0: sor@15b00000 { 2198 compatible = "nvidia,tegra194-sor"; 2199 reg = <0x15b00000 0x40000>; 2200 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2201 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2202 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2203 <&bpmp TEGRA194_CLK_PLLD>, 2204 <&bpmp TEGRA194_CLK_PLLDP>, 2205 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2206 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2207 clock-names = "sor", "out", "parent", "dp", "safe", 2208 "pad"; 2209 resets = <&bpmp TEGRA194_RESET_SOR0>; 2210 reset-names = "sor"; 2211 pinctrl-0 = <&state_dpaux0_aux>; 2212 pinctrl-1 = <&state_dpaux0_i2c>; 2213 pinctrl-2 = <&state_dpaux0_off>; 2214 pinctrl-names = "aux", "i2c", "off"; 2215 status = "disabled"; 2216 2217 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2218 nvidia,interface = <0>; 2219 }; 2220 2221 sor1: sor@15b40000 { 2222 compatible = "nvidia,tegra194-sor"; 2223 reg = <0x15b40000 0x40000>; 2224 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2225 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2226 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2227 <&bpmp TEGRA194_CLK_PLLD2>, 2228 <&bpmp TEGRA194_CLK_PLLDP>, 2229 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2230 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2231 clock-names = "sor", "out", "parent", "dp", "safe", 2232 "pad"; 2233 resets = <&bpmp TEGRA194_RESET_SOR1>; 2234 reset-names = "sor"; 2235 pinctrl-0 = <&state_dpaux1_aux>; 2236 pinctrl-1 = <&state_dpaux1_i2c>; 2237 pinctrl-2 = <&state_dpaux1_off>; 2238 pinctrl-names = "aux", "i2c", "off"; 2239 status = "disabled"; 2240 2241 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2242 nvidia,interface = <1>; 2243 }; 2244 2245 sor2: sor@15b80000 { 2246 compatible = "nvidia,tegra194-sor"; 2247 reg = <0x15b80000 0x40000>; 2248 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2249 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2250 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2251 <&bpmp TEGRA194_CLK_PLLD3>, 2252 <&bpmp TEGRA194_CLK_PLLDP>, 2253 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2254 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2255 clock-names = "sor", "out", "parent", "dp", "safe", 2256 "pad"; 2257 resets = <&bpmp TEGRA194_RESET_SOR2>; 2258 reset-names = "sor"; 2259 pinctrl-0 = <&state_dpaux2_aux>; 2260 pinctrl-1 = <&state_dpaux2_i2c>; 2261 pinctrl-2 = <&state_dpaux2_off>; 2262 pinctrl-names = "aux", "i2c", "off"; 2263 status = "disabled"; 2264 2265 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2266 nvidia,interface = <2>; 2267 }; 2268 2269 sor3: sor@15bc0000 { 2270 compatible = "nvidia,tegra194-sor"; 2271 reg = <0x15bc0000 0x40000>; 2272 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2273 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2274 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2275 <&bpmp TEGRA194_CLK_PLLD4>, 2276 <&bpmp TEGRA194_CLK_PLLDP>, 2277 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2278 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2279 clock-names = "sor", "out", "parent", "dp", "safe", 2280 "pad"; 2281 resets = <&bpmp TEGRA194_RESET_SOR3>; 2282 reset-names = "sor"; 2283 pinctrl-0 = <&state_dpaux3_aux>; 2284 pinctrl-1 = <&state_dpaux3_i2c>; 2285 pinctrl-2 = <&state_dpaux3_off>; 2286 pinctrl-names = "aux", "i2c", "off"; 2287 status = "disabled"; 2288 2289 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2290 nvidia,interface = <3>; 2291 }; 2292 }; 2293 2294 gpu@17000000 { 2295 compatible = "nvidia,gv11b"; 2296 reg = <0x17000000 0x1000000>, 2297 <0x18000000 0x1000000>; 2298 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2299 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2300 interrupt-names = "stall", "nonstall"; 2301 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2302 <&bpmp TEGRA194_CLK_GPU_PWR>, 2303 <&bpmp TEGRA194_CLK_FUSE>; 2304 clock-names = "gpu", "pwr", "fuse"; 2305 resets = <&bpmp TEGRA194_RESET_GPU>; 2306 reset-names = "gpu"; 2307 dma-coherent; 2308 2309 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2310 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2311 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2312 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2313 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2314 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2315 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2316 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2317 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2318 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2319 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2320 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2321 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2322 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2323 "read-1", "read-1-hp", "write-1", 2324 "read-2", "read-2-hp", "write-2", 2325 "read-3", "read-3-hp", "write-3"; 2326 }; 2327 }; 2328 2329 pcie@14100000 { 2330 compatible = "nvidia,tegra194-pcie"; 2331 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2332 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2333 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2334 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2335 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2336 reg-names = "appl", "config", "atu_dma", "dbi"; 2337 2338 status = "disabled"; 2339 2340 #address-cells = <3>; 2341 #size-cells = <2>; 2342 device_type = "pci"; 2343 num-lanes = <1>; 2344 linux,pci-domain = <1>; 2345 2346 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2347 clock-names = "core"; 2348 2349 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2350 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2351 reset-names = "apb", "core"; 2352 2353 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2354 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2355 interrupt-names = "intr", "msi"; 2356 2357 #interrupt-cells = <1>; 2358 interrupt-map-mask = <0 0 0 0>; 2359 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2360 2361 nvidia,bpmp = <&bpmp 1>; 2362 2363 nvidia,aspm-cmrt-us = <60>; 2364 nvidia,aspm-pwr-on-t-us = <20>; 2365 nvidia,aspm-l0s-entrance-latency-us = <3>; 2366 2367 bus-range = <0x0 0xff>; 2368 2369 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2370 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2371 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2372 2373 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2374 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2375 interconnect-names = "dma-mem", "write"; 2376 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2377 iommu-map-mask = <0x0>; 2378 dma-coherent; 2379 }; 2380 2381 pcie@14120000 { 2382 compatible = "nvidia,tegra194-pcie"; 2383 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2384 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2385 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2386 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2387 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2388 reg-names = "appl", "config", "atu_dma", "dbi"; 2389 2390 status = "disabled"; 2391 2392 #address-cells = <3>; 2393 #size-cells = <2>; 2394 device_type = "pci"; 2395 num-lanes = <1>; 2396 linux,pci-domain = <2>; 2397 2398 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2399 clock-names = "core"; 2400 2401 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2402 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2403 reset-names = "apb", "core"; 2404 2405 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2406 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2407 interrupt-names = "intr", "msi"; 2408 2409 #interrupt-cells = <1>; 2410 interrupt-map-mask = <0 0 0 0>; 2411 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2412 2413 nvidia,bpmp = <&bpmp 2>; 2414 2415 nvidia,aspm-cmrt-us = <60>; 2416 nvidia,aspm-pwr-on-t-us = <20>; 2417 nvidia,aspm-l0s-entrance-latency-us = <3>; 2418 2419 bus-range = <0x0 0xff>; 2420 2421 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2422 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2423 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2424 2425 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2426 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2427 interconnect-names = "dma-mem", "write"; 2428 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2429 iommu-map-mask = <0x0>; 2430 dma-coherent; 2431 }; 2432 2433 pcie@14140000 { 2434 compatible = "nvidia,tegra194-pcie"; 2435 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2436 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2437 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2438 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2439 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2440 reg-names = "appl", "config", "atu_dma", "dbi"; 2441 2442 status = "disabled"; 2443 2444 #address-cells = <3>; 2445 #size-cells = <2>; 2446 device_type = "pci"; 2447 num-lanes = <1>; 2448 linux,pci-domain = <3>; 2449 2450 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2451 clock-names = "core"; 2452 2453 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2454 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2455 reset-names = "apb", "core"; 2456 2457 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2458 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2459 interrupt-names = "intr", "msi"; 2460 2461 #interrupt-cells = <1>; 2462 interrupt-map-mask = <0 0 0 0>; 2463 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2464 2465 nvidia,bpmp = <&bpmp 3>; 2466 2467 nvidia,aspm-cmrt-us = <60>; 2468 nvidia,aspm-pwr-on-t-us = <20>; 2469 nvidia,aspm-l0s-entrance-latency-us = <3>; 2470 2471 bus-range = <0x0 0xff>; 2472 2473 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2474 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2475 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2476 2477 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2478 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2479 interconnect-names = "dma-mem", "write"; 2480 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2481 iommu-map-mask = <0x0>; 2482 dma-coherent; 2483 }; 2484 2485 pcie@14160000 { 2486 compatible = "nvidia,tegra194-pcie"; 2487 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2488 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2489 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2490 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2491 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2492 reg-names = "appl", "config", "atu_dma", "dbi"; 2493 2494 status = "disabled"; 2495 2496 #address-cells = <3>; 2497 #size-cells = <2>; 2498 device_type = "pci"; 2499 num-lanes = <4>; 2500 linux,pci-domain = <4>; 2501 2502 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2503 clock-names = "core"; 2504 2505 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2506 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2507 reset-names = "apb", "core"; 2508 2509 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2510 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2511 interrupt-names = "intr", "msi"; 2512 2513 #interrupt-cells = <1>; 2514 interrupt-map-mask = <0 0 0 0>; 2515 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2516 2517 nvidia,bpmp = <&bpmp 4>; 2518 2519 nvidia,aspm-cmrt-us = <60>; 2520 nvidia,aspm-pwr-on-t-us = <20>; 2521 nvidia,aspm-l0s-entrance-latency-us = <3>; 2522 2523 bus-range = <0x0 0xff>; 2524 2525 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2526 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2527 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2528 2529 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2530 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2531 interconnect-names = "dma-mem", "write"; 2532 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2533 iommu-map-mask = <0x0>; 2534 dma-coherent; 2535 }; 2536 2537 pcie@14180000 { 2538 compatible = "nvidia,tegra194-pcie"; 2539 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2540 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2541 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2542 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2543 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2544 reg-names = "appl", "config", "atu_dma", "dbi"; 2545 2546 status = "disabled"; 2547 2548 #address-cells = <3>; 2549 #size-cells = <2>; 2550 device_type = "pci"; 2551 num-lanes = <8>; 2552 linux,pci-domain = <0>; 2553 2554 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2555 clock-names = "core"; 2556 2557 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2558 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2559 reset-names = "apb", "core"; 2560 2561 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2562 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2563 interrupt-names = "intr", "msi"; 2564 2565 #interrupt-cells = <1>; 2566 interrupt-map-mask = <0 0 0 0>; 2567 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2568 2569 nvidia,bpmp = <&bpmp 0>; 2570 2571 nvidia,aspm-cmrt-us = <60>; 2572 nvidia,aspm-pwr-on-t-us = <20>; 2573 nvidia,aspm-l0s-entrance-latency-us = <3>; 2574 2575 bus-range = <0x0 0xff>; 2576 2577 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2578 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2579 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2580 2581 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2582 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2583 interconnect-names = "dma-mem", "write"; 2584 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2585 iommu-map-mask = <0x0>; 2586 dma-coherent; 2587 }; 2588 2589 pcie@141a0000 { 2590 compatible = "nvidia,tegra194-pcie"; 2591 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2592 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2593 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2594 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2595 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2596 reg-names = "appl", "config", "atu_dma", "dbi"; 2597 2598 status = "disabled"; 2599 2600 #address-cells = <3>; 2601 #size-cells = <2>; 2602 device_type = "pci"; 2603 num-lanes = <8>; 2604 linux,pci-domain = <5>; 2605 2606 pinctrl-names = "default"; 2607 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2608 2609 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2610 clock-names = "core"; 2611 2612 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2613 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2614 reset-names = "apb", "core"; 2615 2616 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2617 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2618 interrupt-names = "intr", "msi"; 2619 2620 nvidia,bpmp = <&bpmp 5>; 2621 2622 #interrupt-cells = <1>; 2623 interrupt-map-mask = <0 0 0 0>; 2624 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2625 2626 nvidia,aspm-cmrt-us = <60>; 2627 nvidia,aspm-pwr-on-t-us = <20>; 2628 nvidia,aspm-l0s-entrance-latency-us = <3>; 2629 2630 bus-range = <0x0 0xff>; 2631 2632 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2633 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2634 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2635 2636 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2637 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2638 interconnect-names = "dma-mem", "write"; 2639 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2640 iommu-map-mask = <0x0>; 2641 dma-coherent; 2642 }; 2643 2644 pcie-ep@14160000 { 2645 compatible = "nvidia,tegra194-pcie-ep"; 2646 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2647 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2648 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2649 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2650 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2651 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2652 2653 status = "disabled"; 2654 2655 num-lanes = <4>; 2656 num-ib-windows = <2>; 2657 num-ob-windows = <8>; 2658 2659 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2660 clock-names = "core"; 2661 2662 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2663 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2664 reset-names = "apb", "core"; 2665 2666 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2667 interrupt-names = "intr"; 2668 2669 nvidia,bpmp = <&bpmp 4>; 2670 2671 nvidia,aspm-cmrt-us = <60>; 2672 nvidia,aspm-pwr-on-t-us = <20>; 2673 nvidia,aspm-l0s-entrance-latency-us = <3>; 2674 2675 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2676 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2677 interconnect-names = "dma-mem", "write"; 2678 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2679 iommu-map-mask = <0x0>; 2680 dma-coherent; 2681 }; 2682 2683 pcie-ep@14180000 { 2684 compatible = "nvidia,tegra194-pcie-ep"; 2685 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2686 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2687 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2688 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2689 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2690 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2691 2692 status = "disabled"; 2693 2694 num-lanes = <8>; 2695 num-ib-windows = <2>; 2696 num-ob-windows = <8>; 2697 2698 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2699 clock-names = "core"; 2700 2701 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2702 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2703 reset-names = "apb", "core"; 2704 2705 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2706 interrupt-names = "intr"; 2707 2708 nvidia,bpmp = <&bpmp 0>; 2709 2710 nvidia,aspm-cmrt-us = <60>; 2711 nvidia,aspm-pwr-on-t-us = <20>; 2712 nvidia,aspm-l0s-entrance-latency-us = <3>; 2713 2714 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2715 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2716 interconnect-names = "dma-mem", "write"; 2717 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2718 iommu-map-mask = <0x0>; 2719 dma-coherent; 2720 }; 2721 2722 pcie-ep@141a0000 { 2723 compatible = "nvidia,tegra194-pcie-ep"; 2724 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2725 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2726 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2727 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2728 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2729 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2730 2731 status = "disabled"; 2732 2733 num-lanes = <8>; 2734 num-ib-windows = <2>; 2735 num-ob-windows = <8>; 2736 2737 pinctrl-names = "default"; 2738 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2739 2740 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2741 clock-names = "core"; 2742 2743 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2744 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2745 reset-names = "apb", "core"; 2746 2747 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2748 interrupt-names = "intr"; 2749 2750 nvidia,bpmp = <&bpmp 5>; 2751 2752 nvidia,aspm-cmrt-us = <60>; 2753 nvidia,aspm-pwr-on-t-us = <20>; 2754 nvidia,aspm-l0s-entrance-latency-us = <3>; 2755 2756 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2757 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2758 interconnect-names = "dma-mem", "write"; 2759 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2760 iommu-map-mask = <0x0>; 2761 dma-coherent; 2762 }; 2763 2764 sram@40000000 { 2765 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2766 reg = <0x0 0x40000000 0x0 0x50000>; 2767 #address-cells = <1>; 2768 #size-cells = <1>; 2769 ranges = <0x0 0x0 0x40000000 0x50000>; 2770 no-memory-wc; 2771 2772 cpu_bpmp_tx: sram@4e000 { 2773 reg = <0x4e000 0x1000>; 2774 label = "cpu-bpmp-tx"; 2775 pool; 2776 }; 2777 2778 cpu_bpmp_rx: sram@4f000 { 2779 reg = <0x4f000 0x1000>; 2780 label = "cpu-bpmp-rx"; 2781 pool; 2782 }; 2783 }; 2784 2785 bpmp: bpmp { 2786 compatible = "nvidia,tegra186-bpmp"; 2787 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2788 TEGRA_HSP_DB_MASTER_BPMP>; 2789 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2790 #clock-cells = <1>; 2791 #reset-cells = <1>; 2792 #power-domain-cells = <1>; 2793 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2794 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2795 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2796 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2797 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2798 iommus = <&smmu TEGRA194_SID_BPMP>; 2799 2800 bpmp_i2c: i2c { 2801 compatible = "nvidia,tegra186-bpmp-i2c"; 2802 nvidia,bpmp-bus-id = <5>; 2803 #address-cells = <1>; 2804 #size-cells = <0>; 2805 }; 2806 2807 bpmp_thermal: thermal { 2808 compatible = "nvidia,tegra186-bpmp-thermal"; 2809 #thermal-sensor-cells = <1>; 2810 }; 2811 }; 2812 2813 cpus { 2814 compatible = "nvidia,tegra194-ccplex"; 2815 nvidia,bpmp = <&bpmp>; 2816 #address-cells = <1>; 2817 #size-cells = <0>; 2818 2819 cpu0_0: cpu@0 { 2820 compatible = "nvidia,tegra194-carmel"; 2821 device_type = "cpu"; 2822 reg = <0x000>; 2823 enable-method = "psci"; 2824 i-cache-size = <131072>; 2825 i-cache-line-size = <64>; 2826 i-cache-sets = <512>; 2827 d-cache-size = <65536>; 2828 d-cache-line-size = <64>; 2829 d-cache-sets = <256>; 2830 next-level-cache = <&l2c_0>; 2831 }; 2832 2833 cpu0_1: cpu@1 { 2834 compatible = "nvidia,tegra194-carmel"; 2835 device_type = "cpu"; 2836 reg = <0x001>; 2837 enable-method = "psci"; 2838 i-cache-size = <131072>; 2839 i-cache-line-size = <64>; 2840 i-cache-sets = <512>; 2841 d-cache-size = <65536>; 2842 d-cache-line-size = <64>; 2843 d-cache-sets = <256>; 2844 next-level-cache = <&l2c_0>; 2845 }; 2846 2847 cpu1_0: cpu@100 { 2848 compatible = "nvidia,tegra194-carmel"; 2849 device_type = "cpu"; 2850 reg = <0x100>; 2851 enable-method = "psci"; 2852 i-cache-size = <131072>; 2853 i-cache-line-size = <64>; 2854 i-cache-sets = <512>; 2855 d-cache-size = <65536>; 2856 d-cache-line-size = <64>; 2857 d-cache-sets = <256>; 2858 next-level-cache = <&l2c_1>; 2859 }; 2860 2861 cpu1_1: cpu@101 { 2862 compatible = "nvidia,tegra194-carmel"; 2863 device_type = "cpu"; 2864 reg = <0x101>; 2865 enable-method = "psci"; 2866 i-cache-size = <131072>; 2867 i-cache-line-size = <64>; 2868 i-cache-sets = <512>; 2869 d-cache-size = <65536>; 2870 d-cache-line-size = <64>; 2871 d-cache-sets = <256>; 2872 next-level-cache = <&l2c_1>; 2873 }; 2874 2875 cpu2_0: cpu@200 { 2876 compatible = "nvidia,tegra194-carmel"; 2877 device_type = "cpu"; 2878 reg = <0x200>; 2879 enable-method = "psci"; 2880 i-cache-size = <131072>; 2881 i-cache-line-size = <64>; 2882 i-cache-sets = <512>; 2883 d-cache-size = <65536>; 2884 d-cache-line-size = <64>; 2885 d-cache-sets = <256>; 2886 next-level-cache = <&l2c_2>; 2887 }; 2888 2889 cpu2_1: cpu@201 { 2890 compatible = "nvidia,tegra194-carmel"; 2891 device_type = "cpu"; 2892 reg = <0x201>; 2893 enable-method = "psci"; 2894 i-cache-size = <131072>; 2895 i-cache-line-size = <64>; 2896 i-cache-sets = <512>; 2897 d-cache-size = <65536>; 2898 d-cache-line-size = <64>; 2899 d-cache-sets = <256>; 2900 next-level-cache = <&l2c_2>; 2901 }; 2902 2903 cpu3_0: cpu@300 { 2904 compatible = "nvidia,tegra194-carmel"; 2905 device_type = "cpu"; 2906 reg = <0x300>; 2907 enable-method = "psci"; 2908 i-cache-size = <131072>; 2909 i-cache-line-size = <64>; 2910 i-cache-sets = <512>; 2911 d-cache-size = <65536>; 2912 d-cache-line-size = <64>; 2913 d-cache-sets = <256>; 2914 next-level-cache = <&l2c_3>; 2915 }; 2916 2917 cpu3_1: cpu@301 { 2918 compatible = "nvidia,tegra194-carmel"; 2919 device_type = "cpu"; 2920 reg = <0x301>; 2921 enable-method = "psci"; 2922 i-cache-size = <131072>; 2923 i-cache-line-size = <64>; 2924 i-cache-sets = <512>; 2925 d-cache-size = <65536>; 2926 d-cache-line-size = <64>; 2927 d-cache-sets = <256>; 2928 next-level-cache = <&l2c_3>; 2929 }; 2930 2931 cpu-map { 2932 cluster0 { 2933 core0 { 2934 cpu = <&cpu0_0>; 2935 }; 2936 2937 core1 { 2938 cpu = <&cpu0_1>; 2939 }; 2940 }; 2941 2942 cluster1 { 2943 core0 { 2944 cpu = <&cpu1_0>; 2945 }; 2946 2947 core1 { 2948 cpu = <&cpu1_1>; 2949 }; 2950 }; 2951 2952 cluster2 { 2953 core0 { 2954 cpu = <&cpu2_0>; 2955 }; 2956 2957 core1 { 2958 cpu = <&cpu2_1>; 2959 }; 2960 }; 2961 2962 cluster3 { 2963 core0 { 2964 cpu = <&cpu3_0>; 2965 }; 2966 2967 core1 { 2968 cpu = <&cpu3_1>; 2969 }; 2970 }; 2971 }; 2972 2973 l2c_0: l2-cache0 { 2974 cache-size = <2097152>; 2975 cache-line-size = <64>; 2976 cache-sets = <2048>; 2977 next-level-cache = <&l3c>; 2978 }; 2979 2980 l2c_1: l2-cache1 { 2981 cache-size = <2097152>; 2982 cache-line-size = <64>; 2983 cache-sets = <2048>; 2984 next-level-cache = <&l3c>; 2985 }; 2986 2987 l2c_2: l2-cache2 { 2988 cache-size = <2097152>; 2989 cache-line-size = <64>; 2990 cache-sets = <2048>; 2991 next-level-cache = <&l3c>; 2992 }; 2993 2994 l2c_3: l2-cache3 { 2995 cache-size = <2097152>; 2996 cache-line-size = <64>; 2997 cache-sets = <2048>; 2998 next-level-cache = <&l3c>; 2999 }; 3000 3001 l3c: l3-cache { 3002 cache-size = <4194304>; 3003 cache-line-size = <64>; 3004 cache-sets = <4096>; 3005 }; 3006 }; 3007 3008 pmu { 3009 compatible = "nvidia,carmel-pmu"; 3010 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 3011 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 3012 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 3013 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 3014 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 3015 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 3016 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 3017 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 3018 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 3019 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 3020 }; 3021 3022 psci { 3023 compatible = "arm,psci-1.0"; 3024 status = "okay"; 3025 method = "smc"; 3026 }; 3027 3028 sound { 3029 status = "disabled"; 3030 3031 clocks = <&bpmp TEGRA194_CLK_PLLA>, 3032 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3033 clock-names = "pll_a", "plla_out0"; 3034 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 3035 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 3036 <&bpmp TEGRA194_CLK_AUD_MCLK>; 3037 assigned-clock-parents = <0>, 3038 <&bpmp TEGRA194_CLK_PLLA>, 3039 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3040 /* 3041 * PLLA supports dynamic ramp. Below initial rate is chosen 3042 * for this to work and oscillate between base rates required 3043 * for 8x and 11.025x sample rate streams. 3044 */ 3045 assigned-clock-rates = <258000000>; 3046 }; 3047 3048 tcu: serial { 3049 compatible = "nvidia,tegra194-tcu"; 3050 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3051 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3052 mbox-names = "rx", "tx"; 3053 }; 3054 3055 thermal-zones { 3056 cpu-thermal { 3057 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3058 status = "disabled"; 3059 }; 3060 3061 gpu-thermal { 3062 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3063 status = "disabled"; 3064 }; 3065 3066 aux-thermal { 3067 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3068 status = "disabled"; 3069 }; 3070 3071 pllx-thermal { 3072 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3073 status = "disabled"; 3074 }; 3075 3076 ao-thermal { 3077 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3078 status = "disabled"; 3079 }; 3080 3081 tj-thermal { 3082 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3083 status = "disabled"; 3084 }; 3085 }; 3086 3087 timer { 3088 compatible = "arm,armv8-timer"; 3089 interrupts = <GIC_PPI 13 3090 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3091 <GIC_PPI 14 3092 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3093 <GIC_PPI 11 3094 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3095 <GIC_PPI 10 3096 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3097 interrupt-parent = <&gic>; 3098 always-on; 3099 }; 3100}; 3101