1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x0 0x0 0x0 0x40000000>; 25 26 apbmisc: misc@100000 { 27 compatible = "nvidia,tegra194-misc"; 28 reg = <0x00100000 0xf000>, 29 <0x0010f000 0x1000>; 30 }; 31 32 gpio: gpio@2200000 { 33 compatible = "nvidia,tegra194-gpio"; 34 reg-names = "security", "gpio"; 35 reg = <0x2200000 0x10000>, 36 <0x2210000 0x10000>; 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85 #interrupt-cells = <2>; 86 interrupt-controller; 87 #gpio-cells = <2>; 88 gpio-controller; 89 gpio-ranges = <&pinmux 0 0 169>; 90 }; 91 92 cbb-noc@2300000 { 93 compatible = "nvidia,tegra194-cbb-noc"; 94 reg = <0x02300000 0x1000>; 95 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 97 nvidia,axi2apb = <&axi2apb>; 98 nvidia,apbmisc = <&apbmisc>; 99 status = "okay"; 100 }; 101 102 axi2apb: axi2apb@2390000 { 103 compatible = "nvidia,tegra194-axi2apb"; 104 reg = <0x2390000 0x1000>, 105 <0x23a0000 0x1000>, 106 <0x23b0000 0x1000>, 107 <0x23c0000 0x1000>, 108 <0x23d0000 0x1000>, 109 <0x23e0000 0x1000>; 110 status = "okay"; 111 }; 112 113 ethernet@2490000 { 114 compatible = "nvidia,tegra194-eqos", 115 "nvidia,tegra186-eqos", 116 "snps,dwc-qos-ethernet-4.10"; 117 reg = <0x02490000 0x10000>; 118 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 120 <&bpmp TEGRA194_CLK_EQOS_AXI>, 121 <&bpmp TEGRA194_CLK_EQOS_RX>, 122 <&bpmp TEGRA194_CLK_EQOS_TX>, 123 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 124 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 125 resets = <&bpmp TEGRA194_RESET_EQOS>; 126 reset-names = "eqos"; 127 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 128 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 129 interconnect-names = "dma-mem", "write"; 130 iommus = <&smmu TEGRA194_SID_EQOS>; 131 status = "disabled"; 132 133 snps,write-requests = <1>; 134 snps,read-requests = <3>; 135 snps,burst-map = <0x7>; 136 snps,txpbl = <16>; 137 snps,rxpbl = <8>; 138 }; 139 140 gpcdma: dma-controller@2600000 { 141 compatible = "nvidia,tegra194-gpcdma", 142 "nvidia,tegra186-gpcdma"; 143 reg = <0x2600000 0x210000>; 144 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 145 reset-names = "gpcdma"; 146 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 178 #dma-cells = <1>; 179 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 180 dma-coherent; 181 dma-channel-mask = <0xfffffffe>; 182 status = "okay"; 183 }; 184 185 aconnect@2900000 { 186 compatible = "nvidia,tegra194-aconnect", 187 "nvidia,tegra210-aconnect"; 188 clocks = <&bpmp TEGRA194_CLK_APE>, 189 <&bpmp TEGRA194_CLK_APB2APE>; 190 clock-names = "ape", "apb2ape"; 191 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 192 #address-cells = <1>; 193 #size-cells = <1>; 194 ranges = <0x02900000 0x02900000 0x200000>; 195 status = "disabled"; 196 197 adma: dma-controller@2930000 { 198 compatible = "nvidia,tegra194-adma", 199 "nvidia,tegra186-adma"; 200 reg = <0x02930000 0x20000>; 201 interrupt-parent = <&agic>; 202 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 234 #dma-cells = <1>; 235 clocks = <&bpmp TEGRA194_CLK_AHUB>; 236 clock-names = "d_audio"; 237 status = "disabled"; 238 }; 239 240 agic: interrupt-controller@2a40000 { 241 compatible = "nvidia,tegra194-agic", 242 "nvidia,tegra210-agic"; 243 #interrupt-cells = <3>; 244 interrupt-controller; 245 reg = <0x02a41000 0x1000>, 246 <0x02a42000 0x2000>; 247 interrupts = <GIC_SPI 145 248 (GIC_CPU_MASK_SIMPLE(4) | 249 IRQ_TYPE_LEVEL_HIGH)>; 250 clocks = <&bpmp TEGRA194_CLK_APE>; 251 clock-names = "clk"; 252 status = "disabled"; 253 }; 254 255 tegra_ahub: ahub@2900800 { 256 compatible = "nvidia,tegra194-ahub", 257 "nvidia,tegra186-ahub"; 258 reg = <0x02900800 0x800>; 259 clocks = <&bpmp TEGRA194_CLK_AHUB>; 260 clock-names = "ahub"; 261 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 262 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 263 #address-cells = <1>; 264 #size-cells = <1>; 265 ranges = <0x02900800 0x02900800 0x11800>; 266 status = "disabled"; 267 268 tegra_admaif: admaif@290f000 { 269 compatible = "nvidia,tegra194-admaif", 270 "nvidia,tegra186-admaif"; 271 reg = <0x0290f000 0x1000>; 272 dmas = <&adma 1>, <&adma 1>, 273 <&adma 2>, <&adma 2>, 274 <&adma 3>, <&adma 3>, 275 <&adma 4>, <&adma 4>, 276 <&adma 5>, <&adma 5>, 277 <&adma 6>, <&adma 6>, 278 <&adma 7>, <&adma 7>, 279 <&adma 8>, <&adma 8>, 280 <&adma 9>, <&adma 9>, 281 <&adma 10>, <&adma 10>, 282 <&adma 11>, <&adma 11>, 283 <&adma 12>, <&adma 12>, 284 <&adma 13>, <&adma 13>, 285 <&adma 14>, <&adma 14>, 286 <&adma 15>, <&adma 15>, 287 <&adma 16>, <&adma 16>, 288 <&adma 17>, <&adma 17>, 289 <&adma 18>, <&adma 18>, 290 <&adma 19>, <&adma 19>, 291 <&adma 20>, <&adma 20>; 292 dma-names = "rx1", "tx1", 293 "rx2", "tx2", 294 "rx3", "tx3", 295 "rx4", "tx4", 296 "rx5", "tx5", 297 "rx6", "tx6", 298 "rx7", "tx7", 299 "rx8", "tx8", 300 "rx9", "tx9", 301 "rx10", "tx10", 302 "rx11", "tx11", 303 "rx12", "tx12", 304 "rx13", "tx13", 305 "rx14", "tx14", 306 "rx15", "tx15", 307 "rx16", "tx16", 308 "rx17", "tx17", 309 "rx18", "tx18", 310 "rx19", "tx19", 311 "rx20", "tx20"; 312 status = "disabled"; 313 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 314 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 315 interconnect-names = "dma-mem", "write"; 316 iommus = <&smmu TEGRA194_SID_APE>; 317 }; 318 319 tegra_i2s1: i2s@2901000 { 320 compatible = "nvidia,tegra194-i2s", 321 "nvidia,tegra210-i2s"; 322 reg = <0x2901000 0x100>; 323 clocks = <&bpmp TEGRA194_CLK_I2S1>, 324 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 325 clock-names = "i2s", "sync_input"; 326 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 327 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 328 assigned-clock-rates = <1536000>; 329 sound-name-prefix = "I2S1"; 330 status = "disabled"; 331 }; 332 333 tegra_i2s2: i2s@2901100 { 334 compatible = "nvidia,tegra194-i2s", 335 "nvidia,tegra210-i2s"; 336 reg = <0x2901100 0x100>; 337 clocks = <&bpmp TEGRA194_CLK_I2S2>, 338 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 339 clock-names = "i2s", "sync_input"; 340 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 341 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 342 assigned-clock-rates = <1536000>; 343 sound-name-prefix = "I2S2"; 344 status = "disabled"; 345 }; 346 347 tegra_i2s3: i2s@2901200 { 348 compatible = "nvidia,tegra194-i2s", 349 "nvidia,tegra210-i2s"; 350 reg = <0x2901200 0x100>; 351 clocks = <&bpmp TEGRA194_CLK_I2S3>, 352 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 353 clock-names = "i2s", "sync_input"; 354 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 355 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 356 assigned-clock-rates = <1536000>; 357 sound-name-prefix = "I2S3"; 358 status = "disabled"; 359 }; 360 361 tegra_i2s4: i2s@2901300 { 362 compatible = "nvidia,tegra194-i2s", 363 "nvidia,tegra210-i2s"; 364 reg = <0x2901300 0x100>; 365 clocks = <&bpmp TEGRA194_CLK_I2S4>, 366 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 367 clock-names = "i2s", "sync_input"; 368 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 369 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 370 assigned-clock-rates = <1536000>; 371 sound-name-prefix = "I2S4"; 372 status = "disabled"; 373 }; 374 375 tegra_i2s5: i2s@2901400 { 376 compatible = "nvidia,tegra194-i2s", 377 "nvidia,tegra210-i2s"; 378 reg = <0x2901400 0x100>; 379 clocks = <&bpmp TEGRA194_CLK_I2S5>, 380 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 381 clock-names = "i2s", "sync_input"; 382 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 383 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 384 assigned-clock-rates = <1536000>; 385 sound-name-prefix = "I2S5"; 386 status = "disabled"; 387 }; 388 389 tegra_i2s6: i2s@2901500 { 390 compatible = "nvidia,tegra194-i2s", 391 "nvidia,tegra210-i2s"; 392 reg = <0x2901500 0x100>; 393 clocks = <&bpmp TEGRA194_CLK_I2S6>, 394 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 395 clock-names = "i2s", "sync_input"; 396 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 397 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 398 assigned-clock-rates = <1536000>; 399 sound-name-prefix = "I2S6"; 400 status = "disabled"; 401 }; 402 403 tegra_dmic1: dmic@2904000 { 404 compatible = "nvidia,tegra194-dmic", 405 "nvidia,tegra210-dmic"; 406 reg = <0x2904000 0x100>; 407 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 408 clock-names = "dmic"; 409 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 410 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 411 assigned-clock-rates = <3072000>; 412 sound-name-prefix = "DMIC1"; 413 status = "disabled"; 414 }; 415 416 tegra_dmic2: dmic@2904100 { 417 compatible = "nvidia,tegra194-dmic", 418 "nvidia,tegra210-dmic"; 419 reg = <0x2904100 0x100>; 420 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 421 clock-names = "dmic"; 422 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 423 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 424 assigned-clock-rates = <3072000>; 425 sound-name-prefix = "DMIC2"; 426 status = "disabled"; 427 }; 428 429 tegra_dmic3: dmic@2904200 { 430 compatible = "nvidia,tegra194-dmic", 431 "nvidia,tegra210-dmic"; 432 reg = <0x2904200 0x100>; 433 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 434 clock-names = "dmic"; 435 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 436 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 437 assigned-clock-rates = <3072000>; 438 sound-name-prefix = "DMIC3"; 439 status = "disabled"; 440 }; 441 442 tegra_dmic4: dmic@2904300 { 443 compatible = "nvidia,tegra194-dmic", 444 "nvidia,tegra210-dmic"; 445 reg = <0x2904300 0x100>; 446 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 447 clock-names = "dmic"; 448 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 449 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 450 assigned-clock-rates = <3072000>; 451 sound-name-prefix = "DMIC4"; 452 status = "disabled"; 453 }; 454 455 tegra_dspk1: dspk@2905000 { 456 compatible = "nvidia,tegra194-dspk", 457 "nvidia,tegra186-dspk"; 458 reg = <0x2905000 0x100>; 459 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 460 clock-names = "dspk"; 461 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 462 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 463 assigned-clock-rates = <12288000>; 464 sound-name-prefix = "DSPK1"; 465 status = "disabled"; 466 }; 467 468 tegra_dspk2: dspk@2905100 { 469 compatible = "nvidia,tegra194-dspk", 470 "nvidia,tegra186-dspk"; 471 reg = <0x2905100 0x100>; 472 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 473 clock-names = "dspk"; 474 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 475 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 476 assigned-clock-rates = <12288000>; 477 sound-name-prefix = "DSPK2"; 478 status = "disabled"; 479 }; 480 481 tegra_sfc1: sfc@2902000 { 482 compatible = "nvidia,tegra194-sfc", 483 "nvidia,tegra210-sfc"; 484 reg = <0x2902000 0x200>; 485 sound-name-prefix = "SFC1"; 486 status = "disabled"; 487 }; 488 489 tegra_sfc2: sfc@2902200 { 490 compatible = "nvidia,tegra194-sfc", 491 "nvidia,tegra210-sfc"; 492 reg = <0x2902200 0x200>; 493 sound-name-prefix = "SFC2"; 494 status = "disabled"; 495 }; 496 497 tegra_sfc3: sfc@2902400 { 498 compatible = "nvidia,tegra194-sfc", 499 "nvidia,tegra210-sfc"; 500 reg = <0x2902400 0x200>; 501 sound-name-prefix = "SFC3"; 502 status = "disabled"; 503 }; 504 505 tegra_sfc4: sfc@2902600 { 506 compatible = "nvidia,tegra194-sfc", 507 "nvidia,tegra210-sfc"; 508 reg = <0x2902600 0x200>; 509 sound-name-prefix = "SFC4"; 510 status = "disabled"; 511 }; 512 513 tegra_mvc1: mvc@290a000 { 514 compatible = "nvidia,tegra194-mvc", 515 "nvidia,tegra210-mvc"; 516 reg = <0x290a000 0x200>; 517 sound-name-prefix = "MVC1"; 518 status = "disabled"; 519 }; 520 521 tegra_mvc2: mvc@290a200 { 522 compatible = "nvidia,tegra194-mvc", 523 "nvidia,tegra210-mvc"; 524 reg = <0x290a200 0x200>; 525 sound-name-prefix = "MVC2"; 526 status = "disabled"; 527 }; 528 529 tegra_amx1: amx@2903000 { 530 compatible = "nvidia,tegra194-amx"; 531 reg = <0x2903000 0x100>; 532 sound-name-prefix = "AMX1"; 533 status = "disabled"; 534 }; 535 536 tegra_amx2: amx@2903100 { 537 compatible = "nvidia,tegra194-amx"; 538 reg = <0x2903100 0x100>; 539 sound-name-prefix = "AMX2"; 540 status = "disabled"; 541 }; 542 543 tegra_amx3: amx@2903200 { 544 compatible = "nvidia,tegra194-amx"; 545 reg = <0x2903200 0x100>; 546 sound-name-prefix = "AMX3"; 547 status = "disabled"; 548 }; 549 550 tegra_amx4: amx@2903300 { 551 compatible = "nvidia,tegra194-amx"; 552 reg = <0x2903300 0x100>; 553 sound-name-prefix = "AMX4"; 554 status = "disabled"; 555 }; 556 557 tegra_adx1: adx@2903800 { 558 compatible = "nvidia,tegra194-adx", 559 "nvidia,tegra210-adx"; 560 reg = <0x2903800 0x100>; 561 sound-name-prefix = "ADX1"; 562 status = "disabled"; 563 }; 564 565 tegra_adx2: adx@2903900 { 566 compatible = "nvidia,tegra194-adx", 567 "nvidia,tegra210-adx"; 568 reg = <0x2903900 0x100>; 569 sound-name-prefix = "ADX2"; 570 status = "disabled"; 571 }; 572 573 tegra_adx3: adx@2903a00 { 574 compatible = "nvidia,tegra194-adx", 575 "nvidia,tegra210-adx"; 576 reg = <0x2903a00 0x100>; 577 sound-name-prefix = "ADX3"; 578 status = "disabled"; 579 }; 580 581 tegra_adx4: adx@2903b00 { 582 compatible = "nvidia,tegra194-adx", 583 "nvidia,tegra210-adx"; 584 reg = <0x2903b00 0x100>; 585 sound-name-prefix = "ADX4"; 586 status = "disabled"; 587 }; 588 589 tegra_ope1: processing-engine@2908000 { 590 compatible = "nvidia,tegra194-ope", 591 "nvidia,tegra210-ope"; 592 reg = <0x2908000 0x100>; 593 #address-cells = <1>; 594 #size-cells = <1>; 595 ranges; 596 sound-name-prefix = "OPE1"; 597 status = "disabled"; 598 599 equalizer@2908100 { 600 compatible = "nvidia,tegra194-peq", 601 "nvidia,tegra210-peq"; 602 reg = <0x2908100 0x100>; 603 }; 604 605 dynamic-range-compressor@2908200 { 606 compatible = "nvidia,tegra194-mbdrc", 607 "nvidia,tegra210-mbdrc"; 608 reg = <0x2908200 0x200>; 609 }; 610 }; 611 612 tegra_amixer: amixer@290bb00 { 613 compatible = "nvidia,tegra194-amixer", 614 "nvidia,tegra210-amixer"; 615 reg = <0x290bb00 0x800>; 616 sound-name-prefix = "MIXER1"; 617 status = "disabled"; 618 }; 619 620 tegra_asrc: asrc@2910000 { 621 compatible = "nvidia,tegra194-asrc", 622 "nvidia,tegra186-asrc"; 623 reg = <0x2910000 0x2000>; 624 sound-name-prefix = "ASRC1"; 625 status = "disabled"; 626 }; 627 }; 628 }; 629 630 pinmux: pinmux@2430000 { 631 compatible = "nvidia,tegra194-pinmux"; 632 reg = <0x2430000 0x17000>; 633 status = "okay"; 634 635 pex_rst_c5_out_state: pex_rst_c5_out { 636 pex_rst { 637 nvidia,pins = "pex_l5_rst_n_pgg1"; 638 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 639 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 640 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 641 nvidia,tristate = <TEGRA_PIN_DISABLE>; 642 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 643 }; 644 }; 645 646 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 647 clkreq { 648 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 649 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 650 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 651 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 652 nvidia,tristate = <TEGRA_PIN_DISABLE>; 653 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 654 }; 655 }; 656 }; 657 658 mc: memory-controller@2c00000 { 659 compatible = "nvidia,tegra194-mc"; 660 reg = <0x02c00000 0x10000>, /* MC-SID */ 661 <0x02c10000 0x10000>, /* MC Broadcast*/ 662 <0x02c20000 0x10000>, /* MC0 */ 663 <0x02c30000 0x10000>, /* MC1 */ 664 <0x02c40000 0x10000>, /* MC2 */ 665 <0x02c50000 0x10000>, /* MC3 */ 666 <0x02b80000 0x10000>, /* MC4 */ 667 <0x02b90000 0x10000>, /* MC5 */ 668 <0x02ba0000 0x10000>, /* MC6 */ 669 <0x02bb0000 0x10000>, /* MC7 */ 670 <0x01700000 0x10000>, /* MC8 */ 671 <0x01710000 0x10000>, /* MC9 */ 672 <0x01720000 0x10000>, /* MC10 */ 673 <0x01730000 0x10000>, /* MC11 */ 674 <0x01740000 0x10000>, /* MC12 */ 675 <0x01750000 0x10000>, /* MC13 */ 676 <0x01760000 0x10000>, /* MC14 */ 677 <0x01770000 0x10000>; /* MC15 */ 678 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 679 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 680 "ch11", "ch12", "ch13", "ch14", "ch15"; 681 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 682 #interconnect-cells = <1>; 683 status = "disabled"; 684 685 #address-cells = <2>; 686 #size-cells = <2>; 687 688 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 689 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 690 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 691 692 /* 693 * Bit 39 of addresses passing through the memory 694 * controller selects the XBAR format used when memory 695 * is accessed. This is used to transparently access 696 * memory in the XBAR format used by the discrete GPU 697 * (bit 39 set) or Tegra (bit 39 clear). 698 * 699 * As a consequence, the operating system must ensure 700 * that bit 39 is never used implicitly, for example 701 * via an I/O virtual address mapping of an IOMMU. If 702 * devices require access to the XBAR switch, their 703 * drivers must set this bit explicitly. 704 * 705 * Limit the DMA range for memory clients to [38:0]. 706 */ 707 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 708 709 emc: external-memory-controller@2c60000 { 710 compatible = "nvidia,tegra194-emc"; 711 reg = <0x0 0x02c60000 0x0 0x90000>, 712 <0x0 0x01780000 0x0 0x80000>; 713 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&bpmp TEGRA194_CLK_EMC>; 715 clock-names = "emc"; 716 717 #interconnect-cells = <0>; 718 719 nvidia,bpmp = <&bpmp>; 720 }; 721 }; 722 723 timer@3010000 { 724 compatible = "nvidia,tegra186-timer"; 725 reg = <0x03010000 0x000e0000>; 726 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 736 status = "okay"; 737 }; 738 739 uarta: serial@3100000 { 740 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 741 reg = <0x03100000 0x40>; 742 reg-shift = <2>; 743 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 744 clocks = <&bpmp TEGRA194_CLK_UARTA>; 745 clock-names = "serial"; 746 resets = <&bpmp TEGRA194_RESET_UARTA>; 747 reset-names = "serial"; 748 status = "disabled"; 749 }; 750 751 uartb: serial@3110000 { 752 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 753 reg = <0x03110000 0x40>; 754 reg-shift = <2>; 755 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 756 clocks = <&bpmp TEGRA194_CLK_UARTB>; 757 clock-names = "serial"; 758 resets = <&bpmp TEGRA194_RESET_UARTB>; 759 reset-names = "serial"; 760 status = "disabled"; 761 }; 762 763 uartd: serial@3130000 { 764 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 765 reg = <0x03130000 0x40>; 766 reg-shift = <2>; 767 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&bpmp TEGRA194_CLK_UARTD>; 769 clock-names = "serial"; 770 resets = <&bpmp TEGRA194_RESET_UARTD>; 771 reset-names = "serial"; 772 status = "disabled"; 773 }; 774 775 uarte: serial@3140000 { 776 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 777 reg = <0x03140000 0x40>; 778 reg-shift = <2>; 779 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&bpmp TEGRA194_CLK_UARTE>; 781 clock-names = "serial"; 782 resets = <&bpmp TEGRA194_RESET_UARTE>; 783 reset-names = "serial"; 784 status = "disabled"; 785 }; 786 787 uartf: serial@3150000 { 788 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 789 reg = <0x03150000 0x40>; 790 reg-shift = <2>; 791 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&bpmp TEGRA194_CLK_UARTF>; 793 clock-names = "serial"; 794 resets = <&bpmp TEGRA194_RESET_UARTF>; 795 reset-names = "serial"; 796 status = "disabled"; 797 }; 798 799 gen1_i2c: i2c@3160000 { 800 compatible = "nvidia,tegra194-i2c"; 801 reg = <0x03160000 0x10000>; 802 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 clocks = <&bpmp TEGRA194_CLK_I2C1>; 806 clock-names = "div-clk"; 807 resets = <&bpmp TEGRA194_RESET_I2C1>; 808 reset-names = "i2c"; 809 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 810 dma-coherent; 811 dmas = <&gpcdma 21>, <&gpcdma 21>; 812 dma-names = "rx", "tx"; 813 status = "disabled"; 814 }; 815 816 uarth: serial@3170000 { 817 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 818 reg = <0x03170000 0x40>; 819 reg-shift = <2>; 820 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 821 clocks = <&bpmp TEGRA194_CLK_UARTH>; 822 clock-names = "serial"; 823 resets = <&bpmp TEGRA194_RESET_UARTH>; 824 reset-names = "serial"; 825 status = "disabled"; 826 }; 827 828 cam_i2c: i2c@3180000 { 829 compatible = "nvidia,tegra194-i2c"; 830 reg = <0x03180000 0x10000>; 831 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 clocks = <&bpmp TEGRA194_CLK_I2C3>; 835 clock-names = "div-clk"; 836 resets = <&bpmp TEGRA194_RESET_I2C3>; 837 reset-names = "i2c"; 838 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 839 dma-coherent; 840 dmas = <&gpcdma 23>, <&gpcdma 23>; 841 dma-names = "rx", "tx"; 842 status = "disabled"; 843 }; 844 845 /* shares pads with dpaux1 */ 846 dp_aux_ch1_i2c: i2c@3190000 { 847 compatible = "nvidia,tegra194-i2c"; 848 reg = <0x03190000 0x10000>; 849 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 clocks = <&bpmp TEGRA194_CLK_I2C4>; 853 clock-names = "div-clk"; 854 resets = <&bpmp TEGRA194_RESET_I2C4>; 855 reset-names = "i2c"; 856 pinctrl-0 = <&state_dpaux1_i2c>; 857 pinctrl-1 = <&state_dpaux1_off>; 858 pinctrl-names = "default", "idle"; 859 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 860 dma-coherent; 861 dmas = <&gpcdma 26>, <&gpcdma 26>; 862 dma-names = "rx", "tx"; 863 status = "disabled"; 864 }; 865 866 /* shares pads with dpaux0 */ 867 dp_aux_ch0_i2c: i2c@31b0000 { 868 compatible = "nvidia,tegra194-i2c"; 869 reg = <0x031b0000 0x10000>; 870 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 clocks = <&bpmp TEGRA194_CLK_I2C6>; 874 clock-names = "div-clk"; 875 resets = <&bpmp TEGRA194_RESET_I2C6>; 876 reset-names = "i2c"; 877 pinctrl-0 = <&state_dpaux0_i2c>; 878 pinctrl-1 = <&state_dpaux0_off>; 879 pinctrl-names = "default", "idle"; 880 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 881 dma-coherent; 882 dmas = <&gpcdma 30>, <&gpcdma 30>; 883 dma-names = "rx", "tx"; 884 status = "disabled"; 885 }; 886 887 /* shares pads with dpaux2 */ 888 dp_aux_ch2_i2c: i2c@31c0000 { 889 compatible = "nvidia,tegra194-i2c"; 890 reg = <0x031c0000 0x10000>; 891 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 clocks = <&bpmp TEGRA194_CLK_I2C7>; 895 clock-names = "div-clk"; 896 resets = <&bpmp TEGRA194_RESET_I2C7>; 897 reset-names = "i2c"; 898 pinctrl-0 = <&state_dpaux2_i2c>; 899 pinctrl-1 = <&state_dpaux2_off>; 900 pinctrl-names = "default", "idle"; 901 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 902 dma-coherent; 903 dmas = <&gpcdma 27>, <&gpcdma 27>; 904 dma-names = "rx", "tx"; 905 status = "disabled"; 906 }; 907 908 /* shares pads with dpaux3 */ 909 dp_aux_ch3_i2c: i2c@31e0000 { 910 compatible = "nvidia,tegra194-i2c"; 911 reg = <0x031e0000 0x10000>; 912 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 clocks = <&bpmp TEGRA194_CLK_I2C9>; 916 clock-names = "div-clk"; 917 resets = <&bpmp TEGRA194_RESET_I2C9>; 918 reset-names = "i2c"; 919 pinctrl-0 = <&state_dpaux3_i2c>; 920 pinctrl-1 = <&state_dpaux3_off>; 921 pinctrl-names = "default", "idle"; 922 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 923 dma-coherent; 924 dmas = <&gpcdma 31>, <&gpcdma 31>; 925 dma-names = "rx", "tx"; 926 status = "disabled"; 927 }; 928 929 spi@3270000 { 930 compatible = "nvidia,tegra194-qspi"; 931 reg = <0x3270000 0x1000>; 932 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 936 <&bpmp TEGRA194_CLK_QSPI0_PM>; 937 clock-names = "qspi", "qspi_out"; 938 resets = <&bpmp TEGRA194_RESET_QSPI0>; 939 reset-names = "qspi"; 940 status = "disabled"; 941 }; 942 943 spi@3300000 { 944 compatible = "nvidia,tegra194-qspi"; 945 reg = <0x3300000 0x1000>; 946 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 947 #address-cells = <1>; 948 #size-cells = <0>; 949 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 950 <&bpmp TEGRA194_CLK_QSPI1_PM>; 951 clock-names = "qspi", "qspi_out"; 952 resets = <&bpmp TEGRA194_RESET_QSPI1>; 953 reset-names = "qspi"; 954 status = "disabled"; 955 }; 956 957 pwm1: pwm@3280000 { 958 compatible = "nvidia,tegra194-pwm", 959 "nvidia,tegra186-pwm"; 960 reg = <0x3280000 0x10000>; 961 clocks = <&bpmp TEGRA194_CLK_PWM1>; 962 resets = <&bpmp TEGRA194_RESET_PWM1>; 963 reset-names = "pwm"; 964 status = "disabled"; 965 #pwm-cells = <2>; 966 }; 967 968 pwm2: pwm@3290000 { 969 compatible = "nvidia,tegra194-pwm", 970 "nvidia,tegra186-pwm"; 971 reg = <0x3290000 0x10000>; 972 clocks = <&bpmp TEGRA194_CLK_PWM2>; 973 resets = <&bpmp TEGRA194_RESET_PWM2>; 974 reset-names = "pwm"; 975 status = "disabled"; 976 #pwm-cells = <2>; 977 }; 978 979 pwm3: pwm@32a0000 { 980 compatible = "nvidia,tegra194-pwm", 981 "nvidia,tegra186-pwm"; 982 reg = <0x32a0000 0x10000>; 983 clocks = <&bpmp TEGRA194_CLK_PWM3>; 984 resets = <&bpmp TEGRA194_RESET_PWM3>; 985 reset-names = "pwm"; 986 status = "disabled"; 987 #pwm-cells = <2>; 988 }; 989 990 pwm5: pwm@32c0000 { 991 compatible = "nvidia,tegra194-pwm", 992 "nvidia,tegra186-pwm"; 993 reg = <0x32c0000 0x10000>; 994 clocks = <&bpmp TEGRA194_CLK_PWM5>; 995 resets = <&bpmp TEGRA194_RESET_PWM5>; 996 reset-names = "pwm"; 997 status = "disabled"; 998 #pwm-cells = <2>; 999 }; 1000 1001 pwm6: pwm@32d0000 { 1002 compatible = "nvidia,tegra194-pwm", 1003 "nvidia,tegra186-pwm"; 1004 reg = <0x32d0000 0x10000>; 1005 clocks = <&bpmp TEGRA194_CLK_PWM6>; 1006 resets = <&bpmp TEGRA194_RESET_PWM6>; 1007 reset-names = "pwm"; 1008 status = "disabled"; 1009 #pwm-cells = <2>; 1010 }; 1011 1012 pwm7: pwm@32e0000 { 1013 compatible = "nvidia,tegra194-pwm", 1014 "nvidia,tegra186-pwm"; 1015 reg = <0x32e0000 0x10000>; 1016 clocks = <&bpmp TEGRA194_CLK_PWM7>; 1017 resets = <&bpmp TEGRA194_RESET_PWM7>; 1018 reset-names = "pwm"; 1019 status = "disabled"; 1020 #pwm-cells = <2>; 1021 }; 1022 1023 pwm8: pwm@32f0000 { 1024 compatible = "nvidia,tegra194-pwm", 1025 "nvidia,tegra186-pwm"; 1026 reg = <0x32f0000 0x10000>; 1027 clocks = <&bpmp TEGRA194_CLK_PWM8>; 1028 resets = <&bpmp TEGRA194_RESET_PWM8>; 1029 reset-names = "pwm"; 1030 status = "disabled"; 1031 #pwm-cells = <2>; 1032 }; 1033 1034 sdmmc1: mmc@3400000 { 1035 compatible = "nvidia,tegra194-sdhci"; 1036 reg = <0x03400000 0x10000>; 1037 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1039 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1040 clock-names = "sdhci", "tmclk"; 1041 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1042 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1043 assigned-clock-parents = 1044 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1045 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1046 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 1047 reset-names = "sdhci"; 1048 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1049 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1050 interconnect-names = "dma-mem", "write"; 1051 iommus = <&smmu TEGRA194_SID_SDMMC1>; 1052 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1053 pinctrl-0 = <&sdmmc1_3v3>; 1054 pinctrl-1 = <&sdmmc1_1v8>; 1055 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 1056 <0x07>; 1057 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1058 <0x07>; 1059 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1060 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1061 <0x07>; 1062 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1063 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1064 nvidia,default-tap = <0x9>; 1065 nvidia,default-trim = <0x5>; 1066 sd-uhs-sdr25; 1067 sd-uhs-sdr50; 1068 sd-uhs-ddr50; 1069 sd-uhs-sdr104; 1070 status = "disabled"; 1071 }; 1072 1073 sdmmc3: mmc@3440000 { 1074 compatible = "nvidia,tegra194-sdhci"; 1075 reg = <0x03440000 0x10000>; 1076 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1077 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1078 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1079 clock-names = "sdhci", "tmclk"; 1080 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1081 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1082 assigned-clock-parents = 1083 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1084 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1085 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1086 reset-names = "sdhci"; 1087 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1088 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1089 interconnect-names = "dma-mem", "write"; 1090 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1091 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1092 pinctrl-0 = <&sdmmc3_3v3>; 1093 pinctrl-1 = <&sdmmc3_1v8>; 1094 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1095 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1096 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1097 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1098 <0x07>; 1099 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1100 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1101 <0x07>; 1102 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1103 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1104 nvidia,default-tap = <0x9>; 1105 nvidia,default-trim = <0x5>; 1106 sd-uhs-sdr25; 1107 sd-uhs-sdr50; 1108 sd-uhs-ddr50; 1109 sd-uhs-sdr104; 1110 status = "disabled"; 1111 }; 1112 1113 sdmmc4: mmc@3460000 { 1114 compatible = "nvidia,tegra194-sdhci"; 1115 reg = <0x03460000 0x10000>; 1116 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1118 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1119 clock-names = "sdhci", "tmclk"; 1120 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1121 <&bpmp TEGRA194_CLK_PLLC4>; 1122 assigned-clock-parents = 1123 <&bpmp TEGRA194_CLK_PLLC4>; 1124 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1125 reset-names = "sdhci"; 1126 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1127 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1128 interconnect-names = "dma-mem", "write"; 1129 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1130 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1131 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1132 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1133 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1134 <0x0a>; 1135 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1136 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1137 <0x0a>; 1138 nvidia,default-tap = <0x8>; 1139 nvidia,default-trim = <0x14>; 1140 nvidia,dqs-trim = <40>; 1141 cap-mmc-highspeed; 1142 mmc-ddr-1_8v; 1143 mmc-hs200-1_8v; 1144 mmc-hs400-1_8v; 1145 mmc-hs400-enhanced-strobe; 1146 supports-cqe; 1147 status = "disabled"; 1148 }; 1149 1150 hda@3510000 { 1151 compatible = "nvidia,tegra194-hda"; 1152 reg = <0x3510000 0x10000>; 1153 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1154 clocks = <&bpmp TEGRA194_CLK_HDA>, 1155 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1156 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1157 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1158 resets = <&bpmp TEGRA194_RESET_HDA>, 1159 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1160 reset-names = "hda", "hda2hdmi"; 1161 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1162 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1163 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1164 interconnect-names = "dma-mem", "write"; 1165 iommus = <&smmu TEGRA194_SID_HDA>; 1166 status = "disabled"; 1167 }; 1168 1169 xusb_padctl: padctl@3520000 { 1170 compatible = "nvidia,tegra194-xusb-padctl"; 1171 reg = <0x03520000 0x1000>, 1172 <0x03540000 0x1000>; 1173 reg-names = "padctl", "ao"; 1174 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1175 1176 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1177 reset-names = "padctl"; 1178 1179 status = "disabled"; 1180 1181 pads { 1182 usb2 { 1183 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1184 clock-names = "trk"; 1185 1186 lanes { 1187 usb2-0 { 1188 nvidia,function = "xusb"; 1189 status = "disabled"; 1190 #phy-cells = <0>; 1191 }; 1192 1193 usb2-1 { 1194 nvidia,function = "xusb"; 1195 status = "disabled"; 1196 #phy-cells = <0>; 1197 }; 1198 1199 usb2-2 { 1200 nvidia,function = "xusb"; 1201 status = "disabled"; 1202 #phy-cells = <0>; 1203 }; 1204 1205 usb2-3 { 1206 nvidia,function = "xusb"; 1207 status = "disabled"; 1208 #phy-cells = <0>; 1209 }; 1210 }; 1211 }; 1212 1213 usb3 { 1214 lanes { 1215 usb3-0 { 1216 nvidia,function = "xusb"; 1217 status = "disabled"; 1218 #phy-cells = <0>; 1219 }; 1220 1221 usb3-1 { 1222 nvidia,function = "xusb"; 1223 status = "disabled"; 1224 #phy-cells = <0>; 1225 }; 1226 1227 usb3-2 { 1228 nvidia,function = "xusb"; 1229 status = "disabled"; 1230 #phy-cells = <0>; 1231 }; 1232 1233 usb3-3 { 1234 nvidia,function = "xusb"; 1235 status = "disabled"; 1236 #phy-cells = <0>; 1237 }; 1238 }; 1239 }; 1240 }; 1241 1242 ports { 1243 usb2-0 { 1244 status = "disabled"; 1245 }; 1246 1247 usb2-1 { 1248 status = "disabled"; 1249 }; 1250 1251 usb2-2 { 1252 status = "disabled"; 1253 }; 1254 1255 usb2-3 { 1256 status = "disabled"; 1257 }; 1258 1259 usb3-0 { 1260 status = "disabled"; 1261 }; 1262 1263 usb3-1 { 1264 status = "disabled"; 1265 }; 1266 1267 usb3-2 { 1268 status = "disabled"; 1269 }; 1270 1271 usb3-3 { 1272 status = "disabled"; 1273 }; 1274 }; 1275 }; 1276 1277 usb@3550000 { 1278 compatible = "nvidia,tegra194-xudc"; 1279 reg = <0x03550000 0x8000>, 1280 <0x03558000 0x1000>; 1281 reg-names = "base", "fpci"; 1282 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1284 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1285 <&bpmp TEGRA194_CLK_XUSB_SS>, 1286 <&bpmp TEGRA194_CLK_XUSB_FS>; 1287 clock-names = "dev", "ss", "ss_src", "fs_src"; 1288 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1289 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1290 interconnect-names = "dma-mem", "write"; 1291 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1292 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1293 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1294 power-domain-names = "dev", "ss"; 1295 nvidia,xusb-padctl = <&xusb_padctl>; 1296 status = "disabled"; 1297 }; 1298 1299 usb@3610000 { 1300 compatible = "nvidia,tegra194-xusb"; 1301 reg = <0x03610000 0x40000>, 1302 <0x03600000 0x10000>; 1303 reg-names = "hcd", "fpci"; 1304 1305 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1307 1308 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1309 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1310 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1311 <&bpmp TEGRA194_CLK_XUSB_SS>, 1312 <&bpmp TEGRA194_CLK_CLK_M>, 1313 <&bpmp TEGRA194_CLK_XUSB_FS>, 1314 <&bpmp TEGRA194_CLK_UTMIPLL>, 1315 <&bpmp TEGRA194_CLK_CLK_M>, 1316 <&bpmp TEGRA194_CLK_PLLE>; 1317 clock-names = "xusb_host", "xusb_falcon_src", 1318 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1319 "xusb_fs_src", "pll_u_480m", "clk_m", 1320 "pll_e"; 1321 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1322 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1323 interconnect-names = "dma-mem", "write"; 1324 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1325 1326 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1327 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1328 power-domain-names = "xusb_host", "xusb_ss"; 1329 1330 nvidia,xusb-padctl = <&xusb_padctl>; 1331 status = "disabled"; 1332 }; 1333 1334 fuse@3820000 { 1335 compatible = "nvidia,tegra194-efuse"; 1336 reg = <0x03820000 0x10000>; 1337 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1338 clock-names = "fuse"; 1339 }; 1340 1341 gic: interrupt-controller@3881000 { 1342 compatible = "arm,gic-400"; 1343 #interrupt-cells = <3>; 1344 interrupt-controller; 1345 reg = <0x03881000 0x1000>, 1346 <0x03882000 0x2000>, 1347 <0x03884000 0x2000>, 1348 <0x03886000 0x2000>; 1349 interrupts = <GIC_PPI 9 1350 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1351 interrupt-parent = <&gic>; 1352 }; 1353 1354 cec@3960000 { 1355 compatible = "nvidia,tegra194-cec"; 1356 reg = <0x03960000 0x10000>; 1357 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1358 clocks = <&bpmp TEGRA194_CLK_CEC>; 1359 clock-names = "cec"; 1360 status = "disabled"; 1361 }; 1362 1363 hte_lic: hardware-timestamp@3aa0000 { 1364 compatible = "nvidia,tegra194-gte-lic"; 1365 reg = <0x3aa0000 0x10000>; 1366 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1367 nvidia,int-threshold = <1>; 1368 nvidia,slices = <11>; 1369 #timestamp-cells = <1>; 1370 status = "okay"; 1371 }; 1372 1373 hsp_top0: hsp@3c00000 { 1374 compatible = "nvidia,tegra194-hsp"; 1375 reg = <0x03c00000 0xa0000>; 1376 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1385 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1386 "shared3", "shared4", "shared5", "shared6", 1387 "shared7"; 1388 #mbox-cells = <2>; 1389 }; 1390 1391 p2u_hsio_0: phy@3e10000 { 1392 compatible = "nvidia,tegra194-p2u"; 1393 reg = <0x03e10000 0x10000>; 1394 reg-names = "ctl"; 1395 1396 #phy-cells = <0>; 1397 }; 1398 1399 p2u_hsio_1: phy@3e20000 { 1400 compatible = "nvidia,tegra194-p2u"; 1401 reg = <0x03e20000 0x10000>; 1402 reg-names = "ctl"; 1403 1404 #phy-cells = <0>; 1405 }; 1406 1407 p2u_hsio_2: phy@3e30000 { 1408 compatible = "nvidia,tegra194-p2u"; 1409 reg = <0x03e30000 0x10000>; 1410 reg-names = "ctl"; 1411 1412 #phy-cells = <0>; 1413 }; 1414 1415 p2u_hsio_3: phy@3e40000 { 1416 compatible = "nvidia,tegra194-p2u"; 1417 reg = <0x03e40000 0x10000>; 1418 reg-names = "ctl"; 1419 1420 #phy-cells = <0>; 1421 }; 1422 1423 p2u_hsio_4: phy@3e50000 { 1424 compatible = "nvidia,tegra194-p2u"; 1425 reg = <0x03e50000 0x10000>; 1426 reg-names = "ctl"; 1427 1428 #phy-cells = <0>; 1429 }; 1430 1431 p2u_hsio_5: phy@3e60000 { 1432 compatible = "nvidia,tegra194-p2u"; 1433 reg = <0x03e60000 0x10000>; 1434 reg-names = "ctl"; 1435 1436 #phy-cells = <0>; 1437 }; 1438 1439 p2u_hsio_6: phy@3e70000 { 1440 compatible = "nvidia,tegra194-p2u"; 1441 reg = <0x03e70000 0x10000>; 1442 reg-names = "ctl"; 1443 1444 #phy-cells = <0>; 1445 }; 1446 1447 p2u_hsio_7: phy@3e80000 { 1448 compatible = "nvidia,tegra194-p2u"; 1449 reg = <0x03e80000 0x10000>; 1450 reg-names = "ctl"; 1451 1452 #phy-cells = <0>; 1453 }; 1454 1455 p2u_hsio_8: phy@3e90000 { 1456 compatible = "nvidia,tegra194-p2u"; 1457 reg = <0x03e90000 0x10000>; 1458 reg-names = "ctl"; 1459 1460 #phy-cells = <0>; 1461 }; 1462 1463 p2u_hsio_9: phy@3ea0000 { 1464 compatible = "nvidia,tegra194-p2u"; 1465 reg = <0x03ea0000 0x10000>; 1466 reg-names = "ctl"; 1467 1468 #phy-cells = <0>; 1469 }; 1470 1471 p2u_nvhs_0: phy@3eb0000 { 1472 compatible = "nvidia,tegra194-p2u"; 1473 reg = <0x03eb0000 0x10000>; 1474 reg-names = "ctl"; 1475 1476 #phy-cells = <0>; 1477 }; 1478 1479 p2u_nvhs_1: phy@3ec0000 { 1480 compatible = "nvidia,tegra194-p2u"; 1481 reg = <0x03ec0000 0x10000>; 1482 reg-names = "ctl"; 1483 1484 #phy-cells = <0>; 1485 }; 1486 1487 p2u_nvhs_2: phy@3ed0000 { 1488 compatible = "nvidia,tegra194-p2u"; 1489 reg = <0x03ed0000 0x10000>; 1490 reg-names = "ctl"; 1491 1492 #phy-cells = <0>; 1493 }; 1494 1495 p2u_nvhs_3: phy@3ee0000 { 1496 compatible = "nvidia,tegra194-p2u"; 1497 reg = <0x03ee0000 0x10000>; 1498 reg-names = "ctl"; 1499 1500 #phy-cells = <0>; 1501 }; 1502 1503 p2u_nvhs_4: phy@3ef0000 { 1504 compatible = "nvidia,tegra194-p2u"; 1505 reg = <0x03ef0000 0x10000>; 1506 reg-names = "ctl"; 1507 1508 #phy-cells = <0>; 1509 }; 1510 1511 p2u_nvhs_5: phy@3f00000 { 1512 compatible = "nvidia,tegra194-p2u"; 1513 reg = <0x03f00000 0x10000>; 1514 reg-names = "ctl"; 1515 1516 #phy-cells = <0>; 1517 }; 1518 1519 p2u_nvhs_6: phy@3f10000 { 1520 compatible = "nvidia,tegra194-p2u"; 1521 reg = <0x03f10000 0x10000>; 1522 reg-names = "ctl"; 1523 1524 #phy-cells = <0>; 1525 }; 1526 1527 p2u_nvhs_7: phy@3f20000 { 1528 compatible = "nvidia,tegra194-p2u"; 1529 reg = <0x03f20000 0x10000>; 1530 reg-names = "ctl"; 1531 1532 #phy-cells = <0>; 1533 }; 1534 1535 p2u_hsio_10: phy@3f30000 { 1536 compatible = "nvidia,tegra194-p2u"; 1537 reg = <0x03f30000 0x10000>; 1538 reg-names = "ctl"; 1539 1540 #phy-cells = <0>; 1541 }; 1542 1543 p2u_hsio_11: phy@3f40000 { 1544 compatible = "nvidia,tegra194-p2u"; 1545 reg = <0x03f40000 0x10000>; 1546 reg-names = "ctl"; 1547 1548 #phy-cells = <0>; 1549 }; 1550 1551 sce-noc@b600000 { 1552 compatible = "nvidia,tegra194-sce-noc"; 1553 reg = <0xb600000 0x1000>; 1554 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1555 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1556 nvidia,axi2apb = <&axi2apb>; 1557 nvidia,apbmisc = <&apbmisc>; 1558 status = "okay"; 1559 }; 1560 1561 rce-noc@be00000 { 1562 compatible = "nvidia,tegra194-rce-noc"; 1563 reg = <0xbe00000 0x1000>; 1564 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1566 nvidia,axi2apb = <&axi2apb>; 1567 nvidia,apbmisc = <&apbmisc>; 1568 status = "okay"; 1569 }; 1570 1571 hsp_aon: hsp@c150000 { 1572 compatible = "nvidia,tegra194-hsp"; 1573 reg = <0x0c150000 0x90000>; 1574 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1578 /* 1579 * Shared interrupt 0 is routed only to AON/SPE, so 1580 * we only have 4 shared interrupts for the CCPLEX. 1581 */ 1582 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1583 #mbox-cells = <2>; 1584 }; 1585 1586 hte_aon: hardware-timestamp@c1e0000 { 1587 compatible = "nvidia,tegra194-gte-aon"; 1588 reg = <0xc1e0000 0x10000>; 1589 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1590 nvidia,int-threshold = <1>; 1591 nvidia,slices = <3>; 1592 #timestamp-cells = <1>; 1593 status = "okay"; 1594 }; 1595 1596 gen2_i2c: i2c@c240000 { 1597 compatible = "nvidia,tegra194-i2c"; 1598 reg = <0x0c240000 0x10000>; 1599 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1603 clock-names = "div-clk"; 1604 resets = <&bpmp TEGRA194_RESET_I2C2>; 1605 reset-names = "i2c"; 1606 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1607 dma-coherent; 1608 dmas = <&gpcdma 22>, <&gpcdma 22>; 1609 dma-names = "rx", "tx"; 1610 status = "disabled"; 1611 }; 1612 1613 gen8_i2c: i2c@c250000 { 1614 compatible = "nvidia,tegra194-i2c"; 1615 reg = <0x0c250000 0x10000>; 1616 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1620 clock-names = "div-clk"; 1621 resets = <&bpmp TEGRA194_RESET_I2C8>; 1622 reset-names = "i2c"; 1623 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1624 dma-coherent; 1625 dmas = <&gpcdma 0>, <&gpcdma 0>; 1626 dma-names = "rx", "tx"; 1627 status = "disabled"; 1628 }; 1629 1630 uartc: serial@c280000 { 1631 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1632 reg = <0x0c280000 0x40>; 1633 reg-shift = <2>; 1634 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1635 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1636 clock-names = "serial"; 1637 resets = <&bpmp TEGRA194_RESET_UARTC>; 1638 reset-names = "serial"; 1639 status = "disabled"; 1640 }; 1641 1642 uartg: serial@c290000 { 1643 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1644 reg = <0x0c290000 0x40>; 1645 reg-shift = <2>; 1646 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1647 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1648 clock-names = "serial"; 1649 resets = <&bpmp TEGRA194_RESET_UARTG>; 1650 reset-names = "serial"; 1651 status = "disabled"; 1652 }; 1653 1654 rtc: rtc@c2a0000 { 1655 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1656 reg = <0x0c2a0000 0x10000>; 1657 interrupt-parent = <&pmc>; 1658 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1659 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1660 clock-names = "rtc"; 1661 status = "disabled"; 1662 }; 1663 1664 gpio_aon: gpio@c2f0000 { 1665 compatible = "nvidia,tegra194-gpio-aon"; 1666 reg-names = "security", "gpio"; 1667 reg = <0xc2f0000 0x1000>, 1668 <0xc2f1000 0x1000>; 1669 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1673 gpio-controller; 1674 #gpio-cells = <2>; 1675 interrupt-controller; 1676 #interrupt-cells = <2>; 1677 gpio-range = <&pinmux_aon 0 0 30>; 1678 }; 1679 1680 pinmux_aon: pinmux@c300000 { 1681 compatible = "nvidia,tegra194-pinmux-aon"; 1682 reg = <0xc300000 0x4000>; 1683 1684 status = "okay"; 1685 }; 1686 1687 pwm4: pwm@c340000 { 1688 compatible = "nvidia,tegra194-pwm", 1689 "nvidia,tegra186-pwm"; 1690 reg = <0xc340000 0x10000>; 1691 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1692 resets = <&bpmp TEGRA194_RESET_PWM4>; 1693 reset-names = "pwm"; 1694 status = "disabled"; 1695 #pwm-cells = <2>; 1696 }; 1697 1698 pmc: pmc@c360000 { 1699 compatible = "nvidia,tegra194-pmc"; 1700 reg = <0x0c360000 0x10000>, 1701 <0x0c370000 0x10000>, 1702 <0x0c380000 0x10000>, 1703 <0x0c390000 0x10000>, 1704 <0x0c3a0000 0x10000>; 1705 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1706 1707 #interrupt-cells = <2>; 1708 interrupt-controller; 1709 sdmmc1_3v3: sdmmc1-3v3 { 1710 pins = "sdmmc1-hv"; 1711 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1712 }; 1713 1714 sdmmc1_1v8: sdmmc1-1v8 { 1715 pins = "sdmmc1-hv"; 1716 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1717 }; 1718 sdmmc3_3v3: sdmmc3-3v3 { 1719 pins = "sdmmc3-hv"; 1720 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1721 }; 1722 1723 sdmmc3_1v8: sdmmc3-1v8 { 1724 pins = "sdmmc3-hv"; 1725 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1726 }; 1727 1728 }; 1729 1730 aon-noc@c600000 { 1731 compatible = "nvidia,tegra194-aon-noc"; 1732 reg = <0xc600000 0x1000>; 1733 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1735 nvidia,apbmisc = <&apbmisc>; 1736 status = "okay"; 1737 }; 1738 1739 bpmp-noc@d600000 { 1740 compatible = "nvidia,tegra194-bpmp-noc"; 1741 reg = <0xd600000 0x1000>; 1742 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1744 nvidia,axi2apb = <&axi2apb>; 1745 nvidia,apbmisc = <&apbmisc>; 1746 status = "okay"; 1747 }; 1748 1749 iommu@10000000 { 1750 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1751 reg = <0x10000000 0x800000>; 1752 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1817 stream-match-mask = <0x7f80>; 1818 #global-interrupts = <1>; 1819 #iommu-cells = <1>; 1820 1821 nvidia,memory-controller = <&mc>; 1822 status = "disabled"; 1823 }; 1824 1825 smmu: iommu@12000000 { 1826 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1827 reg = <0x12000000 0x800000>, 1828 <0x11000000 0x800000>; 1829 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1895 stream-match-mask = <0x7f80>; 1896 #global-interrupts = <2>; 1897 #iommu-cells = <1>; 1898 1899 nvidia,memory-controller = <&mc>; 1900 status = "okay"; 1901 }; 1902 1903 host1x@13e00000 { 1904 compatible = "nvidia,tegra194-host1x"; 1905 reg = <0x13e00000 0x10000>, 1906 <0x13e10000 0x10000>; 1907 reg-names = "hypervisor", "vm"; 1908 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1910 interrupt-names = "syncpt", "host1x"; 1911 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1912 clock-names = "host1x"; 1913 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1914 reset-names = "host1x"; 1915 1916 #address-cells = <1>; 1917 #size-cells = <1>; 1918 1919 ranges = <0x14800000 0x14800000 0x02800000>; 1920 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1921 interconnect-names = "dma-mem"; 1922 iommus = <&smmu TEGRA194_SID_HOST1X>; 1923 1924 /* Context isolation domains */ 1925 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1926 <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1927 <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1928 <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1929 <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1930 <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1931 <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1932 <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1933 1934 nvdec@15140000 { 1935 compatible = "nvidia,tegra194-nvdec"; 1936 reg = <0x15140000 0x00040000>; 1937 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1938 clock-names = "nvdec"; 1939 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1940 reset-names = "nvdec"; 1941 1942 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1943 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1944 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1945 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1946 interconnect-names = "dma-mem", "read-1", "write"; 1947 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1948 dma-coherent; 1949 1950 nvidia,host1x-class = <0xf5>; 1951 }; 1952 1953 display-hub@15200000 { 1954 compatible = "nvidia,tegra194-display"; 1955 reg = <0x15200000 0x00040000>; 1956 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1957 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1958 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1959 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1960 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1961 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1962 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1963 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1964 "wgrp3", "wgrp4", "wgrp5"; 1965 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1966 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1967 clock-names = "disp", "hub"; 1968 status = "disabled"; 1969 1970 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1971 1972 #address-cells = <1>; 1973 #size-cells = <1>; 1974 1975 ranges = <0x15200000 0x15200000 0x40000>; 1976 1977 display@15200000 { 1978 compatible = "nvidia,tegra194-dc"; 1979 reg = <0x15200000 0x10000>; 1980 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1981 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1982 clock-names = "dc"; 1983 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1984 reset-names = "dc"; 1985 1986 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1987 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1988 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1989 interconnect-names = "dma-mem", "read-1"; 1990 1991 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1992 nvidia,head = <0>; 1993 }; 1994 1995 display@15210000 { 1996 compatible = "nvidia,tegra194-dc"; 1997 reg = <0x15210000 0x10000>; 1998 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1999 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 2000 clock-names = "dc"; 2001 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 2002 reset-names = "dc"; 2003 2004 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 2005 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2006 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2007 interconnect-names = "dma-mem", "read-1"; 2008 2009 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2010 nvidia,head = <1>; 2011 }; 2012 2013 display@15220000 { 2014 compatible = "nvidia,tegra194-dc"; 2015 reg = <0x15220000 0x10000>; 2016 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2017 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 2018 clock-names = "dc"; 2019 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 2020 reset-names = "dc"; 2021 2022 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2023 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2024 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2025 interconnect-names = "dma-mem", "read-1"; 2026 2027 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2028 nvidia,head = <2>; 2029 }; 2030 2031 display@15230000 { 2032 compatible = "nvidia,tegra194-dc"; 2033 reg = <0x15230000 0x10000>; 2034 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2035 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 2036 clock-names = "dc"; 2037 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 2038 reset-names = "dc"; 2039 2040 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2041 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2042 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2043 interconnect-names = "dma-mem", "read-1"; 2044 2045 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2046 nvidia,head = <3>; 2047 }; 2048 }; 2049 2050 vic@15340000 { 2051 compatible = "nvidia,tegra194-vic"; 2052 reg = <0x15340000 0x00040000>; 2053 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2054 clocks = <&bpmp TEGRA194_CLK_VIC>; 2055 clock-names = "vic"; 2056 resets = <&bpmp TEGRA194_RESET_VIC>; 2057 reset-names = "vic"; 2058 2059 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2060 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2061 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2062 interconnect-names = "dma-mem", "write"; 2063 iommus = <&smmu TEGRA194_SID_VIC>; 2064 dma-coherent; 2065 }; 2066 2067 nvjpg@15380000 { 2068 compatible = "nvidia,tegra194-nvjpg"; 2069 reg = <0x15380000 0x40000>; 2070 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2071 clock-names = "nvjpg"; 2072 resets = <&bpmp TEGRA194_RESET_NVJPG>; 2073 reset-names = "nvjpg"; 2074 2075 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2076 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2077 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2078 interconnect-names = "dma-mem", "write"; 2079 iommus = <&smmu TEGRA194_SID_NVJPG>; 2080 dma-coherent; 2081 }; 2082 2083 nvdec@15480000 { 2084 compatible = "nvidia,tegra194-nvdec"; 2085 reg = <0x15480000 0x00040000>; 2086 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 2087 clock-names = "nvdec"; 2088 resets = <&bpmp TEGRA194_RESET_NVDEC>; 2089 reset-names = "nvdec"; 2090 2091 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 2092 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 2093 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 2094 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 2095 interconnect-names = "dma-mem", "read-1", "write"; 2096 iommus = <&smmu TEGRA194_SID_NVDEC>; 2097 dma-coherent; 2098 2099 nvidia,host1x-class = <0xf0>; 2100 }; 2101 2102 nvenc@154c0000 { 2103 compatible = "nvidia,tegra194-nvenc"; 2104 reg = <0x154c0000 0x40000>; 2105 clocks = <&bpmp TEGRA194_CLK_NVENC>; 2106 clock-names = "nvenc"; 2107 resets = <&bpmp TEGRA194_RESET_NVENC>; 2108 reset-names = "nvenc"; 2109 2110 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2111 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2112 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2113 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2114 interconnect-names = "dma-mem", "read-1", "write"; 2115 iommus = <&smmu TEGRA194_SID_NVENC>; 2116 dma-coherent; 2117 2118 nvidia,host1x-class = <0x21>; 2119 }; 2120 2121 dpaux0: dpaux@155c0000 { 2122 compatible = "nvidia,tegra194-dpaux"; 2123 reg = <0x155c0000 0x10000>; 2124 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 2125 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 2126 <&bpmp TEGRA194_CLK_PLLDP>; 2127 clock-names = "dpaux", "parent"; 2128 resets = <&bpmp TEGRA194_RESET_DPAUX>; 2129 reset-names = "dpaux"; 2130 status = "disabled"; 2131 2132 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2133 2134 state_dpaux0_aux: pinmux-aux { 2135 groups = "dpaux-io"; 2136 function = "aux"; 2137 }; 2138 2139 state_dpaux0_i2c: pinmux-i2c { 2140 groups = "dpaux-io"; 2141 function = "i2c"; 2142 }; 2143 2144 state_dpaux0_off: pinmux-off { 2145 groups = "dpaux-io"; 2146 function = "off"; 2147 }; 2148 2149 i2c-bus { 2150 #address-cells = <1>; 2151 #size-cells = <0>; 2152 }; 2153 }; 2154 2155 dpaux1: dpaux@155d0000 { 2156 compatible = "nvidia,tegra194-dpaux"; 2157 reg = <0x155d0000 0x10000>; 2158 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2159 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 2160 <&bpmp TEGRA194_CLK_PLLDP>; 2161 clock-names = "dpaux", "parent"; 2162 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2163 reset-names = "dpaux"; 2164 status = "disabled"; 2165 2166 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2167 2168 state_dpaux1_aux: pinmux-aux { 2169 groups = "dpaux-io"; 2170 function = "aux"; 2171 }; 2172 2173 state_dpaux1_i2c: pinmux-i2c { 2174 groups = "dpaux-io"; 2175 function = "i2c"; 2176 }; 2177 2178 state_dpaux1_off: pinmux-off { 2179 groups = "dpaux-io"; 2180 function = "off"; 2181 }; 2182 2183 i2c-bus { 2184 #address-cells = <1>; 2185 #size-cells = <0>; 2186 }; 2187 }; 2188 2189 dpaux2: dpaux@155e0000 { 2190 compatible = "nvidia,tegra194-dpaux"; 2191 reg = <0x155e0000 0x10000>; 2192 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2193 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2194 <&bpmp TEGRA194_CLK_PLLDP>; 2195 clock-names = "dpaux", "parent"; 2196 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2197 reset-names = "dpaux"; 2198 status = "disabled"; 2199 2200 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2201 2202 state_dpaux2_aux: pinmux-aux { 2203 groups = "dpaux-io"; 2204 function = "aux"; 2205 }; 2206 2207 state_dpaux2_i2c: pinmux-i2c { 2208 groups = "dpaux-io"; 2209 function = "i2c"; 2210 }; 2211 2212 state_dpaux2_off: pinmux-off { 2213 groups = "dpaux-io"; 2214 function = "off"; 2215 }; 2216 2217 i2c-bus { 2218 #address-cells = <1>; 2219 #size-cells = <0>; 2220 }; 2221 }; 2222 2223 dpaux3: dpaux@155f0000 { 2224 compatible = "nvidia,tegra194-dpaux"; 2225 reg = <0x155f0000 0x10000>; 2226 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2227 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2228 <&bpmp TEGRA194_CLK_PLLDP>; 2229 clock-names = "dpaux", "parent"; 2230 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2231 reset-names = "dpaux"; 2232 status = "disabled"; 2233 2234 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2235 2236 state_dpaux3_aux: pinmux-aux { 2237 groups = "dpaux-io"; 2238 function = "aux"; 2239 }; 2240 2241 state_dpaux3_i2c: pinmux-i2c { 2242 groups = "dpaux-io"; 2243 function = "i2c"; 2244 }; 2245 2246 state_dpaux3_off: pinmux-off { 2247 groups = "dpaux-io"; 2248 function = "off"; 2249 }; 2250 2251 i2c-bus { 2252 #address-cells = <1>; 2253 #size-cells = <0>; 2254 }; 2255 }; 2256 2257 nvenc@15a80000 { 2258 compatible = "nvidia,tegra194-nvenc"; 2259 reg = <0x15a80000 0x00040000>; 2260 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2261 clock-names = "nvenc"; 2262 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2263 reset-names = "nvenc"; 2264 2265 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2266 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2267 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2268 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2269 interconnect-names = "dma-mem", "read-1", "write"; 2270 iommus = <&smmu TEGRA194_SID_NVENC1>; 2271 dma-coherent; 2272 2273 nvidia,host1x-class = <0x22>; 2274 }; 2275 2276 sor0: sor@15b00000 { 2277 compatible = "nvidia,tegra194-sor"; 2278 reg = <0x15b00000 0x40000>; 2279 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2280 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2281 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2282 <&bpmp TEGRA194_CLK_PLLD>, 2283 <&bpmp TEGRA194_CLK_PLLDP>, 2284 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2285 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2286 clock-names = "sor", "out", "parent", "dp", "safe", 2287 "pad"; 2288 resets = <&bpmp TEGRA194_RESET_SOR0>; 2289 reset-names = "sor"; 2290 pinctrl-0 = <&state_dpaux0_aux>; 2291 pinctrl-1 = <&state_dpaux0_i2c>; 2292 pinctrl-2 = <&state_dpaux0_off>; 2293 pinctrl-names = "aux", "i2c", "off"; 2294 status = "disabled"; 2295 2296 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2297 nvidia,interface = <0>; 2298 }; 2299 2300 sor1: sor@15b40000 { 2301 compatible = "nvidia,tegra194-sor"; 2302 reg = <0x15b40000 0x40000>; 2303 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2304 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2305 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2306 <&bpmp TEGRA194_CLK_PLLD2>, 2307 <&bpmp TEGRA194_CLK_PLLDP>, 2308 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2309 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2310 clock-names = "sor", "out", "parent", "dp", "safe", 2311 "pad"; 2312 resets = <&bpmp TEGRA194_RESET_SOR1>; 2313 reset-names = "sor"; 2314 pinctrl-0 = <&state_dpaux1_aux>; 2315 pinctrl-1 = <&state_dpaux1_i2c>; 2316 pinctrl-2 = <&state_dpaux1_off>; 2317 pinctrl-names = "aux", "i2c", "off"; 2318 status = "disabled"; 2319 2320 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2321 nvidia,interface = <1>; 2322 }; 2323 2324 sor2: sor@15b80000 { 2325 compatible = "nvidia,tegra194-sor"; 2326 reg = <0x15b80000 0x40000>; 2327 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2328 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2329 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2330 <&bpmp TEGRA194_CLK_PLLD3>, 2331 <&bpmp TEGRA194_CLK_PLLDP>, 2332 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2333 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2334 clock-names = "sor", "out", "parent", "dp", "safe", 2335 "pad"; 2336 resets = <&bpmp TEGRA194_RESET_SOR2>; 2337 reset-names = "sor"; 2338 pinctrl-0 = <&state_dpaux2_aux>; 2339 pinctrl-1 = <&state_dpaux2_i2c>; 2340 pinctrl-2 = <&state_dpaux2_off>; 2341 pinctrl-names = "aux", "i2c", "off"; 2342 status = "disabled"; 2343 2344 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2345 nvidia,interface = <2>; 2346 }; 2347 2348 sor3: sor@15bc0000 { 2349 compatible = "nvidia,tegra194-sor"; 2350 reg = <0x15bc0000 0x40000>; 2351 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2352 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2353 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2354 <&bpmp TEGRA194_CLK_PLLD4>, 2355 <&bpmp TEGRA194_CLK_PLLDP>, 2356 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2357 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2358 clock-names = "sor", "out", "parent", "dp", "safe", 2359 "pad"; 2360 resets = <&bpmp TEGRA194_RESET_SOR3>; 2361 reset-names = "sor"; 2362 pinctrl-0 = <&state_dpaux3_aux>; 2363 pinctrl-1 = <&state_dpaux3_i2c>; 2364 pinctrl-2 = <&state_dpaux3_off>; 2365 pinctrl-names = "aux", "i2c", "off"; 2366 status = "disabled"; 2367 2368 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2369 nvidia,interface = <3>; 2370 }; 2371 }; 2372 2373 gpu@17000000 { 2374 compatible = "nvidia,gv11b"; 2375 reg = <0x17000000 0x1000000>, 2376 <0x18000000 0x1000000>; 2377 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2378 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2379 interrupt-names = "stall", "nonstall"; 2380 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2381 <&bpmp TEGRA194_CLK_GPU_PWR>, 2382 <&bpmp TEGRA194_CLK_FUSE>; 2383 clock-names = "gpu", "pwr", "fuse"; 2384 resets = <&bpmp TEGRA194_RESET_GPU>; 2385 reset-names = "gpu"; 2386 dma-coherent; 2387 2388 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2389 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2390 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2391 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2392 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2393 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2394 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2395 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2396 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2397 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2398 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2399 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2400 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2401 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2402 "read-1", "read-1-hp", "write-1", 2403 "read-2", "read-2-hp", "write-2", 2404 "read-3", "read-3-hp", "write-3"; 2405 }; 2406 }; 2407 2408 pcie@14100000 { 2409 compatible = "nvidia,tegra194-pcie"; 2410 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2411 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2412 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2413 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2414 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2415 reg-names = "appl", "config", "atu_dma", "dbi"; 2416 2417 status = "disabled"; 2418 2419 #address-cells = <3>; 2420 #size-cells = <2>; 2421 device_type = "pci"; 2422 num-lanes = <1>; 2423 linux,pci-domain = <1>; 2424 2425 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2426 clock-names = "core"; 2427 2428 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2429 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2430 reset-names = "apb", "core"; 2431 2432 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2433 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2434 interrupt-names = "intr", "msi"; 2435 2436 #interrupt-cells = <1>; 2437 interrupt-map-mask = <0 0 0 0>; 2438 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2439 2440 nvidia,bpmp = <&bpmp 1>; 2441 2442 nvidia,aspm-cmrt-us = <60>; 2443 nvidia,aspm-pwr-on-t-us = <20>; 2444 nvidia,aspm-l0s-entrance-latency-us = <3>; 2445 2446 bus-range = <0x0 0xff>; 2447 2448 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2449 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2450 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2451 2452 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2453 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2454 interconnect-names = "dma-mem", "write"; 2455 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2456 iommu-map-mask = <0x0>; 2457 dma-coherent; 2458 }; 2459 2460 pcie@14120000 { 2461 compatible = "nvidia,tegra194-pcie"; 2462 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2463 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2464 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2465 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2466 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2467 reg-names = "appl", "config", "atu_dma", "dbi"; 2468 2469 status = "disabled"; 2470 2471 #address-cells = <3>; 2472 #size-cells = <2>; 2473 device_type = "pci"; 2474 num-lanes = <1>; 2475 linux,pci-domain = <2>; 2476 2477 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2478 clock-names = "core"; 2479 2480 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2481 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2482 reset-names = "apb", "core"; 2483 2484 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2485 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2486 interrupt-names = "intr", "msi"; 2487 2488 #interrupt-cells = <1>; 2489 interrupt-map-mask = <0 0 0 0>; 2490 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2491 2492 nvidia,bpmp = <&bpmp 2>; 2493 2494 nvidia,aspm-cmrt-us = <60>; 2495 nvidia,aspm-pwr-on-t-us = <20>; 2496 nvidia,aspm-l0s-entrance-latency-us = <3>; 2497 2498 bus-range = <0x0 0xff>; 2499 2500 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2501 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2502 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2503 2504 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2505 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2506 interconnect-names = "dma-mem", "write"; 2507 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2508 iommu-map-mask = <0x0>; 2509 dma-coherent; 2510 }; 2511 2512 pcie@14140000 { 2513 compatible = "nvidia,tegra194-pcie"; 2514 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2515 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2516 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2517 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2518 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2519 reg-names = "appl", "config", "atu_dma", "dbi"; 2520 2521 status = "disabled"; 2522 2523 #address-cells = <3>; 2524 #size-cells = <2>; 2525 device_type = "pci"; 2526 num-lanes = <1>; 2527 linux,pci-domain = <3>; 2528 2529 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2530 clock-names = "core"; 2531 2532 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2533 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2534 reset-names = "apb", "core"; 2535 2536 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2537 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2538 interrupt-names = "intr", "msi"; 2539 2540 #interrupt-cells = <1>; 2541 interrupt-map-mask = <0 0 0 0>; 2542 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2543 2544 nvidia,bpmp = <&bpmp 3>; 2545 2546 nvidia,aspm-cmrt-us = <60>; 2547 nvidia,aspm-pwr-on-t-us = <20>; 2548 nvidia,aspm-l0s-entrance-latency-us = <3>; 2549 2550 bus-range = <0x0 0xff>; 2551 2552 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2553 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2554 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2555 2556 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2557 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2558 interconnect-names = "dma-mem", "write"; 2559 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2560 iommu-map-mask = <0x0>; 2561 dma-coherent; 2562 }; 2563 2564 pcie@14160000 { 2565 compatible = "nvidia,tegra194-pcie"; 2566 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2567 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2568 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2569 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2570 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2571 reg-names = "appl", "config", "atu_dma", "dbi"; 2572 2573 status = "disabled"; 2574 2575 #address-cells = <3>; 2576 #size-cells = <2>; 2577 device_type = "pci"; 2578 num-lanes = <4>; 2579 linux,pci-domain = <4>; 2580 2581 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2582 clock-names = "core"; 2583 2584 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2585 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2586 reset-names = "apb", "core"; 2587 2588 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2589 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2590 interrupt-names = "intr", "msi"; 2591 2592 #interrupt-cells = <1>; 2593 interrupt-map-mask = <0 0 0 0>; 2594 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2595 2596 nvidia,bpmp = <&bpmp 4>; 2597 2598 nvidia,aspm-cmrt-us = <60>; 2599 nvidia,aspm-pwr-on-t-us = <20>; 2600 nvidia,aspm-l0s-entrance-latency-us = <3>; 2601 2602 bus-range = <0x0 0xff>; 2603 2604 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2605 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2606 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2607 2608 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2609 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2610 interconnect-names = "dma-mem", "write"; 2611 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2612 iommu-map-mask = <0x0>; 2613 dma-coherent; 2614 }; 2615 2616 pcie@14180000 { 2617 compatible = "nvidia,tegra194-pcie"; 2618 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2619 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2620 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2621 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2622 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2623 reg-names = "appl", "config", "atu_dma", "dbi"; 2624 2625 status = "disabled"; 2626 2627 #address-cells = <3>; 2628 #size-cells = <2>; 2629 device_type = "pci"; 2630 num-lanes = <8>; 2631 linux,pci-domain = <0>; 2632 2633 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2634 clock-names = "core"; 2635 2636 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2637 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2638 reset-names = "apb", "core"; 2639 2640 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2641 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2642 interrupt-names = "intr", "msi"; 2643 2644 #interrupt-cells = <1>; 2645 interrupt-map-mask = <0 0 0 0>; 2646 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2647 2648 nvidia,bpmp = <&bpmp 0>; 2649 2650 nvidia,aspm-cmrt-us = <60>; 2651 nvidia,aspm-pwr-on-t-us = <20>; 2652 nvidia,aspm-l0s-entrance-latency-us = <3>; 2653 2654 bus-range = <0x0 0xff>; 2655 2656 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2657 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2658 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2659 2660 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2661 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2662 interconnect-names = "dma-mem", "write"; 2663 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2664 iommu-map-mask = <0x0>; 2665 dma-coherent; 2666 }; 2667 2668 pcie@141a0000 { 2669 compatible = "nvidia,tegra194-pcie"; 2670 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2671 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2672 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2673 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2674 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2675 reg-names = "appl", "config", "atu_dma", "dbi"; 2676 2677 status = "disabled"; 2678 2679 #address-cells = <3>; 2680 #size-cells = <2>; 2681 device_type = "pci"; 2682 num-lanes = <8>; 2683 linux,pci-domain = <5>; 2684 2685 pinctrl-names = "default"; 2686 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2687 2688 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2689 clock-names = "core"; 2690 2691 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2692 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2693 reset-names = "apb", "core"; 2694 2695 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2696 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2697 interrupt-names = "intr", "msi"; 2698 2699 nvidia,bpmp = <&bpmp 5>; 2700 2701 #interrupt-cells = <1>; 2702 interrupt-map-mask = <0 0 0 0>; 2703 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2704 2705 nvidia,aspm-cmrt-us = <60>; 2706 nvidia,aspm-pwr-on-t-us = <20>; 2707 nvidia,aspm-l0s-entrance-latency-us = <3>; 2708 2709 bus-range = <0x0 0xff>; 2710 2711 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2712 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2713 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2714 2715 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2716 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2717 interconnect-names = "dma-mem", "write"; 2718 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2719 iommu-map-mask = <0x0>; 2720 dma-coherent; 2721 }; 2722 2723 pcie-ep@14160000 { 2724 compatible = "nvidia,tegra194-pcie-ep"; 2725 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2726 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2727 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2728 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2729 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2730 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2731 2732 status = "disabled"; 2733 2734 num-lanes = <4>; 2735 num-ib-windows = <2>; 2736 num-ob-windows = <8>; 2737 2738 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2739 clock-names = "core"; 2740 2741 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2742 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2743 reset-names = "apb", "core"; 2744 2745 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2746 interrupt-names = "intr"; 2747 2748 nvidia,bpmp = <&bpmp 4>; 2749 2750 nvidia,aspm-cmrt-us = <60>; 2751 nvidia,aspm-pwr-on-t-us = <20>; 2752 nvidia,aspm-l0s-entrance-latency-us = <3>; 2753 2754 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2755 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2756 interconnect-names = "dma-mem", "write"; 2757 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2758 iommu-map-mask = <0x0>; 2759 dma-coherent; 2760 }; 2761 2762 pcie-ep@14180000 { 2763 compatible = "nvidia,tegra194-pcie-ep"; 2764 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2765 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2766 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2767 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2768 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2769 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2770 2771 status = "disabled"; 2772 2773 num-lanes = <8>; 2774 num-ib-windows = <2>; 2775 num-ob-windows = <8>; 2776 2777 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2778 clock-names = "core"; 2779 2780 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2781 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2782 reset-names = "apb", "core"; 2783 2784 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2785 interrupt-names = "intr"; 2786 2787 nvidia,bpmp = <&bpmp 0>; 2788 2789 nvidia,aspm-cmrt-us = <60>; 2790 nvidia,aspm-pwr-on-t-us = <20>; 2791 nvidia,aspm-l0s-entrance-latency-us = <3>; 2792 2793 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2794 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2795 interconnect-names = "dma-mem", "write"; 2796 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2797 iommu-map-mask = <0x0>; 2798 dma-coherent; 2799 }; 2800 2801 pcie-ep@141a0000 { 2802 compatible = "nvidia,tegra194-pcie-ep"; 2803 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2804 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2805 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2806 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2807 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2808 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2809 2810 status = "disabled"; 2811 2812 num-lanes = <8>; 2813 num-ib-windows = <2>; 2814 num-ob-windows = <8>; 2815 2816 pinctrl-names = "default"; 2817 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2818 2819 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2820 clock-names = "core"; 2821 2822 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2823 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2824 reset-names = "apb", "core"; 2825 2826 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2827 interrupt-names = "intr"; 2828 2829 nvidia,bpmp = <&bpmp 5>; 2830 2831 nvidia,aspm-cmrt-us = <60>; 2832 nvidia,aspm-pwr-on-t-us = <20>; 2833 nvidia,aspm-l0s-entrance-latency-us = <3>; 2834 2835 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2836 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2837 interconnect-names = "dma-mem", "write"; 2838 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2839 iommu-map-mask = <0x0>; 2840 dma-coherent; 2841 }; 2842 2843 sram@40000000 { 2844 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2845 reg = <0x0 0x40000000 0x0 0x50000>; 2846 #address-cells = <1>; 2847 #size-cells = <1>; 2848 ranges = <0x0 0x0 0x40000000 0x50000>; 2849 no-memory-wc; 2850 2851 cpu_bpmp_tx: sram@4e000 { 2852 reg = <0x4e000 0x1000>; 2853 label = "cpu-bpmp-tx"; 2854 pool; 2855 }; 2856 2857 cpu_bpmp_rx: sram@4f000 { 2858 reg = <0x4f000 0x1000>; 2859 label = "cpu-bpmp-rx"; 2860 pool; 2861 }; 2862 }; 2863 2864 bpmp: bpmp { 2865 compatible = "nvidia,tegra186-bpmp"; 2866 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2867 TEGRA_HSP_DB_MASTER_BPMP>; 2868 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2869 #clock-cells = <1>; 2870 #reset-cells = <1>; 2871 #power-domain-cells = <1>; 2872 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2873 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2874 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2875 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2876 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2877 iommus = <&smmu TEGRA194_SID_BPMP>; 2878 2879 bpmp_i2c: i2c { 2880 compatible = "nvidia,tegra186-bpmp-i2c"; 2881 nvidia,bpmp-bus-id = <5>; 2882 #address-cells = <1>; 2883 #size-cells = <0>; 2884 }; 2885 2886 bpmp_thermal: thermal { 2887 compatible = "nvidia,tegra186-bpmp-thermal"; 2888 #thermal-sensor-cells = <1>; 2889 }; 2890 }; 2891 2892 cpus { 2893 compatible = "nvidia,tegra194-ccplex"; 2894 nvidia,bpmp = <&bpmp>; 2895 #address-cells = <1>; 2896 #size-cells = <0>; 2897 2898 cpu0_0: cpu@0 { 2899 compatible = "nvidia,tegra194-carmel"; 2900 device_type = "cpu"; 2901 reg = <0x000>; 2902 enable-method = "psci"; 2903 i-cache-size = <131072>; 2904 i-cache-line-size = <64>; 2905 i-cache-sets = <512>; 2906 d-cache-size = <65536>; 2907 d-cache-line-size = <64>; 2908 d-cache-sets = <256>; 2909 next-level-cache = <&l2c_0>; 2910 }; 2911 2912 cpu0_1: cpu@1 { 2913 compatible = "nvidia,tegra194-carmel"; 2914 device_type = "cpu"; 2915 reg = <0x001>; 2916 enable-method = "psci"; 2917 i-cache-size = <131072>; 2918 i-cache-line-size = <64>; 2919 i-cache-sets = <512>; 2920 d-cache-size = <65536>; 2921 d-cache-line-size = <64>; 2922 d-cache-sets = <256>; 2923 next-level-cache = <&l2c_0>; 2924 }; 2925 2926 cpu1_0: cpu@100 { 2927 compatible = "nvidia,tegra194-carmel"; 2928 device_type = "cpu"; 2929 reg = <0x100>; 2930 enable-method = "psci"; 2931 i-cache-size = <131072>; 2932 i-cache-line-size = <64>; 2933 i-cache-sets = <512>; 2934 d-cache-size = <65536>; 2935 d-cache-line-size = <64>; 2936 d-cache-sets = <256>; 2937 next-level-cache = <&l2c_1>; 2938 }; 2939 2940 cpu1_1: cpu@101 { 2941 compatible = "nvidia,tegra194-carmel"; 2942 device_type = "cpu"; 2943 reg = <0x101>; 2944 enable-method = "psci"; 2945 i-cache-size = <131072>; 2946 i-cache-line-size = <64>; 2947 i-cache-sets = <512>; 2948 d-cache-size = <65536>; 2949 d-cache-line-size = <64>; 2950 d-cache-sets = <256>; 2951 next-level-cache = <&l2c_1>; 2952 }; 2953 2954 cpu2_0: cpu@200 { 2955 compatible = "nvidia,tegra194-carmel"; 2956 device_type = "cpu"; 2957 reg = <0x200>; 2958 enable-method = "psci"; 2959 i-cache-size = <131072>; 2960 i-cache-line-size = <64>; 2961 i-cache-sets = <512>; 2962 d-cache-size = <65536>; 2963 d-cache-line-size = <64>; 2964 d-cache-sets = <256>; 2965 next-level-cache = <&l2c_2>; 2966 }; 2967 2968 cpu2_1: cpu@201 { 2969 compatible = "nvidia,tegra194-carmel"; 2970 device_type = "cpu"; 2971 reg = <0x201>; 2972 enable-method = "psci"; 2973 i-cache-size = <131072>; 2974 i-cache-line-size = <64>; 2975 i-cache-sets = <512>; 2976 d-cache-size = <65536>; 2977 d-cache-line-size = <64>; 2978 d-cache-sets = <256>; 2979 next-level-cache = <&l2c_2>; 2980 }; 2981 2982 cpu3_0: cpu@300 { 2983 compatible = "nvidia,tegra194-carmel"; 2984 device_type = "cpu"; 2985 reg = <0x300>; 2986 enable-method = "psci"; 2987 i-cache-size = <131072>; 2988 i-cache-line-size = <64>; 2989 i-cache-sets = <512>; 2990 d-cache-size = <65536>; 2991 d-cache-line-size = <64>; 2992 d-cache-sets = <256>; 2993 next-level-cache = <&l2c_3>; 2994 }; 2995 2996 cpu3_1: cpu@301 { 2997 compatible = "nvidia,tegra194-carmel"; 2998 device_type = "cpu"; 2999 reg = <0x301>; 3000 enable-method = "psci"; 3001 i-cache-size = <131072>; 3002 i-cache-line-size = <64>; 3003 i-cache-sets = <512>; 3004 d-cache-size = <65536>; 3005 d-cache-line-size = <64>; 3006 d-cache-sets = <256>; 3007 next-level-cache = <&l2c_3>; 3008 }; 3009 3010 cpu-map { 3011 cluster0 { 3012 core0 { 3013 cpu = <&cpu0_0>; 3014 }; 3015 3016 core1 { 3017 cpu = <&cpu0_1>; 3018 }; 3019 }; 3020 3021 cluster1 { 3022 core0 { 3023 cpu = <&cpu1_0>; 3024 }; 3025 3026 core1 { 3027 cpu = <&cpu1_1>; 3028 }; 3029 }; 3030 3031 cluster2 { 3032 core0 { 3033 cpu = <&cpu2_0>; 3034 }; 3035 3036 core1 { 3037 cpu = <&cpu2_1>; 3038 }; 3039 }; 3040 3041 cluster3 { 3042 core0 { 3043 cpu = <&cpu3_0>; 3044 }; 3045 3046 core1 { 3047 cpu = <&cpu3_1>; 3048 }; 3049 }; 3050 }; 3051 3052 l2c_0: l2-cache0 { 3053 compatible = "cache"; 3054 cache-unified; 3055 cache-size = <2097152>; 3056 cache-line-size = <64>; 3057 cache-sets = <2048>; 3058 cache-level = <2>; 3059 next-level-cache = <&l3c>; 3060 }; 3061 3062 l2c_1: l2-cache1 { 3063 compatible = "cache"; 3064 cache-unified; 3065 cache-size = <2097152>; 3066 cache-line-size = <64>; 3067 cache-sets = <2048>; 3068 cache-level = <2>; 3069 next-level-cache = <&l3c>; 3070 }; 3071 3072 l2c_2: l2-cache2 { 3073 compatible = "cache"; 3074 cache-unified; 3075 cache-size = <2097152>; 3076 cache-line-size = <64>; 3077 cache-sets = <2048>; 3078 cache-level = <2>; 3079 next-level-cache = <&l3c>; 3080 }; 3081 3082 l2c_3: l2-cache3 { 3083 compatible = "cache"; 3084 cache-unified; 3085 cache-size = <2097152>; 3086 cache-line-size = <64>; 3087 cache-sets = <2048>; 3088 cache-level = <2>; 3089 next-level-cache = <&l3c>; 3090 }; 3091 3092 l3c: l3-cache { 3093 compatible = "cache"; 3094 cache-unified; 3095 cache-size = <4194304>; 3096 cache-line-size = <64>; 3097 cache-level = <3>; 3098 cache-sets = <4096>; 3099 }; 3100 }; 3101 3102 pmu { 3103 compatible = "nvidia,carmel-pmu"; 3104 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 3112 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 3113 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 3114 }; 3115 3116 psci { 3117 compatible = "arm,psci-1.0"; 3118 status = "okay"; 3119 method = "smc"; 3120 }; 3121 3122 sound { 3123 status = "disabled"; 3124 3125 clocks = <&bpmp TEGRA194_CLK_PLLA>, 3126 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3127 clock-names = "pll_a", "plla_out0"; 3128 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 3129 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 3130 <&bpmp TEGRA194_CLK_AUD_MCLK>; 3131 assigned-clock-parents = <0>, 3132 <&bpmp TEGRA194_CLK_PLLA>, 3133 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3134 /* 3135 * PLLA supports dynamic ramp. Below initial rate is chosen 3136 * for this to work and oscillate between base rates required 3137 * for 8x and 11.025x sample rate streams. 3138 */ 3139 assigned-clock-rates = <258000000>; 3140 }; 3141 3142 tcu: serial { 3143 compatible = "nvidia,tegra194-tcu"; 3144 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3145 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3146 mbox-names = "rx", "tx"; 3147 }; 3148 3149 thermal-zones { 3150 cpu-thermal { 3151 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3152 status = "disabled"; 3153 }; 3154 3155 gpu-thermal { 3156 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3157 status = "disabled"; 3158 }; 3159 3160 aux-thermal { 3161 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3162 status = "disabled"; 3163 }; 3164 3165 pllx-thermal { 3166 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3167 status = "disabled"; 3168 }; 3169 3170 ao-thermal { 3171 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3172 status = "disabled"; 3173 }; 3174 3175 tj-thermal { 3176 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3177 status = "disabled"; 3178 }; 3179 }; 3180 3181 timer { 3182 compatible = "arm,armv8-timer"; 3183 interrupts = <GIC_PPI 13 3184 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3185 <GIC_PPI 14 3186 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3187 <GIC_PPI 11 3188 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3189 <GIC_PPI 10 3190 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3191 interrupt-parent = <&gic>; 3192 always-on; 3193 }; 3194}; 3195