1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; 26 27 apbmisc: misc@100000 { 28 compatible = "nvidia,tegra194-misc"; 29 reg = <0x0 0x00100000 0x0 0xf000>, 30 <0x0 0x0010f000 0x0 0x1000>; 31 }; 32 33 gpio: gpio@2200000 { 34 compatible = "nvidia,tegra194-gpio"; 35 reg-names = "security", "gpio"; 36 reg = <0x0 0x2200000 0x0 0x10000>, 37 <0x0 0x2210000 0x0 0x10000>; 38 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 86 #interrupt-cells = <2>; 87 interrupt-controller; 88 #gpio-cells = <2>; 89 gpio-controller; 90 gpio-ranges = <&pinmux 0 0 169>; 91 }; 92 93 cbb-noc@2300000 { 94 compatible = "nvidia,tegra194-cbb-noc"; 95 reg = <0x0 0x02300000 0x0 0x1000>; 96 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 98 nvidia,axi2apb = <&axi2apb>; 99 nvidia,apbmisc = <&apbmisc>; 100 status = "okay"; 101 }; 102 103 axi2apb: axi2apb@2390000 { 104 compatible = "nvidia,tegra194-axi2apb"; 105 reg = <0x0 0x2390000 0x0 0x1000>, 106 <0x0 0x23a0000 0x0 0x1000>, 107 <0x0 0x23b0000 0x0 0x1000>, 108 <0x0 0x23c0000 0x0 0x1000>, 109 <0x0 0x23d0000 0x0 0x1000>, 110 <0x0 0x23e0000 0x0 0x1000>; 111 status = "okay"; 112 }; 113 114 pinmux: pinmux@2430000 { 115 compatible = "nvidia,tegra194-pinmux"; 116 reg = <0x0 0x2430000 0x0 0x17000>; 117 status = "okay"; 118 119 pex_clkreq_c5_bi_dir_state: pinmux-pex-clkreq-c5-bi-dir { 120 clkreq { 121 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 122 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 123 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 124 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 125 nvidia,tristate = <TEGRA_PIN_DISABLE>; 126 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 127 }; 128 }; 129 130 pex_rst_c5_out_state: pinmux-pex-rst-c5-out { 131 pex_rst { 132 nvidia,pins = "pex_l5_rst_n_pgg1"; 133 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 134 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 135 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 136 nvidia,tristate = <TEGRA_PIN_DISABLE>; 137 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 138 }; 139 }; 140 }; 141 142 ethernet@2490000 { 143 compatible = "nvidia,tegra194-eqos", 144 "nvidia,tegra186-eqos", 145 "snps,dwc-qos-ethernet-4.10"; 146 reg = <0x0 0x02490000 0x0 0x10000>; 147 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 149 <&bpmp TEGRA194_CLK_EQOS_AXI>, 150 <&bpmp TEGRA194_CLK_EQOS_RX>, 151 <&bpmp TEGRA194_CLK_EQOS_TX>, 152 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 153 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 154 resets = <&bpmp TEGRA194_RESET_EQOS>; 155 reset-names = "eqos"; 156 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 157 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 158 interconnect-names = "dma-mem", "write"; 159 iommus = <&smmu TEGRA194_SID_EQOS>; 160 status = "disabled"; 161 162 snps,write-requests = <1>; 163 snps,read-requests = <3>; 164 snps,burst-map = <0x7>; 165 snps,txpbl = <16>; 166 snps,rxpbl = <8>; 167 }; 168 169 gpcdma: dma-controller@2600000 { 170 compatible = "nvidia,tegra194-gpcdma", 171 "nvidia,tegra186-gpcdma"; 172 reg = <0x0 0x2600000 0x0 0x210000>; 173 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 174 reset-names = "gpcdma"; 175 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 207 #dma-cells = <1>; 208 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 209 dma-coherent; 210 dma-channel-mask = <0xfffffffe>; 211 status = "okay"; 212 }; 213 214 aconnect@2900000 { 215 compatible = "nvidia,tegra194-aconnect", 216 "nvidia,tegra210-aconnect"; 217 clocks = <&bpmp TEGRA194_CLK_APE>, 218 <&bpmp TEGRA194_CLK_APB2APE>; 219 clock-names = "ape", "apb2ape"; 220 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 221 status = "disabled"; 222 223 #address-cells = <2>; 224 #size-cells = <2>; 225 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 226 227 tegra_ahub: ahub@2900800 { 228 compatible = "nvidia,tegra194-ahub", 229 "nvidia,tegra186-ahub"; 230 reg = <0x0 0x02900800 0x0 0x800>; 231 clocks = <&bpmp TEGRA194_CLK_AHUB>; 232 clock-names = "ahub"; 233 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 234 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 235 status = "disabled"; 236 237 #address-cells = <2>; 238 #size-cells = <2>; 239 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 240 241 tegra_i2s1: i2s@2901000 { 242 compatible = "nvidia,tegra194-i2s", 243 "nvidia,tegra210-i2s"; 244 reg = <0x0 0x2901000 0x0 0x100>; 245 clocks = <&bpmp TEGRA194_CLK_I2S1>, 246 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 247 clock-names = "i2s", "sync_input"; 248 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 249 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 250 assigned-clock-rates = <1536000>; 251 sound-name-prefix = "I2S1"; 252 status = "disabled"; 253 }; 254 255 tegra_i2s2: i2s@2901100 { 256 compatible = "nvidia,tegra194-i2s", 257 "nvidia,tegra210-i2s"; 258 reg = <0x0 0x2901100 0x0 0x100>; 259 clocks = <&bpmp TEGRA194_CLK_I2S2>, 260 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 261 clock-names = "i2s", "sync_input"; 262 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 263 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 264 assigned-clock-rates = <1536000>; 265 sound-name-prefix = "I2S2"; 266 status = "disabled"; 267 }; 268 269 tegra_i2s3: i2s@2901200 { 270 compatible = "nvidia,tegra194-i2s", 271 "nvidia,tegra210-i2s"; 272 reg = <0x0 0x2901200 0x0 0x100>; 273 clocks = <&bpmp TEGRA194_CLK_I2S3>, 274 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 275 clock-names = "i2s", "sync_input"; 276 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 277 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 278 assigned-clock-rates = <1536000>; 279 sound-name-prefix = "I2S3"; 280 status = "disabled"; 281 }; 282 283 tegra_i2s4: i2s@2901300 { 284 compatible = "nvidia,tegra194-i2s", 285 "nvidia,tegra210-i2s"; 286 reg = <0x0 0x2901300 0x0 0x100>; 287 clocks = <&bpmp TEGRA194_CLK_I2S4>, 288 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 289 clock-names = "i2s", "sync_input"; 290 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 291 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 292 assigned-clock-rates = <1536000>; 293 sound-name-prefix = "I2S4"; 294 status = "disabled"; 295 }; 296 297 tegra_i2s5: i2s@2901400 { 298 compatible = "nvidia,tegra194-i2s", 299 "nvidia,tegra210-i2s"; 300 reg = <0x0 0x2901400 0x0 0x100>; 301 clocks = <&bpmp TEGRA194_CLK_I2S5>, 302 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 303 clock-names = "i2s", "sync_input"; 304 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 305 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 306 assigned-clock-rates = <1536000>; 307 sound-name-prefix = "I2S5"; 308 status = "disabled"; 309 }; 310 311 tegra_i2s6: i2s@2901500 { 312 compatible = "nvidia,tegra194-i2s", 313 "nvidia,tegra210-i2s"; 314 reg = <0x0 0x2901500 0x0 0x100>; 315 clocks = <&bpmp TEGRA194_CLK_I2S6>, 316 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 317 clock-names = "i2s", "sync_input"; 318 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 319 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 320 assigned-clock-rates = <1536000>; 321 sound-name-prefix = "I2S6"; 322 status = "disabled"; 323 }; 324 325 tegra_sfc1: sfc@2902000 { 326 compatible = "nvidia,tegra194-sfc", 327 "nvidia,tegra210-sfc"; 328 reg = <0x0 0x2902000 0x0 0x200>; 329 sound-name-prefix = "SFC1"; 330 status = "disabled"; 331 }; 332 333 tegra_sfc2: sfc@2902200 { 334 compatible = "nvidia,tegra194-sfc", 335 "nvidia,tegra210-sfc"; 336 reg = <0x0 0x2902200 0x0 0x200>; 337 sound-name-prefix = "SFC2"; 338 status = "disabled"; 339 }; 340 341 tegra_sfc3: sfc@2902400 { 342 compatible = "nvidia,tegra194-sfc", 343 "nvidia,tegra210-sfc"; 344 reg = <0x0 0x2902400 0x0 0x200>; 345 sound-name-prefix = "SFC3"; 346 status = "disabled"; 347 }; 348 349 tegra_sfc4: sfc@2902600 { 350 compatible = "nvidia,tegra194-sfc", 351 "nvidia,tegra210-sfc"; 352 reg = <0x0 0x2902600 0x0 0x200>; 353 sound-name-prefix = "SFC4"; 354 status = "disabled"; 355 }; 356 357 tegra_amx1: amx@2903000 { 358 compatible = "nvidia,tegra194-amx"; 359 reg = <0x0 0x2903000 0x0 0x100>; 360 sound-name-prefix = "AMX1"; 361 status = "disabled"; 362 }; 363 364 tegra_amx2: amx@2903100 { 365 compatible = "nvidia,tegra194-amx"; 366 reg = <0x0 0x2903100 0x0 0x100>; 367 sound-name-prefix = "AMX2"; 368 status = "disabled"; 369 }; 370 371 tegra_amx3: amx@2903200 { 372 compatible = "nvidia,tegra194-amx"; 373 reg = <0x0 0x2903200 0x0 0x100>; 374 sound-name-prefix = "AMX3"; 375 status = "disabled"; 376 }; 377 378 tegra_amx4: amx@2903300 { 379 compatible = "nvidia,tegra194-amx"; 380 reg = <0x0 0x2903300 0x0 0x100>; 381 sound-name-prefix = "AMX4"; 382 status = "disabled"; 383 }; 384 385 tegra_adx1: adx@2903800 { 386 compatible = "nvidia,tegra194-adx", 387 "nvidia,tegra210-adx"; 388 reg = <0x0 0x2903800 0x0 0x100>; 389 sound-name-prefix = "ADX1"; 390 status = "disabled"; 391 }; 392 393 tegra_adx2: adx@2903900 { 394 compatible = "nvidia,tegra194-adx", 395 "nvidia,tegra210-adx"; 396 reg = <0x0 0x2903900 0x0 0x100>; 397 sound-name-prefix = "ADX2"; 398 status = "disabled"; 399 }; 400 401 tegra_adx3: adx@2903a00 { 402 compatible = "nvidia,tegra194-adx", 403 "nvidia,tegra210-adx"; 404 reg = <0x0 0x2903a00 0x0 0x100>; 405 sound-name-prefix = "ADX3"; 406 status = "disabled"; 407 }; 408 409 tegra_adx4: adx@2903b00 { 410 compatible = "nvidia,tegra194-adx", 411 "nvidia,tegra210-adx"; 412 reg = <0x0 0x2903b00 0x0 0x100>; 413 sound-name-prefix = "ADX4"; 414 status = "disabled"; 415 }; 416 417 tegra_dmic1: dmic@2904000 { 418 compatible = "nvidia,tegra194-dmic", 419 "nvidia,tegra210-dmic"; 420 reg = <0x0 0x2904000 0x0 0x100>; 421 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 422 clock-names = "dmic"; 423 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 424 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 425 assigned-clock-rates = <3072000>; 426 sound-name-prefix = "DMIC1"; 427 status = "disabled"; 428 }; 429 430 tegra_dmic2: dmic@2904100 { 431 compatible = "nvidia,tegra194-dmic", 432 "nvidia,tegra210-dmic"; 433 reg = <0x0 0x2904100 0x0 0x100>; 434 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 435 clock-names = "dmic"; 436 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 437 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 438 assigned-clock-rates = <3072000>; 439 sound-name-prefix = "DMIC2"; 440 status = "disabled"; 441 }; 442 443 tegra_dmic3: dmic@2904200 { 444 compatible = "nvidia,tegra194-dmic", 445 "nvidia,tegra210-dmic"; 446 reg = <0x0 0x2904200 0x0 0x100>; 447 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 448 clock-names = "dmic"; 449 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 450 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 451 assigned-clock-rates = <3072000>; 452 sound-name-prefix = "DMIC3"; 453 status = "disabled"; 454 }; 455 456 tegra_dmic4: dmic@2904300 { 457 compatible = "nvidia,tegra194-dmic", 458 "nvidia,tegra210-dmic"; 459 reg = <0x0 0x2904300 0x0 0x100>; 460 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 461 clock-names = "dmic"; 462 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 463 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 464 assigned-clock-rates = <3072000>; 465 sound-name-prefix = "DMIC4"; 466 status = "disabled"; 467 }; 468 469 tegra_dspk1: dspk@2905000 { 470 compatible = "nvidia,tegra194-dspk", 471 "nvidia,tegra186-dspk"; 472 reg = <0x0 0x2905000 0x0 0x100>; 473 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 474 clock-names = "dspk"; 475 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 476 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 477 assigned-clock-rates = <12288000>; 478 sound-name-prefix = "DSPK1"; 479 status = "disabled"; 480 }; 481 482 tegra_dspk2: dspk@2905100 { 483 compatible = "nvidia,tegra194-dspk", 484 "nvidia,tegra186-dspk"; 485 reg = <0x0 0x2905100 0x0 0x100>; 486 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 487 clock-names = "dspk"; 488 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 489 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 490 assigned-clock-rates = <12288000>; 491 sound-name-prefix = "DSPK2"; 492 status = "disabled"; 493 }; 494 495 tegra_ope1: processing-engine@2908000 { 496 compatible = "nvidia,tegra194-ope", 497 "nvidia,tegra210-ope"; 498 reg = <0x0 0x2908000 0x0 0x100>; 499 sound-name-prefix = "OPE1"; 500 status = "disabled"; 501 502 #address-cells = <2>; 503 #size-cells = <2>; 504 ranges; 505 506 equalizer@2908100 { 507 compatible = "nvidia,tegra194-peq", 508 "nvidia,tegra210-peq"; 509 reg = <0x0 0x2908100 0x0 0x100>; 510 }; 511 512 dynamic-range-compressor@2908200 { 513 compatible = "nvidia,tegra194-mbdrc", 514 "nvidia,tegra210-mbdrc"; 515 reg = <0x0 0x2908200 0x0 0x200>; 516 }; 517 }; 518 519 tegra_mvc1: mvc@290a000 { 520 compatible = "nvidia,tegra194-mvc", 521 "nvidia,tegra210-mvc"; 522 reg = <0x0 0x290a000 0x0 0x200>; 523 sound-name-prefix = "MVC1"; 524 status = "disabled"; 525 }; 526 527 tegra_mvc2: mvc@290a200 { 528 compatible = "nvidia,tegra194-mvc", 529 "nvidia,tegra210-mvc"; 530 reg = <0x0 0x290a200 0x0 0x200>; 531 sound-name-prefix = "MVC2"; 532 status = "disabled"; 533 }; 534 535 tegra_amixer: amixer@290bb00 { 536 compatible = "nvidia,tegra194-amixer", 537 "nvidia,tegra210-amixer"; 538 reg = <0x0 0x290bb00 0x0 0x800>; 539 sound-name-prefix = "MIXER1"; 540 status = "disabled"; 541 }; 542 543 tegra_admaif: admaif@290f000 { 544 compatible = "nvidia,tegra194-admaif", 545 "nvidia,tegra186-admaif"; 546 reg = <0x0 0x0290f000 0x0 0x1000>; 547 dmas = <&adma 1>, <&adma 1>, 548 <&adma 2>, <&adma 2>, 549 <&adma 3>, <&adma 3>, 550 <&adma 4>, <&adma 4>, 551 <&adma 5>, <&adma 5>, 552 <&adma 6>, <&adma 6>, 553 <&adma 7>, <&adma 7>, 554 <&adma 8>, <&adma 8>, 555 <&adma 9>, <&adma 9>, 556 <&adma 10>, <&adma 10>, 557 <&adma 11>, <&adma 11>, 558 <&adma 12>, <&adma 12>, 559 <&adma 13>, <&adma 13>, 560 <&adma 14>, <&adma 14>, 561 <&adma 15>, <&adma 15>, 562 <&adma 16>, <&adma 16>, 563 <&adma 17>, <&adma 17>, 564 <&adma 18>, <&adma 18>, 565 <&adma 19>, <&adma 19>, 566 <&adma 20>, <&adma 20>; 567 dma-names = "rx1", "tx1", 568 "rx2", "tx2", 569 "rx3", "tx3", 570 "rx4", "tx4", 571 "rx5", "tx5", 572 "rx6", "tx6", 573 "rx7", "tx7", 574 "rx8", "tx8", 575 "rx9", "tx9", 576 "rx10", "tx10", 577 "rx11", "tx11", 578 "rx12", "tx12", 579 "rx13", "tx13", 580 "rx14", "tx14", 581 "rx15", "tx15", 582 "rx16", "tx16", 583 "rx17", "tx17", 584 "rx18", "tx18", 585 "rx19", "tx19", 586 "rx20", "tx20"; 587 status = "disabled"; 588 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 589 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 590 interconnect-names = "dma-mem", "write"; 591 iommus = <&smmu TEGRA194_SID_APE>; 592 }; 593 594 tegra_asrc: asrc@2910000 { 595 compatible = "nvidia,tegra194-asrc", 596 "nvidia,tegra186-asrc"; 597 reg = <0x0 0x2910000 0x0 0x2000>; 598 sound-name-prefix = "ASRC1"; 599 status = "disabled"; 600 }; 601 }; 602 603 adma: dma-controller@2930000 { 604 compatible = "nvidia,tegra194-adma", 605 "nvidia,tegra186-adma"; 606 reg = <0x0 0x02930000 0x0 0x20000>; 607 interrupt-parent = <&agic>; 608 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 640 #dma-cells = <1>; 641 clocks = <&bpmp TEGRA194_CLK_AHUB>; 642 clock-names = "d_audio"; 643 status = "disabled"; 644 }; 645 646 agic: interrupt-controller@2a40000 { 647 compatible = "nvidia,tegra194-agic", 648 "nvidia,tegra210-agic"; 649 #interrupt-cells = <3>; 650 interrupt-controller; 651 reg = <0x0 0x02a41000 0x0 0x1000>, 652 <0x0 0x02a42000 0x0 0x2000>; 653 interrupts = <GIC_SPI 145 654 (GIC_CPU_MASK_SIMPLE(4) | 655 IRQ_TYPE_LEVEL_HIGH)>; 656 clocks = <&bpmp TEGRA194_CLK_APE>; 657 clock-names = "clk"; 658 status = "disabled"; 659 }; 660 }; 661 662 mc: memory-controller@2c00000 { 663 compatible = "nvidia,tegra194-mc"; 664 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 665 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 666 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 667 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 668 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 669 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 670 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 671 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 672 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 673 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 674 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 675 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 676 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 677 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 678 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 679 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 680 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 681 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 682 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 683 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 684 "ch11", "ch12", "ch13", "ch14", "ch15"; 685 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 686 #interconnect-cells = <1>; 687 status = "disabled"; 688 689 #address-cells = <2>; 690 #size-cells = <2>; 691 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 692 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 693 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 694 695 /* 696 * Bit 39 of addresses passing through the memory 697 * controller selects the XBAR format used when memory 698 * is accessed. This is used to transparently access 699 * memory in the XBAR format used by the discrete GPU 700 * (bit 39 set) or Tegra (bit 39 clear). 701 * 702 * As a consequence, the operating system must ensure 703 * that bit 39 is never used implicitly, for example 704 * via an I/O virtual address mapping of an IOMMU. If 705 * devices require access to the XBAR switch, their 706 * drivers must set this bit explicitly. 707 * 708 * Limit the DMA range for memory clients to [38:0]. 709 */ 710 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 711 712 emc: external-memory-controller@2c60000 { 713 compatible = "nvidia,tegra194-emc"; 714 reg = <0x0 0x02c60000 0x0 0x90000>, 715 <0x0 0x01780000 0x0 0x80000>; 716 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&bpmp TEGRA194_CLK_EMC>; 718 clock-names = "emc"; 719 720 #interconnect-cells = <0>; 721 722 nvidia,bpmp = <&bpmp>; 723 }; 724 }; 725 726 timer@3010000 { 727 compatible = "nvidia,tegra186-timer"; 728 reg = <0x0 0x03010000 0x0 0x000e0000>; 729 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 739 status = "okay"; 740 }; 741 742 uarta: serial@3100000 { 743 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 744 reg = <0x0 0x03100000 0x0 0x40>; 745 reg-shift = <2>; 746 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&bpmp TEGRA194_CLK_UARTA>; 748 clock-names = "serial"; 749 resets = <&bpmp TEGRA194_RESET_UARTA>; 750 reset-names = "serial"; 751 status = "disabled"; 752 }; 753 754 uartb: serial@3110000 { 755 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 756 reg = <0x0 0x03110000 0x0 0x40>; 757 reg-shift = <2>; 758 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&bpmp TEGRA194_CLK_UARTB>; 760 clock-names = "serial"; 761 resets = <&bpmp TEGRA194_RESET_UARTB>; 762 reset-names = "serial"; 763 status = "disabled"; 764 }; 765 766 uartd: serial@3130000 { 767 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 768 reg = <0x0 0x03130000 0x0 0x40>; 769 reg-shift = <2>; 770 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&bpmp TEGRA194_CLK_UARTD>; 772 clock-names = "serial"; 773 resets = <&bpmp TEGRA194_RESET_UARTD>; 774 reset-names = "serial"; 775 status = "disabled"; 776 }; 777 778 uarte: serial@3140000 { 779 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 780 reg = <0x0 0x03140000 0x0 0x40>; 781 reg-shift = <2>; 782 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&bpmp TEGRA194_CLK_UARTE>; 784 clock-names = "serial"; 785 resets = <&bpmp TEGRA194_RESET_UARTE>; 786 reset-names = "serial"; 787 status = "disabled"; 788 }; 789 790 uartf: serial@3150000 { 791 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 792 reg = <0x0 0x03150000 0x0 0x40>; 793 reg-shift = <2>; 794 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&bpmp TEGRA194_CLK_UARTF>; 796 clock-names = "serial"; 797 resets = <&bpmp TEGRA194_RESET_UARTF>; 798 reset-names = "serial"; 799 status = "disabled"; 800 }; 801 802 gen1_i2c: i2c@3160000 { 803 compatible = "nvidia,tegra194-i2c"; 804 reg = <0x0 0x03160000 0x0 0x10000>; 805 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 clocks = <&bpmp TEGRA194_CLK_I2C1>; 809 clock-names = "div-clk"; 810 resets = <&bpmp TEGRA194_RESET_I2C1>; 811 reset-names = "i2c"; 812 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 813 dma-coherent; 814 dmas = <&gpcdma 21>, <&gpcdma 21>; 815 dma-names = "rx", "tx"; 816 status = "disabled"; 817 }; 818 819 uarth: serial@3170000 { 820 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 821 reg = <0x0 0x03170000 0x0 0x40>; 822 reg-shift = <2>; 823 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&bpmp TEGRA194_CLK_UARTH>; 825 clock-names = "serial"; 826 resets = <&bpmp TEGRA194_RESET_UARTH>; 827 reset-names = "serial"; 828 status = "disabled"; 829 }; 830 831 cam_i2c: i2c@3180000 { 832 compatible = "nvidia,tegra194-i2c"; 833 reg = <0x0 0x03180000 0x0 0x10000>; 834 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 clocks = <&bpmp TEGRA194_CLK_I2C3>; 838 clock-names = "div-clk"; 839 resets = <&bpmp TEGRA194_RESET_I2C3>; 840 reset-names = "i2c"; 841 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 842 dma-coherent; 843 dmas = <&gpcdma 23>, <&gpcdma 23>; 844 dma-names = "rx", "tx"; 845 status = "disabled"; 846 }; 847 848 /* shares pads with dpaux1 */ 849 dp_aux_ch1_i2c: i2c@3190000 { 850 compatible = "nvidia,tegra194-i2c"; 851 reg = <0x0 0x03190000 0x0 0x10000>; 852 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 clocks = <&bpmp TEGRA194_CLK_I2C4>; 856 clock-names = "div-clk"; 857 resets = <&bpmp TEGRA194_RESET_I2C4>; 858 reset-names = "i2c"; 859 pinctrl-0 = <&state_dpaux1_i2c>; 860 pinctrl-1 = <&state_dpaux1_off>; 861 pinctrl-names = "default", "idle"; 862 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 863 dma-coherent; 864 dmas = <&gpcdma 26>, <&gpcdma 26>; 865 dma-names = "rx", "tx"; 866 status = "disabled"; 867 }; 868 869 /* shares pads with dpaux0 */ 870 dp_aux_ch0_i2c: i2c@31b0000 { 871 compatible = "nvidia,tegra194-i2c"; 872 reg = <0x0 0x031b0000 0x0 0x10000>; 873 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 clocks = <&bpmp TEGRA194_CLK_I2C6>; 877 clock-names = "div-clk"; 878 resets = <&bpmp TEGRA194_RESET_I2C6>; 879 reset-names = "i2c"; 880 pinctrl-0 = <&state_dpaux0_i2c>; 881 pinctrl-1 = <&state_dpaux0_off>; 882 pinctrl-names = "default", "idle"; 883 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 884 dma-coherent; 885 dmas = <&gpcdma 30>, <&gpcdma 30>; 886 dma-names = "rx", "tx"; 887 status = "disabled"; 888 }; 889 890 /* shares pads with dpaux2 */ 891 dp_aux_ch2_i2c: i2c@31c0000 { 892 compatible = "nvidia,tegra194-i2c"; 893 reg = <0x0 0x031c0000 0x0 0x10000>; 894 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 clocks = <&bpmp TEGRA194_CLK_I2C7>; 898 clock-names = "div-clk"; 899 resets = <&bpmp TEGRA194_RESET_I2C7>; 900 reset-names = "i2c"; 901 pinctrl-0 = <&state_dpaux2_i2c>; 902 pinctrl-1 = <&state_dpaux2_off>; 903 pinctrl-names = "default", "idle"; 904 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 905 dma-coherent; 906 dmas = <&gpcdma 27>, <&gpcdma 27>; 907 dma-names = "rx", "tx"; 908 status = "disabled"; 909 }; 910 911 /* shares pads with dpaux3 */ 912 dp_aux_ch3_i2c: i2c@31e0000 { 913 compatible = "nvidia,tegra194-i2c"; 914 reg = <0x0 0x031e0000 0x0 0x10000>; 915 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 clocks = <&bpmp TEGRA194_CLK_I2C9>; 919 clock-names = "div-clk"; 920 resets = <&bpmp TEGRA194_RESET_I2C9>; 921 reset-names = "i2c"; 922 pinctrl-0 = <&state_dpaux3_i2c>; 923 pinctrl-1 = <&state_dpaux3_off>; 924 pinctrl-names = "default", "idle"; 925 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 926 dma-coherent; 927 dmas = <&gpcdma 31>, <&gpcdma 31>; 928 dma-names = "rx", "tx"; 929 status = "disabled"; 930 }; 931 932 spi@3270000 { 933 compatible = "nvidia,tegra194-qspi"; 934 reg = <0x0 0x3270000 0x0 0x1000>; 935 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 939 <&bpmp TEGRA194_CLK_QSPI0_PM>; 940 clock-names = "qspi", "qspi_out"; 941 resets = <&bpmp TEGRA194_RESET_QSPI0>; 942 status = "disabled"; 943 }; 944 945 pwm1: pwm@3280000 { 946 compatible = "nvidia,tegra194-pwm", 947 "nvidia,tegra186-pwm"; 948 reg = <0x0 0x3280000 0x0 0x10000>; 949 clocks = <&bpmp TEGRA194_CLK_PWM1>; 950 resets = <&bpmp TEGRA194_RESET_PWM1>; 951 reset-names = "pwm"; 952 status = "disabled"; 953 #pwm-cells = <2>; 954 }; 955 956 pwm2: pwm@3290000 { 957 compatible = "nvidia,tegra194-pwm", 958 "nvidia,tegra186-pwm"; 959 reg = <0x0 0x3290000 0x0 0x10000>; 960 clocks = <&bpmp TEGRA194_CLK_PWM2>; 961 resets = <&bpmp TEGRA194_RESET_PWM2>; 962 reset-names = "pwm"; 963 status = "disabled"; 964 #pwm-cells = <2>; 965 }; 966 967 pwm3: pwm@32a0000 { 968 compatible = "nvidia,tegra194-pwm", 969 "nvidia,tegra186-pwm"; 970 reg = <0x0 0x32a0000 0x0 0x10000>; 971 clocks = <&bpmp TEGRA194_CLK_PWM3>; 972 resets = <&bpmp TEGRA194_RESET_PWM3>; 973 reset-names = "pwm"; 974 status = "disabled"; 975 #pwm-cells = <2>; 976 }; 977 978 pwm5: pwm@32c0000 { 979 compatible = "nvidia,tegra194-pwm", 980 "nvidia,tegra186-pwm"; 981 reg = <0x0 0x32c0000 0x0 0x10000>; 982 clocks = <&bpmp TEGRA194_CLK_PWM5>; 983 resets = <&bpmp TEGRA194_RESET_PWM5>; 984 reset-names = "pwm"; 985 status = "disabled"; 986 #pwm-cells = <2>; 987 }; 988 989 pwm6: pwm@32d0000 { 990 compatible = "nvidia,tegra194-pwm", 991 "nvidia,tegra186-pwm"; 992 reg = <0x0 0x32d0000 0x0 0x10000>; 993 clocks = <&bpmp TEGRA194_CLK_PWM6>; 994 resets = <&bpmp TEGRA194_RESET_PWM6>; 995 reset-names = "pwm"; 996 status = "disabled"; 997 #pwm-cells = <2>; 998 }; 999 1000 pwm7: pwm@32e0000 { 1001 compatible = "nvidia,tegra194-pwm", 1002 "nvidia,tegra186-pwm"; 1003 reg = <0x0 0x32e0000 0x0 0x10000>; 1004 clocks = <&bpmp TEGRA194_CLK_PWM7>; 1005 resets = <&bpmp TEGRA194_RESET_PWM7>; 1006 reset-names = "pwm"; 1007 status = "disabled"; 1008 #pwm-cells = <2>; 1009 }; 1010 1011 pwm8: pwm@32f0000 { 1012 compatible = "nvidia,tegra194-pwm", 1013 "nvidia,tegra186-pwm"; 1014 reg = <0x0 0x32f0000 0x0 0x10000>; 1015 clocks = <&bpmp TEGRA194_CLK_PWM8>; 1016 resets = <&bpmp TEGRA194_RESET_PWM8>; 1017 reset-names = "pwm"; 1018 status = "disabled"; 1019 #pwm-cells = <2>; 1020 }; 1021 1022 spi@3300000 { 1023 compatible = "nvidia,tegra194-qspi"; 1024 reg = <0x0 0x3300000 0x0 0x1000>; 1025 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 1029 <&bpmp TEGRA194_CLK_QSPI1_PM>; 1030 clock-names = "qspi", "qspi_out"; 1031 resets = <&bpmp TEGRA194_RESET_QSPI1>; 1032 status = "disabled"; 1033 }; 1034 1035 sdmmc1: mmc@3400000 { 1036 compatible = "nvidia,tegra194-sdhci"; 1037 reg = <0x0 0x03400000 0x0 0x10000>; 1038 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1040 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1041 clock-names = "sdhci", "tmclk"; 1042 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1043 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1044 assigned-clock-parents = 1045 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1046 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1047 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 1048 reset-names = "sdhci"; 1049 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1050 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1051 interconnect-names = "dma-mem", "write"; 1052 iommus = <&smmu TEGRA194_SID_SDMMC1>; 1053 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1054 pinctrl-0 = <&sdmmc1_3v3>; 1055 pinctrl-1 = <&sdmmc1_1v8>; 1056 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 1057 <0x07>; 1058 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1059 <0x07>; 1060 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1061 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1062 <0x07>; 1063 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1064 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1065 nvidia,default-tap = <0x9>; 1066 nvidia,default-trim = <0x5>; 1067 sd-uhs-sdr25; 1068 sd-uhs-sdr50; 1069 sd-uhs-ddr50; 1070 sd-uhs-sdr104; 1071 status = "disabled"; 1072 }; 1073 1074 sdmmc3: mmc@3440000 { 1075 compatible = "nvidia,tegra194-sdhci"; 1076 reg = <0x0 0x03440000 0x0 0x10000>; 1077 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1079 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1080 clock-names = "sdhci", "tmclk"; 1081 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1082 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1083 assigned-clock-parents = 1084 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1085 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1086 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1087 reset-names = "sdhci"; 1088 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1089 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1090 interconnect-names = "dma-mem", "write"; 1091 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1092 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1093 pinctrl-0 = <&sdmmc3_3v3>; 1094 pinctrl-1 = <&sdmmc3_1v8>; 1095 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1096 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1097 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1098 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1099 <0x07>; 1100 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1101 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1102 <0x07>; 1103 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1104 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1105 nvidia,default-tap = <0x9>; 1106 nvidia,default-trim = <0x5>; 1107 sd-uhs-sdr25; 1108 sd-uhs-sdr50; 1109 sd-uhs-ddr50; 1110 sd-uhs-sdr104; 1111 status = "disabled"; 1112 }; 1113 1114 sdmmc4: mmc@3460000 { 1115 compatible = "nvidia,tegra194-sdhci"; 1116 reg = <0x0 0x03460000 0x0 0x10000>; 1117 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1119 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1120 clock-names = "sdhci", "tmclk"; 1121 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1122 <&bpmp TEGRA194_CLK_PLLC4>; 1123 assigned-clock-parents = 1124 <&bpmp TEGRA194_CLK_PLLC4>; 1125 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1126 reset-names = "sdhci"; 1127 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1128 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1129 interconnect-names = "dma-mem", "write"; 1130 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1131 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1132 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1133 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1134 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1135 <0x0a>; 1136 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1137 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1138 <0x0a>; 1139 nvidia,default-tap = <0x8>; 1140 nvidia,default-trim = <0x14>; 1141 nvidia,dqs-trim = <40>; 1142 cap-mmc-highspeed; 1143 mmc-ddr-1_8v; 1144 mmc-hs200-1_8v; 1145 mmc-hs400-1_8v; 1146 mmc-hs400-enhanced-strobe; 1147 supports-cqe; 1148 status = "disabled"; 1149 }; 1150 1151 hda@3510000 { 1152 compatible = "nvidia,tegra194-hda"; 1153 reg = <0x0 0x3510000 0x0 0x10000>; 1154 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1155 clocks = <&bpmp TEGRA194_CLK_HDA>, 1156 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1157 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1158 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1159 resets = <&bpmp TEGRA194_RESET_HDA>, 1160 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1161 reset-names = "hda", "hda2hdmi"; 1162 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1163 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1164 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1165 interconnect-names = "dma-mem", "write"; 1166 iommus = <&smmu TEGRA194_SID_HDA>; 1167 status = "disabled"; 1168 }; 1169 1170 xusb_padctl: padctl@3520000 { 1171 compatible = "nvidia,tegra194-xusb-padctl"; 1172 reg = <0x0 0x03520000 0x0 0x1000>, 1173 <0x0 0x03540000 0x0 0x1000>; 1174 reg-names = "padctl", "ao"; 1175 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1176 1177 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1178 reset-names = "padctl"; 1179 1180 status = "disabled"; 1181 1182 pads { 1183 usb2 { 1184 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1185 clock-names = "trk"; 1186 1187 lanes { 1188 usb2-0 { 1189 nvidia,function = "xusb"; 1190 status = "disabled"; 1191 #phy-cells = <0>; 1192 }; 1193 1194 usb2-1 { 1195 nvidia,function = "xusb"; 1196 status = "disabled"; 1197 #phy-cells = <0>; 1198 }; 1199 1200 usb2-2 { 1201 nvidia,function = "xusb"; 1202 status = "disabled"; 1203 #phy-cells = <0>; 1204 }; 1205 1206 usb2-3 { 1207 nvidia,function = "xusb"; 1208 status = "disabled"; 1209 #phy-cells = <0>; 1210 }; 1211 }; 1212 }; 1213 1214 usb3 { 1215 lanes { 1216 usb3-0 { 1217 nvidia,function = "xusb"; 1218 status = "disabled"; 1219 #phy-cells = <0>; 1220 }; 1221 1222 usb3-1 { 1223 nvidia,function = "xusb"; 1224 status = "disabled"; 1225 #phy-cells = <0>; 1226 }; 1227 1228 usb3-2 { 1229 nvidia,function = "xusb"; 1230 status = "disabled"; 1231 #phy-cells = <0>; 1232 }; 1233 1234 usb3-3 { 1235 nvidia,function = "xusb"; 1236 status = "disabled"; 1237 #phy-cells = <0>; 1238 }; 1239 }; 1240 }; 1241 }; 1242 1243 ports { 1244 usb2-0 { 1245 status = "disabled"; 1246 }; 1247 1248 usb2-1 { 1249 status = "disabled"; 1250 }; 1251 1252 usb2-2 { 1253 status = "disabled"; 1254 }; 1255 1256 usb2-3 { 1257 status = "disabled"; 1258 }; 1259 1260 usb3-0 { 1261 status = "disabled"; 1262 }; 1263 1264 usb3-1 { 1265 status = "disabled"; 1266 }; 1267 1268 usb3-2 { 1269 status = "disabled"; 1270 }; 1271 1272 usb3-3 { 1273 status = "disabled"; 1274 }; 1275 }; 1276 }; 1277 1278 usb@3550000 { 1279 compatible = "nvidia,tegra194-xudc"; 1280 reg = <0x0 0x03550000 0x0 0x8000>, 1281 <0x0 0x03558000 0x0 0x1000>; 1282 reg-names = "base", "fpci"; 1283 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1284 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1285 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1286 <&bpmp TEGRA194_CLK_XUSB_SS>, 1287 <&bpmp TEGRA194_CLK_XUSB_FS>; 1288 clock-names = "dev", "ss", "ss_src", "fs_src"; 1289 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1290 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1291 interconnect-names = "dma-mem", "write"; 1292 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1293 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1294 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1295 power-domain-names = "dev", "ss"; 1296 nvidia,xusb-padctl = <&xusb_padctl>; 1297 status = "disabled"; 1298 }; 1299 1300 usb@3610000 { 1301 compatible = "nvidia,tegra194-xusb"; 1302 reg = <0x0 0x03610000 0x0 0x40000>, 1303 <0x0 0x03600000 0x0 0x10000>; 1304 reg-names = "hcd", "fpci"; 1305 1306 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1308 1309 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1310 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1311 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1312 <&bpmp TEGRA194_CLK_XUSB_SS>, 1313 <&bpmp TEGRA194_CLK_CLK_M>, 1314 <&bpmp TEGRA194_CLK_XUSB_FS>, 1315 <&bpmp TEGRA194_CLK_UTMIPLL>, 1316 <&bpmp TEGRA194_CLK_CLK_M>, 1317 <&bpmp TEGRA194_CLK_PLLE>; 1318 clock-names = "xusb_host", "xusb_falcon_src", 1319 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1320 "xusb_fs_src", "pll_u_480m", "clk_m", 1321 "pll_e"; 1322 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1323 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1324 interconnect-names = "dma-mem", "write"; 1325 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1326 1327 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1328 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1329 power-domain-names = "xusb_host", "xusb_ss"; 1330 1331 nvidia,xusb-padctl = <&xusb_padctl>; 1332 status = "disabled"; 1333 }; 1334 1335 fuse@3820000 { 1336 compatible = "nvidia,tegra194-efuse"; 1337 reg = <0x0 0x03820000 0x0 0x10000>; 1338 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1339 clock-names = "fuse"; 1340 }; 1341 1342 gic: interrupt-controller@3881000 { 1343 compatible = "arm,gic-400"; 1344 #interrupt-cells = <3>; 1345 interrupt-controller; 1346 reg = <0x0 0x03881000 0x0 0x1000>, 1347 <0x0 0x03882000 0x0 0x2000>, 1348 <0x0 0x03884000 0x0 0x2000>, 1349 <0x0 0x03886000 0x0 0x2000>; 1350 interrupts = <GIC_PPI 9 1351 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1352 interrupt-parent = <&gic>; 1353 }; 1354 1355 cec@3960000 { 1356 compatible = "nvidia,tegra194-cec"; 1357 reg = <0x0 0x03960000 0x0 0x10000>; 1358 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1359 clocks = <&bpmp TEGRA194_CLK_CEC>; 1360 clock-names = "cec"; 1361 status = "disabled"; 1362 }; 1363 1364 hte_lic: hardware-timestamp@3aa0000 { 1365 compatible = "nvidia,tegra194-gte-lic"; 1366 reg = <0x0 0x3aa0000 0x0 0x10000>; 1367 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1368 nvidia,int-threshold = <1>; 1369 nvidia,slices = <11>; 1370 #timestamp-cells = <1>; 1371 status = "okay"; 1372 }; 1373 1374 hsp_top0: hsp@3c00000 { 1375 compatible = "nvidia,tegra194-hsp"; 1376 reg = <0x0 0x03c00000 0x0 0xa0000>; 1377 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1386 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1387 "shared3", "shared4", "shared5", "shared6", 1388 "shared7"; 1389 #mbox-cells = <2>; 1390 }; 1391 1392 p2u_hsio_0: phy@3e10000 { 1393 compatible = "nvidia,tegra194-p2u"; 1394 reg = <0x0 0x03e10000 0x0 0x10000>; 1395 reg-names = "ctl"; 1396 1397 #phy-cells = <0>; 1398 }; 1399 1400 p2u_hsio_1: phy@3e20000 { 1401 compatible = "nvidia,tegra194-p2u"; 1402 reg = <0x0 0x03e20000 0x0 0x10000>; 1403 reg-names = "ctl"; 1404 1405 #phy-cells = <0>; 1406 }; 1407 1408 p2u_hsio_2: phy@3e30000 { 1409 compatible = "nvidia,tegra194-p2u"; 1410 reg = <0x0 0x03e30000 0x0 0x10000>; 1411 reg-names = "ctl"; 1412 1413 #phy-cells = <0>; 1414 }; 1415 1416 p2u_hsio_3: phy@3e40000 { 1417 compatible = "nvidia,tegra194-p2u"; 1418 reg = <0x0 0x03e40000 0x0 0x10000>; 1419 reg-names = "ctl"; 1420 1421 #phy-cells = <0>; 1422 }; 1423 1424 p2u_hsio_4: phy@3e50000 { 1425 compatible = "nvidia,tegra194-p2u"; 1426 reg = <0x0 0x03e50000 0x0 0x10000>; 1427 reg-names = "ctl"; 1428 1429 #phy-cells = <0>; 1430 }; 1431 1432 p2u_hsio_5: phy@3e60000 { 1433 compatible = "nvidia,tegra194-p2u"; 1434 reg = <0x0 0x03e60000 0x0 0x10000>; 1435 reg-names = "ctl"; 1436 1437 #phy-cells = <0>; 1438 }; 1439 1440 p2u_hsio_6: phy@3e70000 { 1441 compatible = "nvidia,tegra194-p2u"; 1442 reg = <0x0 0x03e70000 0x0 0x10000>; 1443 reg-names = "ctl"; 1444 1445 #phy-cells = <0>; 1446 }; 1447 1448 p2u_hsio_7: phy@3e80000 { 1449 compatible = "nvidia,tegra194-p2u"; 1450 reg = <0x0 0x03e80000 0x0 0x10000>; 1451 reg-names = "ctl"; 1452 1453 #phy-cells = <0>; 1454 }; 1455 1456 p2u_hsio_8: phy@3e90000 { 1457 compatible = "nvidia,tegra194-p2u"; 1458 reg = <0x0 0x03e90000 0x0 0x10000>; 1459 reg-names = "ctl"; 1460 1461 #phy-cells = <0>; 1462 }; 1463 1464 p2u_hsio_9: phy@3ea0000 { 1465 compatible = "nvidia,tegra194-p2u"; 1466 reg = <0x0 0x03ea0000 0x0 0x10000>; 1467 reg-names = "ctl"; 1468 1469 #phy-cells = <0>; 1470 }; 1471 1472 p2u_nvhs_0: phy@3eb0000 { 1473 compatible = "nvidia,tegra194-p2u"; 1474 reg = <0x0 0x03eb0000 0x0 0x10000>; 1475 reg-names = "ctl"; 1476 1477 #phy-cells = <0>; 1478 }; 1479 1480 p2u_nvhs_1: phy@3ec0000 { 1481 compatible = "nvidia,tegra194-p2u"; 1482 reg = <0x0 0x03ec0000 0x0 0x10000>; 1483 reg-names = "ctl"; 1484 1485 #phy-cells = <0>; 1486 }; 1487 1488 p2u_nvhs_2: phy@3ed0000 { 1489 compatible = "nvidia,tegra194-p2u"; 1490 reg = <0x0 0x03ed0000 0x0 0x10000>; 1491 reg-names = "ctl"; 1492 1493 #phy-cells = <0>; 1494 }; 1495 1496 p2u_nvhs_3: phy@3ee0000 { 1497 compatible = "nvidia,tegra194-p2u"; 1498 reg = <0x0 0x03ee0000 0x0 0x10000>; 1499 reg-names = "ctl"; 1500 1501 #phy-cells = <0>; 1502 }; 1503 1504 p2u_nvhs_4: phy@3ef0000 { 1505 compatible = "nvidia,tegra194-p2u"; 1506 reg = <0x0 0x03ef0000 0x0 0x10000>; 1507 reg-names = "ctl"; 1508 1509 #phy-cells = <0>; 1510 }; 1511 1512 p2u_nvhs_5: phy@3f00000 { 1513 compatible = "nvidia,tegra194-p2u"; 1514 reg = <0x0 0x03f00000 0x0 0x10000>; 1515 reg-names = "ctl"; 1516 1517 #phy-cells = <0>; 1518 }; 1519 1520 p2u_nvhs_6: phy@3f10000 { 1521 compatible = "nvidia,tegra194-p2u"; 1522 reg = <0x0 0x03f10000 0x0 0x10000>; 1523 reg-names = "ctl"; 1524 1525 #phy-cells = <0>; 1526 }; 1527 1528 p2u_nvhs_7: phy@3f20000 { 1529 compatible = "nvidia,tegra194-p2u"; 1530 reg = <0x0 0x03f20000 0x0 0x10000>; 1531 reg-names = "ctl"; 1532 1533 #phy-cells = <0>; 1534 }; 1535 1536 p2u_hsio_10: phy@3f30000 { 1537 compatible = "nvidia,tegra194-p2u"; 1538 reg = <0x0 0x03f30000 0x0 0x10000>; 1539 reg-names = "ctl"; 1540 1541 #phy-cells = <0>; 1542 }; 1543 1544 p2u_hsio_11: phy@3f40000 { 1545 compatible = "nvidia,tegra194-p2u"; 1546 reg = <0x0 0x03f40000 0x0 0x10000>; 1547 reg-names = "ctl"; 1548 1549 #phy-cells = <0>; 1550 }; 1551 1552 sce-noc@b600000 { 1553 compatible = "nvidia,tegra194-sce-noc"; 1554 reg = <0x0 0xb600000 0x0 0x1000>; 1555 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1557 nvidia,axi2apb = <&axi2apb>; 1558 nvidia,apbmisc = <&apbmisc>; 1559 status = "okay"; 1560 }; 1561 1562 rce-noc@be00000 { 1563 compatible = "nvidia,tegra194-rce-noc"; 1564 reg = <0x0 0xbe00000 0x0 0x1000>; 1565 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1567 nvidia,axi2apb = <&axi2apb>; 1568 nvidia,apbmisc = <&apbmisc>; 1569 status = "okay"; 1570 }; 1571 1572 hsp_aon: hsp@c150000 { 1573 compatible = "nvidia,tegra194-hsp"; 1574 reg = <0x0 0x0c150000 0x0 0x90000>; 1575 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1579 /* 1580 * Shared interrupt 0 is routed only to AON/SPE, so 1581 * we only have 4 shared interrupts for the CCPLEX. 1582 */ 1583 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1584 #mbox-cells = <2>; 1585 }; 1586 1587 hte_aon: hardware-timestamp@c1e0000 { 1588 compatible = "nvidia,tegra194-gte-aon"; 1589 reg = <0x0 0xc1e0000 0x0 0x10000>; 1590 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1591 nvidia,int-threshold = <1>; 1592 nvidia,slices = <3>; 1593 #timestamp-cells = <1>; 1594 status = "okay"; 1595 }; 1596 1597 gen2_i2c: i2c@c240000 { 1598 compatible = "nvidia,tegra194-i2c"; 1599 reg = <0x0 0x0c240000 0x0 0x10000>; 1600 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1604 clock-names = "div-clk"; 1605 resets = <&bpmp TEGRA194_RESET_I2C2>; 1606 reset-names = "i2c"; 1607 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1608 dma-coherent; 1609 dmas = <&gpcdma 22>, <&gpcdma 22>; 1610 dma-names = "rx", "tx"; 1611 status = "disabled"; 1612 }; 1613 1614 gen8_i2c: i2c@c250000 { 1615 compatible = "nvidia,tegra194-i2c"; 1616 reg = <0x0 0x0c250000 0x0 0x10000>; 1617 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1618 #address-cells = <1>; 1619 #size-cells = <0>; 1620 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1621 clock-names = "div-clk"; 1622 resets = <&bpmp TEGRA194_RESET_I2C8>; 1623 reset-names = "i2c"; 1624 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1625 dma-coherent; 1626 dmas = <&gpcdma 0>, <&gpcdma 0>; 1627 dma-names = "rx", "tx"; 1628 status = "disabled"; 1629 }; 1630 1631 uartc: serial@c280000 { 1632 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1633 reg = <0x0 0x0c280000 0x0 0x40>; 1634 reg-shift = <2>; 1635 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1636 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1637 clock-names = "serial"; 1638 resets = <&bpmp TEGRA194_RESET_UARTC>; 1639 reset-names = "serial"; 1640 status = "disabled"; 1641 }; 1642 1643 uartg: serial@c290000 { 1644 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1645 reg = <0x0 0x0c290000 0x0 0x40>; 1646 reg-shift = <2>; 1647 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1648 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1649 clock-names = "serial"; 1650 resets = <&bpmp TEGRA194_RESET_UARTG>; 1651 reset-names = "serial"; 1652 status = "disabled"; 1653 }; 1654 1655 rtc: rtc@c2a0000 { 1656 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1657 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1658 interrupt-parent = <&pmc>; 1659 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1660 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1661 clock-names = "rtc"; 1662 status = "disabled"; 1663 }; 1664 1665 gpio_aon: gpio@c2f0000 { 1666 compatible = "nvidia,tegra194-gpio-aon"; 1667 reg-names = "security", "gpio"; 1668 reg = <0x0 0xc2f0000 0x0 0x1000>, 1669 <0x0 0xc2f1000 0x0 0x1000>; 1670 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1674 gpio-controller; 1675 #gpio-cells = <2>; 1676 interrupt-controller; 1677 #interrupt-cells = <2>; 1678 gpio-ranges = <&pinmux_aon 0 0 30>; 1679 }; 1680 1681 pinmux_aon: pinmux@c300000 { 1682 compatible = "nvidia,tegra194-pinmux-aon"; 1683 reg = <0x0 0xc300000 0x0 0x4000>; 1684 1685 status = "okay"; 1686 }; 1687 1688 pwm4: pwm@c340000 { 1689 compatible = "nvidia,tegra194-pwm", 1690 "nvidia,tegra186-pwm"; 1691 reg = <0x0 0xc340000 0x0 0x10000>; 1692 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1693 resets = <&bpmp TEGRA194_RESET_PWM4>; 1694 reset-names = "pwm"; 1695 status = "disabled"; 1696 #pwm-cells = <2>; 1697 }; 1698 1699 pmc: pmc@c360000 { 1700 compatible = "nvidia,tegra194-pmc"; 1701 reg = <0x0 0x0c360000 0x0 0x10000>, 1702 <0x0 0x0c370000 0x0 0x10000>, 1703 <0x0 0x0c380000 0x0 0x10000>, 1704 <0x0 0x0c390000 0x0 0x10000>, 1705 <0x0 0x0c3a0000 0x0 0x10000>; 1706 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1707 1708 #interrupt-cells = <2>; 1709 interrupt-controller; 1710 1711 sdmmc1_1v8: sdmmc1-1v8 { 1712 pins = "sdmmc1-hv"; 1713 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1714 }; 1715 1716 sdmmc1_3v3: sdmmc1-3v3 { 1717 pins = "sdmmc1-hv"; 1718 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1719 }; 1720 1721 sdmmc3_1v8: sdmmc3-1v8 { 1722 pins = "sdmmc3-hv"; 1723 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1724 }; 1725 1726 sdmmc3_3v3: sdmmc3-3v3 { 1727 pins = "sdmmc3-hv"; 1728 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1729 }; 1730 }; 1731 1732 aon-noc@c600000 { 1733 compatible = "nvidia,tegra194-aon-noc"; 1734 reg = <0x0 0xc600000 0x0 0x1000>; 1735 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1737 nvidia,apbmisc = <&apbmisc>; 1738 status = "okay"; 1739 }; 1740 1741 bpmp-noc@d600000 { 1742 compatible = "nvidia,tegra194-bpmp-noc"; 1743 reg = <0x0 0xd600000 0x0 0x1000>; 1744 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1746 nvidia,axi2apb = <&axi2apb>; 1747 nvidia,apbmisc = <&apbmisc>; 1748 status = "okay"; 1749 }; 1750 1751 iommu@10000000 { 1752 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1753 reg = <0x0 0x10000000 0x0 0x800000>; 1754 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1818 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1819 stream-match-mask = <0x7f80>; 1820 #global-interrupts = <1>; 1821 #iommu-cells = <1>; 1822 1823 nvidia,memory-controller = <&mc>; 1824 status = "disabled"; 1825 }; 1826 1827 smmu: iommu@12000000 { 1828 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1829 reg = <0x0 0x12000000 0x0 0x800000>, 1830 <0x0 0x11000000 0x0 0x800000>; 1831 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1897 stream-match-mask = <0x7f80>; 1898 #global-interrupts = <2>; 1899 #iommu-cells = <1>; 1900 1901 nvidia,memory-controller = <&mc>; 1902 status = "okay"; 1903 }; 1904 1905 host1x@13e00000 { 1906 compatible = "nvidia,tegra194-host1x"; 1907 reg = <0x0 0x13e00000 0x0 0x10000>, 1908 <0x0 0x13e10000 0x0 0x10000>; 1909 reg-names = "hypervisor", "vm"; 1910 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1912 interrupt-names = "syncpt", "host1x"; 1913 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1914 clock-names = "host1x"; 1915 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1916 reset-names = "host1x"; 1917 1918 #address-cells = <2>; 1919 #size-cells = <2>; 1920 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>; 1921 1922 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1923 interconnect-names = "dma-mem"; 1924 iommus = <&smmu TEGRA194_SID_HOST1X>; 1925 1926 /* Context isolation domains */ 1927 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1928 <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1929 <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1930 <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1931 <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1932 <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1933 <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1934 <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1935 1936 nvdec@15140000 { 1937 compatible = "nvidia,tegra194-nvdec"; 1938 reg = <0x0 0x15140000 0x0 0x00040000>; 1939 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1940 clock-names = "nvdec"; 1941 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1942 reset-names = "nvdec"; 1943 1944 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1945 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1946 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1947 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1948 interconnect-names = "dma-mem", "read-1", "write"; 1949 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1950 dma-coherent; 1951 1952 nvidia,host1x-class = <0xf5>; 1953 }; 1954 1955 display-hub@15200000 { 1956 compatible = "nvidia,tegra194-display"; 1957 reg = <0x0 0x15200000 0x0 0x00040000>; 1958 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1959 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1960 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1961 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1962 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1963 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1964 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1965 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1966 "wgrp3", "wgrp4", "wgrp5"; 1967 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1968 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1969 clock-names = "disp", "hub"; 1970 status = "disabled"; 1971 1972 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1973 1974 #address-cells = <2>; 1975 #size-cells = <2>; 1976 ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; 1977 1978 display@15200000 { 1979 compatible = "nvidia,tegra194-dc"; 1980 reg = <0x0 0x15200000 0x0 0x10000>; 1981 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1982 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1983 clock-names = "dc"; 1984 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1985 reset-names = "dc"; 1986 1987 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1988 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1989 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1990 interconnect-names = "dma-mem", "read-1"; 1991 1992 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1993 nvidia,head = <0>; 1994 }; 1995 1996 display@15210000 { 1997 compatible = "nvidia,tegra194-dc"; 1998 reg = <0x0 0x15210000 0x0 0x10000>; 1999 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 2000 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 2001 clock-names = "dc"; 2002 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 2003 reset-names = "dc"; 2004 2005 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 2006 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2007 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2008 interconnect-names = "dma-mem", "read-1"; 2009 2010 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2011 nvidia,head = <1>; 2012 }; 2013 2014 display@15220000 { 2015 compatible = "nvidia,tegra194-dc"; 2016 reg = <0x0 0x15220000 0x0 0x10000>; 2017 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2018 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 2019 clock-names = "dc"; 2020 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 2021 reset-names = "dc"; 2022 2023 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2024 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2025 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2026 interconnect-names = "dma-mem", "read-1"; 2027 2028 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2029 nvidia,head = <2>; 2030 }; 2031 2032 display@15230000 { 2033 compatible = "nvidia,tegra194-dc"; 2034 reg = <0x0 0x15230000 0x0 0x10000>; 2035 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2036 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 2037 clock-names = "dc"; 2038 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 2039 reset-names = "dc"; 2040 2041 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2042 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2043 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2044 interconnect-names = "dma-mem", "read-1"; 2045 2046 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2047 nvidia,head = <3>; 2048 }; 2049 }; 2050 2051 vic@15340000 { 2052 compatible = "nvidia,tegra194-vic"; 2053 reg = <0x0 0x15340000 0x0 0x00040000>; 2054 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2055 clocks = <&bpmp TEGRA194_CLK_VIC>; 2056 clock-names = "vic"; 2057 resets = <&bpmp TEGRA194_RESET_VIC>; 2058 reset-names = "vic"; 2059 2060 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2061 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2062 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2063 interconnect-names = "dma-mem", "write"; 2064 iommus = <&smmu TEGRA194_SID_VIC>; 2065 dma-coherent; 2066 }; 2067 2068 nvjpg@15380000 { 2069 compatible = "nvidia,tegra194-nvjpg"; 2070 reg = <0x0 0x15380000 0x0 0x40000>; 2071 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2072 clock-names = "nvjpg"; 2073 resets = <&bpmp TEGRA194_RESET_NVJPG>; 2074 reset-names = "nvjpg"; 2075 2076 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2077 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2078 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2079 interconnect-names = "dma-mem", "write"; 2080 iommus = <&smmu TEGRA194_SID_NVJPG>; 2081 dma-coherent; 2082 }; 2083 2084 nvdec@15480000 { 2085 compatible = "nvidia,tegra194-nvdec"; 2086 reg = <0x0 0x15480000 0x0 0x00040000>; 2087 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 2088 clock-names = "nvdec"; 2089 resets = <&bpmp TEGRA194_RESET_NVDEC>; 2090 reset-names = "nvdec"; 2091 2092 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 2093 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 2094 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 2095 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 2096 interconnect-names = "dma-mem", "read-1", "write"; 2097 iommus = <&smmu TEGRA194_SID_NVDEC>; 2098 dma-coherent; 2099 2100 nvidia,host1x-class = <0xf0>; 2101 }; 2102 2103 nvenc@154c0000 { 2104 compatible = "nvidia,tegra194-nvenc"; 2105 reg = <0x0 0x154c0000 0x0 0x40000>; 2106 clocks = <&bpmp TEGRA194_CLK_NVENC>; 2107 clock-names = "nvenc"; 2108 resets = <&bpmp TEGRA194_RESET_NVENC>; 2109 reset-names = "nvenc"; 2110 2111 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2112 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2113 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2114 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2115 interconnect-names = "dma-mem", "read-1", "write"; 2116 iommus = <&smmu TEGRA194_SID_NVENC>; 2117 dma-coherent; 2118 2119 nvidia,host1x-class = <0x21>; 2120 }; 2121 2122 dpaux0: dpaux@155c0000 { 2123 compatible = "nvidia,tegra194-dpaux"; 2124 reg = <0x0 0x155c0000 0x0 0x10000>; 2125 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 2126 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 2127 <&bpmp TEGRA194_CLK_PLLDP>; 2128 clock-names = "dpaux", "parent"; 2129 resets = <&bpmp TEGRA194_RESET_DPAUX>; 2130 reset-names = "dpaux"; 2131 status = "disabled"; 2132 2133 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2134 2135 state_dpaux0_aux: pinmux-aux { 2136 groups = "dpaux-io"; 2137 function = "aux"; 2138 }; 2139 2140 state_dpaux0_i2c: pinmux-i2c { 2141 groups = "dpaux-io"; 2142 function = "i2c"; 2143 }; 2144 2145 state_dpaux0_off: pinmux-off { 2146 groups = "dpaux-io"; 2147 function = "off"; 2148 }; 2149 2150 i2c-bus { 2151 #address-cells = <1>; 2152 #size-cells = <0>; 2153 }; 2154 }; 2155 2156 dpaux1: dpaux@155d0000 { 2157 compatible = "nvidia,tegra194-dpaux"; 2158 reg = <0x0 0x155d0000 0x0 0x10000>; 2159 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2160 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 2161 <&bpmp TEGRA194_CLK_PLLDP>; 2162 clock-names = "dpaux", "parent"; 2163 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2164 reset-names = "dpaux"; 2165 status = "disabled"; 2166 2167 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2168 2169 state_dpaux1_aux: pinmux-aux { 2170 groups = "dpaux-io"; 2171 function = "aux"; 2172 }; 2173 2174 state_dpaux1_i2c: pinmux-i2c { 2175 groups = "dpaux-io"; 2176 function = "i2c"; 2177 }; 2178 2179 state_dpaux1_off: pinmux-off { 2180 groups = "dpaux-io"; 2181 function = "off"; 2182 }; 2183 2184 i2c-bus { 2185 #address-cells = <1>; 2186 #size-cells = <0>; 2187 }; 2188 }; 2189 2190 dpaux2: dpaux@155e0000 { 2191 compatible = "nvidia,tegra194-dpaux"; 2192 reg = <0x0 0x155e0000 0x0 0x10000>; 2193 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2194 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2195 <&bpmp TEGRA194_CLK_PLLDP>; 2196 clock-names = "dpaux", "parent"; 2197 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2198 reset-names = "dpaux"; 2199 status = "disabled"; 2200 2201 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2202 2203 state_dpaux2_aux: pinmux-aux { 2204 groups = "dpaux-io"; 2205 function = "aux"; 2206 }; 2207 2208 state_dpaux2_i2c: pinmux-i2c { 2209 groups = "dpaux-io"; 2210 function = "i2c"; 2211 }; 2212 2213 state_dpaux2_off: pinmux-off { 2214 groups = "dpaux-io"; 2215 function = "off"; 2216 }; 2217 2218 i2c-bus { 2219 #address-cells = <1>; 2220 #size-cells = <0>; 2221 }; 2222 }; 2223 2224 dpaux3: dpaux@155f0000 { 2225 compatible = "nvidia,tegra194-dpaux"; 2226 reg = <0x0 0x155f0000 0x0 0x10000>; 2227 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2228 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2229 <&bpmp TEGRA194_CLK_PLLDP>; 2230 clock-names = "dpaux", "parent"; 2231 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2232 reset-names = "dpaux"; 2233 status = "disabled"; 2234 2235 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2236 2237 state_dpaux3_aux: pinmux-aux { 2238 groups = "dpaux-io"; 2239 function = "aux"; 2240 }; 2241 2242 state_dpaux3_i2c: pinmux-i2c { 2243 groups = "dpaux-io"; 2244 function = "i2c"; 2245 }; 2246 2247 state_dpaux3_off: pinmux-off { 2248 groups = "dpaux-io"; 2249 function = "off"; 2250 }; 2251 2252 i2c-bus { 2253 #address-cells = <1>; 2254 #size-cells = <0>; 2255 }; 2256 }; 2257 2258 nvenc@15a80000 { 2259 compatible = "nvidia,tegra194-nvenc"; 2260 reg = <0x0 0x15a80000 0x0 0x00040000>; 2261 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2262 clock-names = "nvenc"; 2263 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2264 reset-names = "nvenc"; 2265 2266 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2267 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2268 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2269 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2270 interconnect-names = "dma-mem", "read-1", "write"; 2271 iommus = <&smmu TEGRA194_SID_NVENC1>; 2272 dma-coherent; 2273 2274 nvidia,host1x-class = <0x22>; 2275 }; 2276 2277 sor0: sor@15b00000 { 2278 compatible = "nvidia,tegra194-sor"; 2279 reg = <0x0 0x15b00000 0x0 0x40000>; 2280 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2281 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2282 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2283 <&bpmp TEGRA194_CLK_PLLD>, 2284 <&bpmp TEGRA194_CLK_PLLDP>, 2285 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2286 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2287 clock-names = "sor", "out", "parent", "dp", "safe", 2288 "pad"; 2289 resets = <&bpmp TEGRA194_RESET_SOR0>; 2290 reset-names = "sor"; 2291 pinctrl-0 = <&state_dpaux0_aux>; 2292 pinctrl-1 = <&state_dpaux0_i2c>; 2293 pinctrl-2 = <&state_dpaux0_off>; 2294 pinctrl-names = "aux", "i2c", "off"; 2295 status = "disabled"; 2296 2297 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2298 nvidia,interface = <0>; 2299 }; 2300 2301 sor1: sor@15b40000 { 2302 compatible = "nvidia,tegra194-sor"; 2303 reg = <0x0 0x15b40000 0x0 0x40000>; 2304 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2305 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2306 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2307 <&bpmp TEGRA194_CLK_PLLD2>, 2308 <&bpmp TEGRA194_CLK_PLLDP>, 2309 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2310 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2311 clock-names = "sor", "out", "parent", "dp", "safe", 2312 "pad"; 2313 resets = <&bpmp TEGRA194_RESET_SOR1>; 2314 reset-names = "sor"; 2315 pinctrl-0 = <&state_dpaux1_aux>; 2316 pinctrl-1 = <&state_dpaux1_i2c>; 2317 pinctrl-2 = <&state_dpaux1_off>; 2318 pinctrl-names = "aux", "i2c", "off"; 2319 status = "disabled"; 2320 2321 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2322 nvidia,interface = <1>; 2323 }; 2324 2325 sor2: sor@15b80000 { 2326 compatible = "nvidia,tegra194-sor"; 2327 reg = <0x0 0x15b80000 0x0 0x40000>; 2328 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2329 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2330 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2331 <&bpmp TEGRA194_CLK_PLLD3>, 2332 <&bpmp TEGRA194_CLK_PLLDP>, 2333 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2334 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2335 clock-names = "sor", "out", "parent", "dp", "safe", 2336 "pad"; 2337 resets = <&bpmp TEGRA194_RESET_SOR2>; 2338 reset-names = "sor"; 2339 pinctrl-0 = <&state_dpaux2_aux>; 2340 pinctrl-1 = <&state_dpaux2_i2c>; 2341 pinctrl-2 = <&state_dpaux2_off>; 2342 pinctrl-names = "aux", "i2c", "off"; 2343 status = "disabled"; 2344 2345 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2346 nvidia,interface = <2>; 2347 }; 2348 2349 sor3: sor@15bc0000 { 2350 compatible = "nvidia,tegra194-sor"; 2351 reg = <0x0 0x15bc0000 0x0 0x40000>; 2352 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2353 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2354 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2355 <&bpmp TEGRA194_CLK_PLLD4>, 2356 <&bpmp TEGRA194_CLK_PLLDP>, 2357 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2358 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2359 clock-names = "sor", "out", "parent", "dp", "safe", 2360 "pad"; 2361 resets = <&bpmp TEGRA194_RESET_SOR3>; 2362 reset-names = "sor"; 2363 pinctrl-0 = <&state_dpaux3_aux>; 2364 pinctrl-1 = <&state_dpaux3_i2c>; 2365 pinctrl-2 = <&state_dpaux3_off>; 2366 pinctrl-names = "aux", "i2c", "off"; 2367 status = "disabled"; 2368 2369 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2370 nvidia,interface = <3>; 2371 }; 2372 }; 2373 2374 pcie@14100000 { 2375 compatible = "nvidia,tegra194-pcie"; 2376 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2377 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2378 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2379 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2380 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2381 reg-names = "appl", "config", "atu_dma", "dbi"; 2382 2383 status = "disabled"; 2384 2385 #address-cells = <3>; 2386 #size-cells = <2>; 2387 device_type = "pci"; 2388 num-lanes = <1>; 2389 linux,pci-domain = <1>; 2390 2391 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2392 clock-names = "core"; 2393 2394 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2395 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2396 reset-names = "apb", "core"; 2397 2398 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2399 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2400 interrupt-names = "intr", "msi"; 2401 2402 #interrupt-cells = <1>; 2403 interrupt-map-mask = <0 0 0 0>; 2404 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2405 2406 nvidia,bpmp = <&bpmp 1>; 2407 2408 nvidia,aspm-cmrt-us = <60>; 2409 nvidia,aspm-pwr-on-t-us = <20>; 2410 nvidia,aspm-l0s-entrance-latency-us = <3>; 2411 2412 bus-range = <0x0 0xff>; 2413 2414 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2415 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2416 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2417 2418 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2419 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2420 interconnect-names = "dma-mem", "write"; 2421 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2422 iommu-map-mask = <0x0>; 2423 dma-coherent; 2424 }; 2425 2426 pcie@14120000 { 2427 compatible = "nvidia,tegra194-pcie"; 2428 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2429 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2430 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2431 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2432 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2433 reg-names = "appl", "config", "atu_dma", "dbi"; 2434 2435 status = "disabled"; 2436 2437 #address-cells = <3>; 2438 #size-cells = <2>; 2439 device_type = "pci"; 2440 num-lanes = <1>; 2441 linux,pci-domain = <2>; 2442 2443 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2444 clock-names = "core"; 2445 2446 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2447 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2448 reset-names = "apb", "core"; 2449 2450 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2451 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2452 interrupt-names = "intr", "msi"; 2453 2454 #interrupt-cells = <1>; 2455 interrupt-map-mask = <0 0 0 0>; 2456 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2457 2458 nvidia,bpmp = <&bpmp 2>; 2459 2460 nvidia,aspm-cmrt-us = <60>; 2461 nvidia,aspm-pwr-on-t-us = <20>; 2462 nvidia,aspm-l0s-entrance-latency-us = <3>; 2463 2464 bus-range = <0x0 0xff>; 2465 2466 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2467 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2468 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2469 2470 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2471 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2472 interconnect-names = "dma-mem", "write"; 2473 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2474 iommu-map-mask = <0x0>; 2475 dma-coherent; 2476 }; 2477 2478 pcie@14140000 { 2479 compatible = "nvidia,tegra194-pcie"; 2480 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2481 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2482 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2483 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2484 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2485 reg-names = "appl", "config", "atu_dma", "dbi"; 2486 2487 status = "disabled"; 2488 2489 #address-cells = <3>; 2490 #size-cells = <2>; 2491 device_type = "pci"; 2492 num-lanes = <1>; 2493 linux,pci-domain = <3>; 2494 2495 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2496 clock-names = "core"; 2497 2498 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2499 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2500 reset-names = "apb", "core"; 2501 2502 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2503 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2504 interrupt-names = "intr", "msi"; 2505 2506 #interrupt-cells = <1>; 2507 interrupt-map-mask = <0 0 0 0>; 2508 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2509 2510 nvidia,bpmp = <&bpmp 3>; 2511 2512 nvidia,aspm-cmrt-us = <60>; 2513 nvidia,aspm-pwr-on-t-us = <20>; 2514 nvidia,aspm-l0s-entrance-latency-us = <3>; 2515 2516 bus-range = <0x0 0xff>; 2517 2518 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2519 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2520 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2521 2522 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2523 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2524 interconnect-names = "dma-mem", "write"; 2525 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2526 iommu-map-mask = <0x0>; 2527 dma-coherent; 2528 }; 2529 2530 pcie@14160000 { 2531 compatible = "nvidia,tegra194-pcie"; 2532 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2533 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2534 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2535 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2536 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2537 reg-names = "appl", "config", "atu_dma", "dbi"; 2538 2539 status = "disabled"; 2540 2541 #address-cells = <3>; 2542 #size-cells = <2>; 2543 device_type = "pci"; 2544 num-lanes = <4>; 2545 linux,pci-domain = <4>; 2546 2547 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2548 clock-names = "core"; 2549 2550 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2551 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2552 reset-names = "apb", "core"; 2553 2554 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2555 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2556 interrupt-names = "intr", "msi"; 2557 2558 #interrupt-cells = <1>; 2559 interrupt-map-mask = <0 0 0 0>; 2560 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2561 2562 nvidia,bpmp = <&bpmp 4>; 2563 2564 nvidia,aspm-cmrt-us = <60>; 2565 nvidia,aspm-pwr-on-t-us = <20>; 2566 nvidia,aspm-l0s-entrance-latency-us = <3>; 2567 2568 bus-range = <0x0 0xff>; 2569 2570 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2571 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2572 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2573 2574 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2575 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2576 interconnect-names = "dma-mem", "write"; 2577 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2578 iommu-map-mask = <0x0>; 2579 dma-coherent; 2580 }; 2581 2582 pcie-ep@14160000 { 2583 compatible = "nvidia,tegra194-pcie-ep"; 2584 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2585 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2586 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2587 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2588 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2589 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2590 2591 status = "disabled"; 2592 2593 num-lanes = <4>; 2594 num-ib-windows = <2>; 2595 num-ob-windows = <8>; 2596 2597 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2598 clock-names = "core"; 2599 2600 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2601 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2602 reset-names = "apb", "core"; 2603 2604 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2605 interrupt-names = "intr"; 2606 2607 nvidia,bpmp = <&bpmp 4>; 2608 2609 nvidia,aspm-cmrt-us = <60>; 2610 nvidia,aspm-pwr-on-t-us = <20>; 2611 nvidia,aspm-l0s-entrance-latency-us = <3>; 2612 2613 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2614 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2615 interconnect-names = "dma-mem", "write"; 2616 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2617 iommu-map-mask = <0x0>; 2618 dma-coherent; 2619 }; 2620 2621 pcie@14180000 { 2622 compatible = "nvidia,tegra194-pcie"; 2623 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2624 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2625 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2626 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2627 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2628 reg-names = "appl", "config", "atu_dma", "dbi"; 2629 2630 status = "disabled"; 2631 2632 #address-cells = <3>; 2633 #size-cells = <2>; 2634 device_type = "pci"; 2635 num-lanes = <8>; 2636 linux,pci-domain = <0>; 2637 2638 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2639 clock-names = "core"; 2640 2641 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2642 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2643 reset-names = "apb", "core"; 2644 2645 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2646 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2647 interrupt-names = "intr", "msi"; 2648 2649 #interrupt-cells = <1>; 2650 interrupt-map-mask = <0 0 0 0>; 2651 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2652 2653 nvidia,bpmp = <&bpmp 0>; 2654 2655 nvidia,aspm-cmrt-us = <60>; 2656 nvidia,aspm-pwr-on-t-us = <20>; 2657 nvidia,aspm-l0s-entrance-latency-us = <3>; 2658 2659 bus-range = <0x0 0xff>; 2660 2661 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2662 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2663 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2664 2665 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2666 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2667 interconnect-names = "dma-mem", "write"; 2668 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2669 iommu-map-mask = <0x0>; 2670 dma-coherent; 2671 }; 2672 2673 pcie-ep@14180000 { 2674 compatible = "nvidia,tegra194-pcie-ep"; 2675 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2676 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2677 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2678 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2679 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2680 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2681 2682 status = "disabled"; 2683 2684 num-lanes = <8>; 2685 num-ib-windows = <2>; 2686 num-ob-windows = <8>; 2687 2688 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2689 clock-names = "core"; 2690 2691 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2692 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2693 reset-names = "apb", "core"; 2694 2695 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2696 interrupt-names = "intr"; 2697 2698 nvidia,bpmp = <&bpmp 0>; 2699 2700 nvidia,aspm-cmrt-us = <60>; 2701 nvidia,aspm-pwr-on-t-us = <20>; 2702 nvidia,aspm-l0s-entrance-latency-us = <3>; 2703 2704 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2705 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2706 interconnect-names = "dma-mem", "write"; 2707 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2708 iommu-map-mask = <0x0>; 2709 dma-coherent; 2710 }; 2711 2712 pcie@141a0000 { 2713 compatible = "nvidia,tegra194-pcie"; 2714 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2715 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2716 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2717 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2718 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2719 reg-names = "appl", "config", "atu_dma", "dbi"; 2720 2721 status = "disabled"; 2722 2723 #address-cells = <3>; 2724 #size-cells = <2>; 2725 device_type = "pci"; 2726 num-lanes = <8>; 2727 linux,pci-domain = <5>; 2728 2729 pinctrl-names = "default"; 2730 pinctrl-0 = <&pex_rst_c5_out_state>, <&pex_clkreq_c5_bi_dir_state>; 2731 2732 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2733 clock-names = "core"; 2734 2735 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2736 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2737 reset-names = "apb", "core"; 2738 2739 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2740 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2741 interrupt-names = "intr", "msi"; 2742 2743 nvidia,bpmp = <&bpmp 5>; 2744 2745 #interrupt-cells = <1>; 2746 interrupt-map-mask = <0 0 0 0>; 2747 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2748 2749 nvidia,aspm-cmrt-us = <60>; 2750 nvidia,aspm-pwr-on-t-us = <20>; 2751 nvidia,aspm-l0s-entrance-latency-us = <3>; 2752 2753 bus-range = <0x0 0xff>; 2754 2755 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2756 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2757 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2758 2759 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2760 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2761 interconnect-names = "dma-mem", "write"; 2762 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2763 iommu-map-mask = <0x0>; 2764 dma-coherent; 2765 }; 2766 2767 pcie-ep@141a0000 { 2768 compatible = "nvidia,tegra194-pcie-ep"; 2769 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2770 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2771 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2772 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2773 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2774 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2775 2776 status = "disabled"; 2777 2778 num-lanes = <8>; 2779 num-ib-windows = <2>; 2780 num-ob-windows = <8>; 2781 2782 pinctrl-names = "default"; 2783 pinctrl-0 = <&pex_clkreq_c5_bi_dir_state>; 2784 2785 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2786 clock-names = "core"; 2787 2788 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2789 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2790 reset-names = "apb", "core"; 2791 2792 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2793 interrupt-names = "intr"; 2794 2795 nvidia,bpmp = <&bpmp 5>; 2796 2797 nvidia,aspm-cmrt-us = <60>; 2798 nvidia,aspm-pwr-on-t-us = <20>; 2799 nvidia,aspm-l0s-entrance-latency-us = <3>; 2800 2801 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2802 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2803 interconnect-names = "dma-mem", "write"; 2804 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2805 iommu-map-mask = <0x0>; 2806 dma-coherent; 2807 }; 2808 2809 gpu@17000000 { 2810 compatible = "nvidia,gv11b"; 2811 reg = <0x0 0x17000000 0x0 0x1000000>, 2812 <0x0 0x18000000 0x0 0x1000000>; 2813 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2814 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2815 interrupt-names = "stall", "nonstall"; 2816 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2817 <&bpmp TEGRA194_CLK_GPU_PWR>, 2818 <&bpmp TEGRA194_CLK_FUSE>; 2819 clock-names = "gpu", "pwr", "fuse"; 2820 resets = <&bpmp TEGRA194_RESET_GPU>; 2821 reset-names = "gpu"; 2822 dma-coherent; 2823 2824 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2825 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2826 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2827 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2828 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2829 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2830 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2831 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2832 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2833 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2834 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2835 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2836 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2837 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2838 "read-1", "read-1-hp", "write-1", 2839 "read-2", "read-2-hp", "write-2", 2840 "read-3", "read-3-hp", "write-3"; 2841 }; 2842 }; 2843 2844 sram@40000000 { 2845 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2846 reg = <0x0 0x40000000 0x0 0x50000>; 2847 2848 #address-cells = <1>; 2849 #size-cells = <1>; 2850 ranges = <0x0 0x0 0x40000000 0x50000>; 2851 2852 no-memory-wc; 2853 2854 cpu_bpmp_tx: sram@4e000 { 2855 reg = <0x4e000 0x1000>; 2856 label = "cpu-bpmp-tx"; 2857 pool; 2858 }; 2859 2860 cpu_bpmp_rx: sram@4f000 { 2861 reg = <0x4f000 0x1000>; 2862 label = "cpu-bpmp-rx"; 2863 pool; 2864 }; 2865 }; 2866 2867 bpmp: bpmp { 2868 compatible = "nvidia,tegra186-bpmp"; 2869 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2870 TEGRA_HSP_DB_MASTER_BPMP>; 2871 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2872 #clock-cells = <1>; 2873 #reset-cells = <1>; 2874 #power-domain-cells = <1>; 2875 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2876 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2877 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2878 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2879 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2880 iommus = <&smmu TEGRA194_SID_BPMP>; 2881 2882 bpmp_i2c: i2c { 2883 compatible = "nvidia,tegra186-bpmp-i2c"; 2884 nvidia,bpmp-bus-id = <5>; 2885 #address-cells = <1>; 2886 #size-cells = <0>; 2887 }; 2888 2889 bpmp_thermal: thermal { 2890 compatible = "nvidia,tegra186-bpmp-thermal"; 2891 #thermal-sensor-cells = <1>; 2892 }; 2893 }; 2894 2895 cpus { 2896 compatible = "nvidia,tegra194-ccplex"; 2897 nvidia,bpmp = <&bpmp>; 2898 #address-cells = <1>; 2899 #size-cells = <0>; 2900 2901 cpu0_0: cpu@0 { 2902 compatible = "nvidia,tegra194-carmel"; 2903 device_type = "cpu"; 2904 reg = <0x000>; 2905 enable-method = "psci"; 2906 i-cache-size = <131072>; 2907 i-cache-line-size = <64>; 2908 i-cache-sets = <512>; 2909 d-cache-size = <65536>; 2910 d-cache-line-size = <64>; 2911 d-cache-sets = <256>; 2912 next-level-cache = <&l2c_0>; 2913 }; 2914 2915 cpu0_1: cpu@1 { 2916 compatible = "nvidia,tegra194-carmel"; 2917 device_type = "cpu"; 2918 reg = <0x001>; 2919 enable-method = "psci"; 2920 i-cache-size = <131072>; 2921 i-cache-line-size = <64>; 2922 i-cache-sets = <512>; 2923 d-cache-size = <65536>; 2924 d-cache-line-size = <64>; 2925 d-cache-sets = <256>; 2926 next-level-cache = <&l2c_0>; 2927 }; 2928 2929 cpu1_0: cpu@100 { 2930 compatible = "nvidia,tegra194-carmel"; 2931 device_type = "cpu"; 2932 reg = <0x100>; 2933 enable-method = "psci"; 2934 i-cache-size = <131072>; 2935 i-cache-line-size = <64>; 2936 i-cache-sets = <512>; 2937 d-cache-size = <65536>; 2938 d-cache-line-size = <64>; 2939 d-cache-sets = <256>; 2940 next-level-cache = <&l2c_1>; 2941 }; 2942 2943 cpu1_1: cpu@101 { 2944 compatible = "nvidia,tegra194-carmel"; 2945 device_type = "cpu"; 2946 reg = <0x101>; 2947 enable-method = "psci"; 2948 i-cache-size = <131072>; 2949 i-cache-line-size = <64>; 2950 i-cache-sets = <512>; 2951 d-cache-size = <65536>; 2952 d-cache-line-size = <64>; 2953 d-cache-sets = <256>; 2954 next-level-cache = <&l2c_1>; 2955 }; 2956 2957 cpu2_0: cpu@200 { 2958 compatible = "nvidia,tegra194-carmel"; 2959 device_type = "cpu"; 2960 reg = <0x200>; 2961 enable-method = "psci"; 2962 i-cache-size = <131072>; 2963 i-cache-line-size = <64>; 2964 i-cache-sets = <512>; 2965 d-cache-size = <65536>; 2966 d-cache-line-size = <64>; 2967 d-cache-sets = <256>; 2968 next-level-cache = <&l2c_2>; 2969 }; 2970 2971 cpu2_1: cpu@201 { 2972 compatible = "nvidia,tegra194-carmel"; 2973 device_type = "cpu"; 2974 reg = <0x201>; 2975 enable-method = "psci"; 2976 i-cache-size = <131072>; 2977 i-cache-line-size = <64>; 2978 i-cache-sets = <512>; 2979 d-cache-size = <65536>; 2980 d-cache-line-size = <64>; 2981 d-cache-sets = <256>; 2982 next-level-cache = <&l2c_2>; 2983 }; 2984 2985 cpu3_0: cpu@300 { 2986 compatible = "nvidia,tegra194-carmel"; 2987 device_type = "cpu"; 2988 reg = <0x300>; 2989 enable-method = "psci"; 2990 i-cache-size = <131072>; 2991 i-cache-line-size = <64>; 2992 i-cache-sets = <512>; 2993 d-cache-size = <65536>; 2994 d-cache-line-size = <64>; 2995 d-cache-sets = <256>; 2996 next-level-cache = <&l2c_3>; 2997 }; 2998 2999 cpu3_1: cpu@301 { 3000 compatible = "nvidia,tegra194-carmel"; 3001 device_type = "cpu"; 3002 reg = <0x301>; 3003 enable-method = "psci"; 3004 i-cache-size = <131072>; 3005 i-cache-line-size = <64>; 3006 i-cache-sets = <512>; 3007 d-cache-size = <65536>; 3008 d-cache-line-size = <64>; 3009 d-cache-sets = <256>; 3010 next-level-cache = <&l2c_3>; 3011 }; 3012 3013 cpu-map { 3014 cluster0 { 3015 core0 { 3016 cpu = <&cpu0_0>; 3017 }; 3018 3019 core1 { 3020 cpu = <&cpu0_1>; 3021 }; 3022 }; 3023 3024 cluster1 { 3025 core0 { 3026 cpu = <&cpu1_0>; 3027 }; 3028 3029 core1 { 3030 cpu = <&cpu1_1>; 3031 }; 3032 }; 3033 3034 cluster2 { 3035 core0 { 3036 cpu = <&cpu2_0>; 3037 }; 3038 3039 core1 { 3040 cpu = <&cpu2_1>; 3041 }; 3042 }; 3043 3044 cluster3 { 3045 core0 { 3046 cpu = <&cpu3_0>; 3047 }; 3048 3049 core1 { 3050 cpu = <&cpu3_1>; 3051 }; 3052 }; 3053 }; 3054 3055 l2c_0: l2-cache0 { 3056 compatible = "cache"; 3057 cache-unified; 3058 cache-size = <2097152>; 3059 cache-line-size = <64>; 3060 cache-sets = <2048>; 3061 cache-level = <2>; 3062 next-level-cache = <&l3c>; 3063 }; 3064 3065 l2c_1: l2-cache1 { 3066 compatible = "cache"; 3067 cache-unified; 3068 cache-size = <2097152>; 3069 cache-line-size = <64>; 3070 cache-sets = <2048>; 3071 cache-level = <2>; 3072 next-level-cache = <&l3c>; 3073 }; 3074 3075 l2c_2: l2-cache2 { 3076 compatible = "cache"; 3077 cache-unified; 3078 cache-size = <2097152>; 3079 cache-line-size = <64>; 3080 cache-sets = <2048>; 3081 cache-level = <2>; 3082 next-level-cache = <&l3c>; 3083 }; 3084 3085 l2c_3: l2-cache3 { 3086 compatible = "cache"; 3087 cache-unified; 3088 cache-size = <2097152>; 3089 cache-line-size = <64>; 3090 cache-sets = <2048>; 3091 cache-level = <2>; 3092 next-level-cache = <&l3c>; 3093 }; 3094 3095 l3c: l3-cache { 3096 compatible = "cache"; 3097 cache-unified; 3098 cache-size = <4194304>; 3099 cache-line-size = <64>; 3100 cache-level = <3>; 3101 cache-sets = <4096>; 3102 }; 3103 }; 3104 3105 pmu { 3106 compatible = "nvidia,carmel-pmu"; 3107 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 3115 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 3116 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 3117 }; 3118 3119 psci { 3120 compatible = "arm,psci-1.0"; 3121 status = "okay"; 3122 method = "smc"; 3123 }; 3124 3125 tcu: serial { 3126 compatible = "nvidia,tegra194-tcu"; 3127 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3128 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3129 mbox-names = "rx", "tx"; 3130 }; 3131 3132 sound { 3133 status = "disabled"; 3134 3135 clocks = <&bpmp TEGRA194_CLK_PLLA>, 3136 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3137 clock-names = "pll_a", "plla_out0"; 3138 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 3139 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 3140 <&bpmp TEGRA194_CLK_AUD_MCLK>; 3141 assigned-clock-parents = <0>, 3142 <&bpmp TEGRA194_CLK_PLLA>, 3143 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3144 /* 3145 * PLLA supports dynamic ramp. Below initial rate is chosen 3146 * for this to work and oscillate between base rates required 3147 * for 8x and 11.025x sample rate streams. 3148 */ 3149 assigned-clock-rates = <258000000>; 3150 }; 3151 3152 thermal-zones { 3153 cpu-thermal { 3154 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3155 status = "disabled"; 3156 }; 3157 3158 gpu-thermal { 3159 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3160 status = "disabled"; 3161 }; 3162 3163 aux-thermal { 3164 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3165 status = "disabled"; 3166 }; 3167 3168 pllx-thermal { 3169 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3170 status = "disabled"; 3171 }; 3172 3173 ao-thermal { 3174 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3175 status = "disabled"; 3176 }; 3177 3178 tj-thermal { 3179 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3180 status = "disabled"; 3181 }; 3182 }; 3183 3184 timer { 3185 compatible = "arm,armv8-timer"; 3186 interrupts = <GIC_PPI 13 3187 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3188 <GIC_PPI 14 3189 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3190 <GIC_PPI 11 3191 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3192 <GIC_PPI 10 3193 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3194 interrupt-parent = <&gic>; 3195 always-on; 3196 }; 3197}; 3198