1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x0 0x0 0x0 0x40000000>; 25 26 misc@100000 { 27 compatible = "nvidia,tegra194-misc"; 28 reg = <0x00100000 0xf000>, 29 <0x0010f000 0x1000>; 30 }; 31 32 gpio: gpio@2200000 { 33 compatible = "nvidia,tegra194-gpio"; 34 reg-names = "security", "gpio"; 35 reg = <0x2200000 0x10000>, 36 <0x2210000 0x10000>; 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85 #interrupt-cells = <2>; 86 interrupt-controller; 87 #gpio-cells = <2>; 88 gpio-controller; 89 }; 90 91 ethernet@2490000 { 92 compatible = "nvidia,tegra194-eqos", 93 "nvidia,tegra186-eqos", 94 "snps,dwc-qos-ethernet-4.10"; 95 reg = <0x02490000 0x10000>; 96 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 98 <&bpmp TEGRA194_CLK_EQOS_AXI>, 99 <&bpmp TEGRA194_CLK_EQOS_RX>, 100 <&bpmp TEGRA194_CLK_EQOS_TX>, 101 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 102 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 103 resets = <&bpmp TEGRA194_RESET_EQOS>; 104 reset-names = "eqos"; 105 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 106 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 107 interconnect-names = "dma-mem", "write"; 108 iommus = <&smmu TEGRA194_SID_EQOS>; 109 status = "disabled"; 110 111 snps,write-requests = <1>; 112 snps,read-requests = <3>; 113 snps,burst-map = <0x7>; 114 snps,txpbl = <16>; 115 snps,rxpbl = <8>; 116 }; 117 118 gpcdma: dma-controller@2600000 { 119 compatible = "nvidia,tegra194-gpcdma", 120 "nvidia,tegra186-gpcdma"; 121 reg = <0x2600000 0x210000>; 122 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 123 reset-names = "gpcdma"; 124 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 155 #dma-cells = <1>; 156 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 157 dma-coherent; 158 status = "okay"; 159 }; 160 161 aconnect@2900000 { 162 compatible = "nvidia,tegra194-aconnect", 163 "nvidia,tegra210-aconnect"; 164 clocks = <&bpmp TEGRA194_CLK_APE>, 165 <&bpmp TEGRA194_CLK_APB2APE>; 166 clock-names = "ape", "apb2ape"; 167 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 168 #address-cells = <1>; 169 #size-cells = <1>; 170 ranges = <0x02900000 0x02900000 0x200000>; 171 status = "disabled"; 172 173 adma: dma-controller@2930000 { 174 compatible = "nvidia,tegra194-adma", 175 "nvidia,tegra186-adma"; 176 reg = <0x02930000 0x20000>; 177 interrupt-parent = <&agic>; 178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 210 #dma-cells = <1>; 211 clocks = <&bpmp TEGRA194_CLK_AHUB>; 212 clock-names = "d_audio"; 213 status = "disabled"; 214 }; 215 216 agic: interrupt-controller@2a40000 { 217 compatible = "nvidia,tegra194-agic", 218 "nvidia,tegra210-agic"; 219 #interrupt-cells = <3>; 220 interrupt-controller; 221 reg = <0x02a41000 0x1000>, 222 <0x02a42000 0x2000>; 223 interrupts = <GIC_SPI 145 224 (GIC_CPU_MASK_SIMPLE(4) | 225 IRQ_TYPE_LEVEL_HIGH)>; 226 clocks = <&bpmp TEGRA194_CLK_APE>; 227 clock-names = "clk"; 228 status = "disabled"; 229 }; 230 231 tegra_ahub: ahub@2900800 { 232 compatible = "nvidia,tegra194-ahub", 233 "nvidia,tegra186-ahub"; 234 reg = <0x02900800 0x800>; 235 clocks = <&bpmp TEGRA194_CLK_AHUB>; 236 clock-names = "ahub"; 237 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 238 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 239 #address-cells = <1>; 240 #size-cells = <1>; 241 ranges = <0x02900800 0x02900800 0x11800>; 242 status = "disabled"; 243 244 tegra_admaif: admaif@290f000 { 245 compatible = "nvidia,tegra194-admaif", 246 "nvidia,tegra186-admaif"; 247 reg = <0x0290f000 0x1000>; 248 dmas = <&adma 1>, <&adma 1>, 249 <&adma 2>, <&adma 2>, 250 <&adma 3>, <&adma 3>, 251 <&adma 4>, <&adma 4>, 252 <&adma 5>, <&adma 5>, 253 <&adma 6>, <&adma 6>, 254 <&adma 7>, <&adma 7>, 255 <&adma 8>, <&adma 8>, 256 <&adma 9>, <&adma 9>, 257 <&adma 10>, <&adma 10>, 258 <&adma 11>, <&adma 11>, 259 <&adma 12>, <&adma 12>, 260 <&adma 13>, <&adma 13>, 261 <&adma 14>, <&adma 14>, 262 <&adma 15>, <&adma 15>, 263 <&adma 16>, <&adma 16>, 264 <&adma 17>, <&adma 17>, 265 <&adma 18>, <&adma 18>, 266 <&adma 19>, <&adma 19>, 267 <&adma 20>, <&adma 20>; 268 dma-names = "rx1", "tx1", 269 "rx2", "tx2", 270 "rx3", "tx3", 271 "rx4", "tx4", 272 "rx5", "tx5", 273 "rx6", "tx6", 274 "rx7", "tx7", 275 "rx8", "tx8", 276 "rx9", "tx9", 277 "rx10", "tx10", 278 "rx11", "tx11", 279 "rx12", "tx12", 280 "rx13", "tx13", 281 "rx14", "tx14", 282 "rx15", "tx15", 283 "rx16", "tx16", 284 "rx17", "tx17", 285 "rx18", "tx18", 286 "rx19", "tx19", 287 "rx20", "tx20"; 288 status = "disabled"; 289 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 290 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 291 interconnect-names = "dma-mem", "write"; 292 iommus = <&smmu TEGRA194_SID_APE>; 293 }; 294 295 tegra_i2s1: i2s@2901000 { 296 compatible = "nvidia,tegra194-i2s", 297 "nvidia,tegra210-i2s"; 298 reg = <0x2901000 0x100>; 299 clocks = <&bpmp TEGRA194_CLK_I2S1>, 300 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 301 clock-names = "i2s", "sync_input"; 302 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 303 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 304 assigned-clock-rates = <1536000>; 305 sound-name-prefix = "I2S1"; 306 status = "disabled"; 307 }; 308 309 tegra_i2s2: i2s@2901100 { 310 compatible = "nvidia,tegra194-i2s", 311 "nvidia,tegra210-i2s"; 312 reg = <0x2901100 0x100>; 313 clocks = <&bpmp TEGRA194_CLK_I2S2>, 314 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 315 clock-names = "i2s", "sync_input"; 316 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 317 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 318 assigned-clock-rates = <1536000>; 319 sound-name-prefix = "I2S2"; 320 status = "disabled"; 321 }; 322 323 tegra_i2s3: i2s@2901200 { 324 compatible = "nvidia,tegra194-i2s", 325 "nvidia,tegra210-i2s"; 326 reg = <0x2901200 0x100>; 327 clocks = <&bpmp TEGRA194_CLK_I2S3>, 328 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 329 clock-names = "i2s", "sync_input"; 330 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 331 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 332 assigned-clock-rates = <1536000>; 333 sound-name-prefix = "I2S3"; 334 status = "disabled"; 335 }; 336 337 tegra_i2s4: i2s@2901300 { 338 compatible = "nvidia,tegra194-i2s", 339 "nvidia,tegra210-i2s"; 340 reg = <0x2901300 0x100>; 341 clocks = <&bpmp TEGRA194_CLK_I2S4>, 342 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 343 clock-names = "i2s", "sync_input"; 344 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 345 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 346 assigned-clock-rates = <1536000>; 347 sound-name-prefix = "I2S4"; 348 status = "disabled"; 349 }; 350 351 tegra_i2s5: i2s@2901400 { 352 compatible = "nvidia,tegra194-i2s", 353 "nvidia,tegra210-i2s"; 354 reg = <0x2901400 0x100>; 355 clocks = <&bpmp TEGRA194_CLK_I2S5>, 356 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 357 clock-names = "i2s", "sync_input"; 358 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 359 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 360 assigned-clock-rates = <1536000>; 361 sound-name-prefix = "I2S5"; 362 status = "disabled"; 363 }; 364 365 tegra_i2s6: i2s@2901500 { 366 compatible = "nvidia,tegra194-i2s", 367 "nvidia,tegra210-i2s"; 368 reg = <0x2901500 0x100>; 369 clocks = <&bpmp TEGRA194_CLK_I2S6>, 370 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 371 clock-names = "i2s", "sync_input"; 372 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 373 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 374 assigned-clock-rates = <1536000>; 375 sound-name-prefix = "I2S6"; 376 status = "disabled"; 377 }; 378 379 tegra_dmic1: dmic@2904000 { 380 compatible = "nvidia,tegra194-dmic", 381 "nvidia,tegra210-dmic"; 382 reg = <0x2904000 0x100>; 383 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 384 clock-names = "dmic"; 385 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 386 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 387 assigned-clock-rates = <3072000>; 388 sound-name-prefix = "DMIC1"; 389 status = "disabled"; 390 }; 391 392 tegra_dmic2: dmic@2904100 { 393 compatible = "nvidia,tegra194-dmic", 394 "nvidia,tegra210-dmic"; 395 reg = <0x2904100 0x100>; 396 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 397 clock-names = "dmic"; 398 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 399 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 400 assigned-clock-rates = <3072000>; 401 sound-name-prefix = "DMIC2"; 402 status = "disabled"; 403 }; 404 405 tegra_dmic3: dmic@2904200 { 406 compatible = "nvidia,tegra194-dmic", 407 "nvidia,tegra210-dmic"; 408 reg = <0x2904200 0x100>; 409 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 410 clock-names = "dmic"; 411 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 412 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 413 assigned-clock-rates = <3072000>; 414 sound-name-prefix = "DMIC3"; 415 status = "disabled"; 416 }; 417 418 tegra_dmic4: dmic@2904300 { 419 compatible = "nvidia,tegra194-dmic", 420 "nvidia,tegra210-dmic"; 421 reg = <0x2904300 0x100>; 422 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 423 clock-names = "dmic"; 424 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 425 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 426 assigned-clock-rates = <3072000>; 427 sound-name-prefix = "DMIC4"; 428 status = "disabled"; 429 }; 430 431 tegra_dspk1: dspk@2905000 { 432 compatible = "nvidia,tegra194-dspk", 433 "nvidia,tegra186-dspk"; 434 reg = <0x2905000 0x100>; 435 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 436 clock-names = "dspk"; 437 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 438 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 439 assigned-clock-rates = <12288000>; 440 sound-name-prefix = "DSPK1"; 441 status = "disabled"; 442 }; 443 444 tegra_dspk2: dspk@2905100 { 445 compatible = "nvidia,tegra194-dspk", 446 "nvidia,tegra186-dspk"; 447 reg = <0x2905100 0x100>; 448 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 449 clock-names = "dspk"; 450 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 451 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 452 assigned-clock-rates = <12288000>; 453 sound-name-prefix = "DSPK2"; 454 status = "disabled"; 455 }; 456 457 tegra_sfc1: sfc@2902000 { 458 compatible = "nvidia,tegra194-sfc", 459 "nvidia,tegra210-sfc"; 460 reg = <0x2902000 0x200>; 461 sound-name-prefix = "SFC1"; 462 status = "disabled"; 463 }; 464 465 tegra_sfc2: sfc@2902200 { 466 compatible = "nvidia,tegra194-sfc", 467 "nvidia,tegra210-sfc"; 468 reg = <0x2902200 0x200>; 469 sound-name-prefix = "SFC2"; 470 status = "disabled"; 471 }; 472 473 tegra_sfc3: sfc@2902400 { 474 compatible = "nvidia,tegra194-sfc", 475 "nvidia,tegra210-sfc"; 476 reg = <0x2902400 0x200>; 477 sound-name-prefix = "SFC3"; 478 status = "disabled"; 479 }; 480 481 tegra_sfc4: sfc@2902600 { 482 compatible = "nvidia,tegra194-sfc", 483 "nvidia,tegra210-sfc"; 484 reg = <0x2902600 0x200>; 485 sound-name-prefix = "SFC4"; 486 status = "disabled"; 487 }; 488 489 tegra_mvc1: mvc@290a000 { 490 compatible = "nvidia,tegra194-mvc", 491 "nvidia,tegra210-mvc"; 492 reg = <0x290a000 0x200>; 493 sound-name-prefix = "MVC1"; 494 status = "disabled"; 495 }; 496 497 tegra_mvc2: mvc@290a200 { 498 compatible = "nvidia,tegra194-mvc", 499 "nvidia,tegra210-mvc"; 500 reg = <0x290a200 0x200>; 501 sound-name-prefix = "MVC2"; 502 status = "disabled"; 503 }; 504 505 tegra_amx1: amx@2903000 { 506 compatible = "nvidia,tegra194-amx"; 507 reg = <0x2903000 0x100>; 508 sound-name-prefix = "AMX1"; 509 status = "disabled"; 510 }; 511 512 tegra_amx2: amx@2903100 { 513 compatible = "nvidia,tegra194-amx"; 514 reg = <0x2903100 0x100>; 515 sound-name-prefix = "AMX2"; 516 status = "disabled"; 517 }; 518 519 tegra_amx3: amx@2903200 { 520 compatible = "nvidia,tegra194-amx"; 521 reg = <0x2903200 0x100>; 522 sound-name-prefix = "AMX3"; 523 status = "disabled"; 524 }; 525 526 tegra_amx4: amx@2903300 { 527 compatible = "nvidia,tegra194-amx"; 528 reg = <0x2903300 0x100>; 529 sound-name-prefix = "AMX4"; 530 status = "disabled"; 531 }; 532 533 tegra_adx1: adx@2903800 { 534 compatible = "nvidia,tegra194-adx", 535 "nvidia,tegra210-adx"; 536 reg = <0x2903800 0x100>; 537 sound-name-prefix = "ADX1"; 538 status = "disabled"; 539 }; 540 541 tegra_adx2: adx@2903900 { 542 compatible = "nvidia,tegra194-adx", 543 "nvidia,tegra210-adx"; 544 reg = <0x2903900 0x100>; 545 sound-name-prefix = "ADX2"; 546 status = "disabled"; 547 }; 548 549 tegra_adx3: adx@2903a00 { 550 compatible = "nvidia,tegra194-adx", 551 "nvidia,tegra210-adx"; 552 reg = <0x2903a00 0x100>; 553 sound-name-prefix = "ADX3"; 554 status = "disabled"; 555 }; 556 557 tegra_adx4: adx@2903b00 { 558 compatible = "nvidia,tegra194-adx", 559 "nvidia,tegra210-adx"; 560 reg = <0x2903b00 0x100>; 561 sound-name-prefix = "ADX4"; 562 status = "disabled"; 563 }; 564 565 tegra_ope1: processing-engine@2908000 { 566 compatible = "nvidia,tegra194-ope", 567 "nvidia,tegra210-ope"; 568 reg = <0x2908000 0x100>; 569 #address-cells = <1>; 570 #size-cells = <1>; 571 ranges; 572 sound-name-prefix = "OPE1"; 573 status = "disabled"; 574 575 equalizer@2908100 { 576 compatible = "nvidia,tegra194-peq", 577 "nvidia,tegra210-peq"; 578 reg = <0x2908100 0x100>; 579 }; 580 581 dynamic-range-compressor@2908200 { 582 compatible = "nvidia,tegra194-mbdrc", 583 "nvidia,tegra210-mbdrc"; 584 reg = <0x2908200 0x200>; 585 }; 586 }; 587 588 tegra_amixer: amixer@290bb00 { 589 compatible = "nvidia,tegra194-amixer", 590 "nvidia,tegra210-amixer"; 591 reg = <0x290bb00 0x800>; 592 sound-name-prefix = "MIXER1"; 593 status = "disabled"; 594 }; 595 596 tegra_asrc: asrc@2910000 { 597 compatible = "nvidia,tegra194-asrc", 598 "nvidia,tegra186-asrc"; 599 reg = <0x2910000 0x2000>; 600 sound-name-prefix = "ASRC1"; 601 status = "disabled"; 602 }; 603 }; 604 }; 605 606 pinmux: pinmux@2430000 { 607 compatible = "nvidia,tegra194-pinmux"; 608 reg = <0x2430000 0x17000>, 609 <0xc300000 0x4000>; 610 611 status = "okay"; 612 613 pex_rst_c5_out_state: pex_rst_c5_out { 614 pex_rst { 615 nvidia,pins = "pex_l5_rst_n_pgg1"; 616 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 617 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 618 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 619 nvidia,tristate = <TEGRA_PIN_DISABLE>; 620 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 621 }; 622 }; 623 624 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 625 clkreq { 626 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 627 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 628 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 629 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 630 nvidia,tristate = <TEGRA_PIN_DISABLE>; 631 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 632 }; 633 }; 634 }; 635 636 mc: memory-controller@2c00000 { 637 compatible = "nvidia,tegra194-mc"; 638 reg = <0x02c00000 0x10000>, /* MC-SID */ 639 <0x02c10000 0x10000>, /* MC Broadcast*/ 640 <0x02c20000 0x10000>, /* MC0 */ 641 <0x02c30000 0x10000>, /* MC1 */ 642 <0x02c40000 0x10000>, /* MC2 */ 643 <0x02c50000 0x10000>, /* MC3 */ 644 <0x02b80000 0x10000>, /* MC4 */ 645 <0x02b90000 0x10000>, /* MC5 */ 646 <0x02ba0000 0x10000>, /* MC6 */ 647 <0x02bb0000 0x10000>, /* MC7 */ 648 <0x01700000 0x10000>, /* MC8 */ 649 <0x01710000 0x10000>, /* MC9 */ 650 <0x01720000 0x10000>, /* MC10 */ 651 <0x01730000 0x10000>, /* MC11 */ 652 <0x01740000 0x10000>, /* MC12 */ 653 <0x01750000 0x10000>, /* MC13 */ 654 <0x01760000 0x10000>, /* MC14 */ 655 <0x01770000 0x10000>; /* MC15 */ 656 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 657 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 658 "ch11", "ch12", "ch13", "ch14", "ch15"; 659 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 660 #interconnect-cells = <1>; 661 status = "disabled"; 662 663 #address-cells = <2>; 664 #size-cells = <2>; 665 666 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 667 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 668 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 669 670 /* 671 * Bit 39 of addresses passing through the memory 672 * controller selects the XBAR format used when memory 673 * is accessed. This is used to transparently access 674 * memory in the XBAR format used by the discrete GPU 675 * (bit 39 set) or Tegra (bit 39 clear). 676 * 677 * As a consequence, the operating system must ensure 678 * that bit 39 is never used implicitly, for example 679 * via an I/O virtual address mapping of an IOMMU. If 680 * devices require access to the XBAR switch, their 681 * drivers must set this bit explicitly. 682 * 683 * Limit the DMA range for memory clients to [38:0]. 684 */ 685 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 686 687 emc: external-memory-controller@2c60000 { 688 compatible = "nvidia,tegra194-emc"; 689 reg = <0x0 0x02c60000 0x0 0x90000>, 690 <0x0 0x01780000 0x0 0x80000>; 691 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&bpmp TEGRA194_CLK_EMC>; 693 clock-names = "emc"; 694 695 #interconnect-cells = <0>; 696 697 nvidia,bpmp = <&bpmp>; 698 }; 699 }; 700 701 uarta: serial@3100000 { 702 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 703 reg = <0x03100000 0x40>; 704 reg-shift = <2>; 705 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&bpmp TEGRA194_CLK_UARTA>; 707 clock-names = "serial"; 708 resets = <&bpmp TEGRA194_RESET_UARTA>; 709 reset-names = "serial"; 710 status = "disabled"; 711 }; 712 713 uartb: serial@3110000 { 714 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 715 reg = <0x03110000 0x40>; 716 reg-shift = <2>; 717 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&bpmp TEGRA194_CLK_UARTB>; 719 clock-names = "serial"; 720 resets = <&bpmp TEGRA194_RESET_UARTB>; 721 reset-names = "serial"; 722 status = "disabled"; 723 }; 724 725 uartd: serial@3130000 { 726 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 727 reg = <0x03130000 0x40>; 728 reg-shift = <2>; 729 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&bpmp TEGRA194_CLK_UARTD>; 731 clock-names = "serial"; 732 resets = <&bpmp TEGRA194_RESET_UARTD>; 733 reset-names = "serial"; 734 status = "disabled"; 735 }; 736 737 uarte: serial@3140000 { 738 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 739 reg = <0x03140000 0x40>; 740 reg-shift = <2>; 741 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&bpmp TEGRA194_CLK_UARTE>; 743 clock-names = "serial"; 744 resets = <&bpmp TEGRA194_RESET_UARTE>; 745 reset-names = "serial"; 746 status = "disabled"; 747 }; 748 749 uartf: serial@3150000 { 750 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 751 reg = <0x03150000 0x40>; 752 reg-shift = <2>; 753 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&bpmp TEGRA194_CLK_UARTF>; 755 clock-names = "serial"; 756 resets = <&bpmp TEGRA194_RESET_UARTF>; 757 reset-names = "serial"; 758 status = "disabled"; 759 }; 760 761 gen1_i2c: i2c@3160000 { 762 compatible = "nvidia,tegra194-i2c"; 763 reg = <0x03160000 0x10000>; 764 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 765 #address-cells = <1>; 766 #size-cells = <0>; 767 clocks = <&bpmp TEGRA194_CLK_I2C1>; 768 clock-names = "div-clk"; 769 resets = <&bpmp TEGRA194_RESET_I2C1>; 770 reset-names = "i2c"; 771 status = "disabled"; 772 }; 773 774 uarth: serial@3170000 { 775 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 776 reg = <0x03170000 0x40>; 777 reg-shift = <2>; 778 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&bpmp TEGRA194_CLK_UARTH>; 780 clock-names = "serial"; 781 resets = <&bpmp TEGRA194_RESET_UARTH>; 782 reset-names = "serial"; 783 status = "disabled"; 784 }; 785 786 cam_i2c: i2c@3180000 { 787 compatible = "nvidia,tegra194-i2c"; 788 reg = <0x03180000 0x10000>; 789 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 clocks = <&bpmp TEGRA194_CLK_I2C3>; 793 clock-names = "div-clk"; 794 resets = <&bpmp TEGRA194_RESET_I2C3>; 795 reset-names = "i2c"; 796 status = "disabled"; 797 }; 798 799 /* shares pads with dpaux1 */ 800 dp_aux_ch1_i2c: i2c@3190000 { 801 compatible = "nvidia,tegra194-i2c"; 802 reg = <0x03190000 0x10000>; 803 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 clocks = <&bpmp TEGRA194_CLK_I2C4>; 807 clock-names = "div-clk"; 808 resets = <&bpmp TEGRA194_RESET_I2C4>; 809 reset-names = "i2c"; 810 pinctrl-0 = <&state_dpaux1_i2c>; 811 pinctrl-1 = <&state_dpaux1_off>; 812 pinctrl-names = "default", "idle"; 813 status = "disabled"; 814 }; 815 816 /* shares pads with dpaux0 */ 817 dp_aux_ch0_i2c: i2c@31b0000 { 818 compatible = "nvidia,tegra194-i2c"; 819 reg = <0x031b0000 0x10000>; 820 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 clocks = <&bpmp TEGRA194_CLK_I2C6>; 824 clock-names = "div-clk"; 825 resets = <&bpmp TEGRA194_RESET_I2C6>; 826 reset-names = "i2c"; 827 pinctrl-0 = <&state_dpaux0_i2c>; 828 pinctrl-1 = <&state_dpaux0_off>; 829 pinctrl-names = "default", "idle"; 830 status = "disabled"; 831 }; 832 833 /* shares pads with dpaux2 */ 834 dp_aux_ch2_i2c: i2c@31c0000 { 835 compatible = "nvidia,tegra194-i2c"; 836 reg = <0x031c0000 0x10000>; 837 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 clocks = <&bpmp TEGRA194_CLK_I2C7>; 841 clock-names = "div-clk"; 842 resets = <&bpmp TEGRA194_RESET_I2C7>; 843 reset-names = "i2c"; 844 pinctrl-0 = <&state_dpaux2_i2c>; 845 pinctrl-1 = <&state_dpaux2_off>; 846 pinctrl-names = "default", "idle"; 847 status = "disabled"; 848 }; 849 850 /* shares pads with dpaux3 */ 851 dp_aux_ch3_i2c: i2c@31e0000 { 852 compatible = "nvidia,tegra194-i2c"; 853 reg = <0x031e0000 0x10000>; 854 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 clocks = <&bpmp TEGRA194_CLK_I2C9>; 858 clock-names = "div-clk"; 859 resets = <&bpmp TEGRA194_RESET_I2C9>; 860 reset-names = "i2c"; 861 pinctrl-0 = <&state_dpaux3_i2c>; 862 pinctrl-1 = <&state_dpaux3_off>; 863 pinctrl-names = "default", "idle"; 864 status = "disabled"; 865 }; 866 867 spi@3270000 { 868 compatible = "nvidia,tegra194-qspi"; 869 reg = <0x3270000 0x1000>; 870 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 874 <&bpmp TEGRA194_CLK_QSPI0_PM>; 875 clock-names = "qspi", "qspi_out"; 876 resets = <&bpmp TEGRA194_RESET_QSPI0>; 877 reset-names = "qspi"; 878 status = "disabled"; 879 }; 880 881 spi@3300000 { 882 compatible = "nvidia,tegra194-qspi"; 883 reg = <0x3300000 0x1000>; 884 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 888 <&bpmp TEGRA194_CLK_QSPI1_PM>; 889 clock-names = "qspi", "qspi_out"; 890 resets = <&bpmp TEGRA194_RESET_QSPI1>; 891 reset-names = "qspi"; 892 status = "disabled"; 893 }; 894 895 pwm1: pwm@3280000 { 896 compatible = "nvidia,tegra194-pwm", 897 "nvidia,tegra186-pwm"; 898 reg = <0x3280000 0x10000>; 899 clocks = <&bpmp TEGRA194_CLK_PWM1>; 900 clock-names = "pwm"; 901 resets = <&bpmp TEGRA194_RESET_PWM1>; 902 reset-names = "pwm"; 903 status = "disabled"; 904 #pwm-cells = <2>; 905 }; 906 907 pwm2: pwm@3290000 { 908 compatible = "nvidia,tegra194-pwm", 909 "nvidia,tegra186-pwm"; 910 reg = <0x3290000 0x10000>; 911 clocks = <&bpmp TEGRA194_CLK_PWM2>; 912 clock-names = "pwm"; 913 resets = <&bpmp TEGRA194_RESET_PWM2>; 914 reset-names = "pwm"; 915 status = "disabled"; 916 #pwm-cells = <2>; 917 }; 918 919 pwm3: pwm@32a0000 { 920 compatible = "nvidia,tegra194-pwm", 921 "nvidia,tegra186-pwm"; 922 reg = <0x32a0000 0x10000>; 923 clocks = <&bpmp TEGRA194_CLK_PWM3>; 924 clock-names = "pwm"; 925 resets = <&bpmp TEGRA194_RESET_PWM3>; 926 reset-names = "pwm"; 927 status = "disabled"; 928 #pwm-cells = <2>; 929 }; 930 931 pwm5: pwm@32c0000 { 932 compatible = "nvidia,tegra194-pwm", 933 "nvidia,tegra186-pwm"; 934 reg = <0x32c0000 0x10000>; 935 clocks = <&bpmp TEGRA194_CLK_PWM5>; 936 clock-names = "pwm"; 937 resets = <&bpmp TEGRA194_RESET_PWM5>; 938 reset-names = "pwm"; 939 status = "disabled"; 940 #pwm-cells = <2>; 941 }; 942 943 pwm6: pwm@32d0000 { 944 compatible = "nvidia,tegra194-pwm", 945 "nvidia,tegra186-pwm"; 946 reg = <0x32d0000 0x10000>; 947 clocks = <&bpmp TEGRA194_CLK_PWM6>; 948 clock-names = "pwm"; 949 resets = <&bpmp TEGRA194_RESET_PWM6>; 950 reset-names = "pwm"; 951 status = "disabled"; 952 #pwm-cells = <2>; 953 }; 954 955 pwm7: pwm@32e0000 { 956 compatible = "nvidia,tegra194-pwm", 957 "nvidia,tegra186-pwm"; 958 reg = <0x32e0000 0x10000>; 959 clocks = <&bpmp TEGRA194_CLK_PWM7>; 960 clock-names = "pwm"; 961 resets = <&bpmp TEGRA194_RESET_PWM7>; 962 reset-names = "pwm"; 963 status = "disabled"; 964 #pwm-cells = <2>; 965 }; 966 967 pwm8: pwm@32f0000 { 968 compatible = "nvidia,tegra194-pwm", 969 "nvidia,tegra186-pwm"; 970 reg = <0x32f0000 0x10000>; 971 clocks = <&bpmp TEGRA194_CLK_PWM8>; 972 clock-names = "pwm"; 973 resets = <&bpmp TEGRA194_RESET_PWM8>; 974 reset-names = "pwm"; 975 status = "disabled"; 976 #pwm-cells = <2>; 977 }; 978 979 sdmmc1: mmc@3400000 { 980 compatible = "nvidia,tegra194-sdhci"; 981 reg = <0x03400000 0x10000>; 982 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 984 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 985 clock-names = "sdhci", "tmclk"; 986 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 987 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 988 assigned-clock-parents = 989 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 990 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 991 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 992 reset-names = "sdhci"; 993 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 994 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 995 interconnect-names = "dma-mem", "write"; 996 iommus = <&smmu TEGRA194_SID_SDMMC1>; 997 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 998 pinctrl-0 = <&sdmmc1_3v3>; 999 pinctrl-1 = <&sdmmc1_1v8>; 1000 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 1001 <0x07>; 1002 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1003 <0x07>; 1004 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1005 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1006 <0x07>; 1007 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1008 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1009 nvidia,default-tap = <0x9>; 1010 nvidia,default-trim = <0x5>; 1011 sd-uhs-sdr25; 1012 sd-uhs-sdr50; 1013 sd-uhs-ddr50; 1014 sd-uhs-sdr104; 1015 status = "disabled"; 1016 }; 1017 1018 sdmmc3: mmc@3440000 { 1019 compatible = "nvidia,tegra194-sdhci"; 1020 reg = <0x03440000 0x10000>; 1021 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1023 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1024 clock-names = "sdhci", "tmclk"; 1025 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1026 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1027 assigned-clock-parents = 1028 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1029 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1030 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1031 reset-names = "sdhci"; 1032 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1033 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1034 interconnect-names = "dma-mem", "write"; 1035 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1036 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1037 pinctrl-0 = <&sdmmc3_3v3>; 1038 pinctrl-1 = <&sdmmc3_1v8>; 1039 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1040 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1041 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1042 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1043 <0x07>; 1044 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1045 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1046 <0x07>; 1047 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1048 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1049 nvidia,default-tap = <0x9>; 1050 nvidia,default-trim = <0x5>; 1051 sd-uhs-sdr25; 1052 sd-uhs-sdr50; 1053 sd-uhs-ddr50; 1054 sd-uhs-sdr104; 1055 status = "disabled"; 1056 }; 1057 1058 sdmmc4: mmc@3460000 { 1059 compatible = "nvidia,tegra194-sdhci"; 1060 reg = <0x03460000 0x10000>; 1061 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1063 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1064 clock-names = "sdhci", "tmclk"; 1065 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1066 <&bpmp TEGRA194_CLK_PLLC4>; 1067 assigned-clock-parents = 1068 <&bpmp TEGRA194_CLK_PLLC4>; 1069 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1070 reset-names = "sdhci"; 1071 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1072 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1073 interconnect-names = "dma-mem", "write"; 1074 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1075 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1076 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1077 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1078 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1079 <0x0a>; 1080 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1081 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1082 <0x0a>; 1083 nvidia,default-tap = <0x8>; 1084 nvidia,default-trim = <0x14>; 1085 nvidia,dqs-trim = <40>; 1086 cap-mmc-highspeed; 1087 mmc-ddr-1_8v; 1088 mmc-hs200-1_8v; 1089 mmc-hs400-1_8v; 1090 mmc-hs400-enhanced-strobe; 1091 supports-cqe; 1092 status = "disabled"; 1093 }; 1094 1095 hda@3510000 { 1096 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 1097 reg = <0x3510000 0x10000>; 1098 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&bpmp TEGRA194_CLK_HDA>, 1100 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1101 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1102 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1103 resets = <&bpmp TEGRA194_RESET_HDA>, 1104 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1105 reset-names = "hda", "hda2hdmi"; 1106 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1107 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1108 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1109 interconnect-names = "dma-mem", "write"; 1110 iommus = <&smmu TEGRA194_SID_HDA>; 1111 status = "disabled"; 1112 }; 1113 1114 xusb_padctl: padctl@3520000 { 1115 compatible = "nvidia,tegra194-xusb-padctl"; 1116 reg = <0x03520000 0x1000>, 1117 <0x03540000 0x1000>; 1118 reg-names = "padctl", "ao"; 1119 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1120 1121 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1122 reset-names = "padctl"; 1123 1124 status = "disabled"; 1125 1126 pads { 1127 usb2 { 1128 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1129 clock-names = "trk"; 1130 1131 lanes { 1132 usb2-0 { 1133 nvidia,function = "xusb"; 1134 status = "disabled"; 1135 #phy-cells = <0>; 1136 }; 1137 1138 usb2-1 { 1139 nvidia,function = "xusb"; 1140 status = "disabled"; 1141 #phy-cells = <0>; 1142 }; 1143 1144 usb2-2 { 1145 nvidia,function = "xusb"; 1146 status = "disabled"; 1147 #phy-cells = <0>; 1148 }; 1149 1150 usb2-3 { 1151 nvidia,function = "xusb"; 1152 status = "disabled"; 1153 #phy-cells = <0>; 1154 }; 1155 }; 1156 }; 1157 1158 usb3 { 1159 lanes { 1160 usb3-0 { 1161 nvidia,function = "xusb"; 1162 status = "disabled"; 1163 #phy-cells = <0>; 1164 }; 1165 1166 usb3-1 { 1167 nvidia,function = "xusb"; 1168 status = "disabled"; 1169 #phy-cells = <0>; 1170 }; 1171 1172 usb3-2 { 1173 nvidia,function = "xusb"; 1174 status = "disabled"; 1175 #phy-cells = <0>; 1176 }; 1177 1178 usb3-3 { 1179 nvidia,function = "xusb"; 1180 status = "disabled"; 1181 #phy-cells = <0>; 1182 }; 1183 }; 1184 }; 1185 }; 1186 1187 ports { 1188 usb2-0 { 1189 status = "disabled"; 1190 }; 1191 1192 usb2-1 { 1193 status = "disabled"; 1194 }; 1195 1196 usb2-2 { 1197 status = "disabled"; 1198 }; 1199 1200 usb2-3 { 1201 status = "disabled"; 1202 }; 1203 1204 usb3-0 { 1205 status = "disabled"; 1206 }; 1207 1208 usb3-1 { 1209 status = "disabled"; 1210 }; 1211 1212 usb3-2 { 1213 status = "disabled"; 1214 }; 1215 1216 usb3-3 { 1217 status = "disabled"; 1218 }; 1219 }; 1220 }; 1221 1222 usb@3550000 { 1223 compatible = "nvidia,tegra194-xudc"; 1224 reg = <0x03550000 0x8000>, 1225 <0x03558000 0x1000>; 1226 reg-names = "base", "fpci"; 1227 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1229 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1230 <&bpmp TEGRA194_CLK_XUSB_SS>, 1231 <&bpmp TEGRA194_CLK_XUSB_FS>; 1232 clock-names = "dev", "ss", "ss_src", "fs_src"; 1233 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1234 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1235 interconnect-names = "dma-mem", "write"; 1236 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1237 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1238 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1239 power-domain-names = "dev", "ss"; 1240 nvidia,xusb-padctl = <&xusb_padctl>; 1241 status = "disabled"; 1242 }; 1243 1244 usb@3610000 { 1245 compatible = "nvidia,tegra194-xusb"; 1246 reg = <0x03610000 0x40000>, 1247 <0x03600000 0x10000>; 1248 reg-names = "hcd", "fpci"; 1249 1250 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1252 1253 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1254 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1255 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1256 <&bpmp TEGRA194_CLK_XUSB_SS>, 1257 <&bpmp TEGRA194_CLK_CLK_M>, 1258 <&bpmp TEGRA194_CLK_XUSB_FS>, 1259 <&bpmp TEGRA194_CLK_UTMIPLL>, 1260 <&bpmp TEGRA194_CLK_CLK_M>, 1261 <&bpmp TEGRA194_CLK_PLLE>; 1262 clock-names = "xusb_host", "xusb_falcon_src", 1263 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1264 "xusb_fs_src", "pll_u_480m", "clk_m", 1265 "pll_e"; 1266 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1267 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1268 interconnect-names = "dma-mem", "write"; 1269 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1270 1271 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1272 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1273 power-domain-names = "xusb_host", "xusb_ss"; 1274 1275 nvidia,xusb-padctl = <&xusb_padctl>; 1276 status = "disabled"; 1277 }; 1278 1279 fuse@3820000 { 1280 compatible = "nvidia,tegra194-efuse"; 1281 reg = <0x03820000 0x10000>; 1282 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1283 clock-names = "fuse"; 1284 }; 1285 1286 gic: interrupt-controller@3881000 { 1287 compatible = "arm,gic-400"; 1288 #interrupt-cells = <3>; 1289 interrupt-controller; 1290 reg = <0x03881000 0x1000>, 1291 <0x03882000 0x2000>, 1292 <0x03884000 0x2000>, 1293 <0x03886000 0x2000>; 1294 interrupts = <GIC_PPI 9 1295 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1296 interrupt-parent = <&gic>; 1297 }; 1298 1299 cec@3960000 { 1300 compatible = "nvidia,tegra194-cec"; 1301 reg = <0x03960000 0x10000>; 1302 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&bpmp TEGRA194_CLK_CEC>; 1304 clock-names = "cec"; 1305 status = "disabled"; 1306 }; 1307 1308 hsp_top0: hsp@3c00000 { 1309 compatible = "nvidia,tegra194-hsp"; 1310 reg = <0x03c00000 0xa0000>; 1311 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1313 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1319 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1320 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1321 "shared3", "shared4", "shared5", "shared6", 1322 "shared7"; 1323 #mbox-cells = <2>; 1324 }; 1325 1326 p2u_hsio_0: phy@3e10000 { 1327 compatible = "nvidia,tegra194-p2u"; 1328 reg = <0x03e10000 0x10000>; 1329 reg-names = "ctl"; 1330 1331 #phy-cells = <0>; 1332 }; 1333 1334 p2u_hsio_1: phy@3e20000 { 1335 compatible = "nvidia,tegra194-p2u"; 1336 reg = <0x03e20000 0x10000>; 1337 reg-names = "ctl"; 1338 1339 #phy-cells = <0>; 1340 }; 1341 1342 p2u_hsio_2: phy@3e30000 { 1343 compatible = "nvidia,tegra194-p2u"; 1344 reg = <0x03e30000 0x10000>; 1345 reg-names = "ctl"; 1346 1347 #phy-cells = <0>; 1348 }; 1349 1350 p2u_hsio_3: phy@3e40000 { 1351 compatible = "nvidia,tegra194-p2u"; 1352 reg = <0x03e40000 0x10000>; 1353 reg-names = "ctl"; 1354 1355 #phy-cells = <0>; 1356 }; 1357 1358 p2u_hsio_4: phy@3e50000 { 1359 compatible = "nvidia,tegra194-p2u"; 1360 reg = <0x03e50000 0x10000>; 1361 reg-names = "ctl"; 1362 1363 #phy-cells = <0>; 1364 }; 1365 1366 p2u_hsio_5: phy@3e60000 { 1367 compatible = "nvidia,tegra194-p2u"; 1368 reg = <0x03e60000 0x10000>; 1369 reg-names = "ctl"; 1370 1371 #phy-cells = <0>; 1372 }; 1373 1374 p2u_hsio_6: phy@3e70000 { 1375 compatible = "nvidia,tegra194-p2u"; 1376 reg = <0x03e70000 0x10000>; 1377 reg-names = "ctl"; 1378 1379 #phy-cells = <0>; 1380 }; 1381 1382 p2u_hsio_7: phy@3e80000 { 1383 compatible = "nvidia,tegra194-p2u"; 1384 reg = <0x03e80000 0x10000>; 1385 reg-names = "ctl"; 1386 1387 #phy-cells = <0>; 1388 }; 1389 1390 p2u_hsio_8: phy@3e90000 { 1391 compatible = "nvidia,tegra194-p2u"; 1392 reg = <0x03e90000 0x10000>; 1393 reg-names = "ctl"; 1394 1395 #phy-cells = <0>; 1396 }; 1397 1398 p2u_hsio_9: phy@3ea0000 { 1399 compatible = "nvidia,tegra194-p2u"; 1400 reg = <0x03ea0000 0x10000>; 1401 reg-names = "ctl"; 1402 1403 #phy-cells = <0>; 1404 }; 1405 1406 p2u_nvhs_0: phy@3eb0000 { 1407 compatible = "nvidia,tegra194-p2u"; 1408 reg = <0x03eb0000 0x10000>; 1409 reg-names = "ctl"; 1410 1411 #phy-cells = <0>; 1412 }; 1413 1414 p2u_nvhs_1: phy@3ec0000 { 1415 compatible = "nvidia,tegra194-p2u"; 1416 reg = <0x03ec0000 0x10000>; 1417 reg-names = "ctl"; 1418 1419 #phy-cells = <0>; 1420 }; 1421 1422 p2u_nvhs_2: phy@3ed0000 { 1423 compatible = "nvidia,tegra194-p2u"; 1424 reg = <0x03ed0000 0x10000>; 1425 reg-names = "ctl"; 1426 1427 #phy-cells = <0>; 1428 }; 1429 1430 p2u_nvhs_3: phy@3ee0000 { 1431 compatible = "nvidia,tegra194-p2u"; 1432 reg = <0x03ee0000 0x10000>; 1433 reg-names = "ctl"; 1434 1435 #phy-cells = <0>; 1436 }; 1437 1438 p2u_nvhs_4: phy@3ef0000 { 1439 compatible = "nvidia,tegra194-p2u"; 1440 reg = <0x03ef0000 0x10000>; 1441 reg-names = "ctl"; 1442 1443 #phy-cells = <0>; 1444 }; 1445 1446 p2u_nvhs_5: phy@3f00000 { 1447 compatible = "nvidia,tegra194-p2u"; 1448 reg = <0x03f00000 0x10000>; 1449 reg-names = "ctl"; 1450 1451 #phy-cells = <0>; 1452 }; 1453 1454 p2u_nvhs_6: phy@3f10000 { 1455 compatible = "nvidia,tegra194-p2u"; 1456 reg = <0x03f10000 0x10000>; 1457 reg-names = "ctl"; 1458 1459 #phy-cells = <0>; 1460 }; 1461 1462 p2u_nvhs_7: phy@3f20000 { 1463 compatible = "nvidia,tegra194-p2u"; 1464 reg = <0x03f20000 0x10000>; 1465 reg-names = "ctl"; 1466 1467 #phy-cells = <0>; 1468 }; 1469 1470 p2u_hsio_10: phy@3f30000 { 1471 compatible = "nvidia,tegra194-p2u"; 1472 reg = <0x03f30000 0x10000>; 1473 reg-names = "ctl"; 1474 1475 #phy-cells = <0>; 1476 }; 1477 1478 p2u_hsio_11: phy@3f40000 { 1479 compatible = "nvidia,tegra194-p2u"; 1480 reg = <0x03f40000 0x10000>; 1481 reg-names = "ctl"; 1482 1483 #phy-cells = <0>; 1484 }; 1485 1486 hsp_aon: hsp@c150000 { 1487 compatible = "nvidia,tegra194-hsp"; 1488 reg = <0x0c150000 0x90000>; 1489 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1493 /* 1494 * Shared interrupt 0 is routed only to AON/SPE, so 1495 * we only have 4 shared interrupts for the CCPLEX. 1496 */ 1497 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1498 #mbox-cells = <2>; 1499 }; 1500 1501 gen2_i2c: i2c@c240000 { 1502 compatible = "nvidia,tegra194-i2c"; 1503 reg = <0x0c240000 0x10000>; 1504 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1508 clock-names = "div-clk"; 1509 resets = <&bpmp TEGRA194_RESET_I2C2>; 1510 reset-names = "i2c"; 1511 status = "disabled"; 1512 }; 1513 1514 gen8_i2c: i2c@c250000 { 1515 compatible = "nvidia,tegra194-i2c"; 1516 reg = <0x0c250000 0x10000>; 1517 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1518 #address-cells = <1>; 1519 #size-cells = <0>; 1520 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1521 clock-names = "div-clk"; 1522 resets = <&bpmp TEGRA194_RESET_I2C8>; 1523 reset-names = "i2c"; 1524 status = "disabled"; 1525 }; 1526 1527 uartc: serial@c280000 { 1528 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1529 reg = <0x0c280000 0x40>; 1530 reg-shift = <2>; 1531 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1532 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1533 clock-names = "serial"; 1534 resets = <&bpmp TEGRA194_RESET_UARTC>; 1535 reset-names = "serial"; 1536 status = "disabled"; 1537 }; 1538 1539 uartg: serial@c290000 { 1540 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1541 reg = <0x0c290000 0x40>; 1542 reg-shift = <2>; 1543 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1544 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1545 clock-names = "serial"; 1546 resets = <&bpmp TEGRA194_RESET_UARTG>; 1547 reset-names = "serial"; 1548 status = "disabled"; 1549 }; 1550 1551 rtc: rtc@c2a0000 { 1552 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1553 reg = <0x0c2a0000 0x10000>; 1554 interrupt-parent = <&pmc>; 1555 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1556 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1557 clock-names = "rtc"; 1558 status = "disabled"; 1559 }; 1560 1561 gpio_aon: gpio@c2f0000 { 1562 compatible = "nvidia,tegra194-gpio-aon"; 1563 reg-names = "security", "gpio"; 1564 reg = <0xc2f0000 0x1000>, 1565 <0xc2f1000 0x1000>; 1566 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1567 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1570 gpio-controller; 1571 #gpio-cells = <2>; 1572 interrupt-controller; 1573 #interrupt-cells = <2>; 1574 }; 1575 1576 pwm4: pwm@c340000 { 1577 compatible = "nvidia,tegra194-pwm", 1578 "nvidia,tegra186-pwm"; 1579 reg = <0xc340000 0x10000>; 1580 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1581 clock-names = "pwm"; 1582 resets = <&bpmp TEGRA194_RESET_PWM4>; 1583 reset-names = "pwm"; 1584 status = "disabled"; 1585 #pwm-cells = <2>; 1586 }; 1587 1588 pmc: pmc@c360000 { 1589 compatible = "nvidia,tegra194-pmc"; 1590 reg = <0x0c360000 0x10000>, 1591 <0x0c370000 0x10000>, 1592 <0x0c380000 0x10000>, 1593 <0x0c390000 0x10000>, 1594 <0x0c3a0000 0x10000>; 1595 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1596 1597 #interrupt-cells = <2>; 1598 interrupt-controller; 1599 sdmmc1_3v3: sdmmc1-3v3 { 1600 pins = "sdmmc1-hv"; 1601 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1602 }; 1603 1604 sdmmc1_1v8: sdmmc1-1v8 { 1605 pins = "sdmmc1-hv"; 1606 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1607 }; 1608 sdmmc3_3v3: sdmmc3-3v3 { 1609 pins = "sdmmc3-hv"; 1610 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1611 }; 1612 1613 sdmmc3_1v8: sdmmc3-1v8 { 1614 pins = "sdmmc3-hv"; 1615 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1616 }; 1617 1618 }; 1619 1620 iommu@10000000 { 1621 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1622 reg = <0x10000000 0x800000>; 1623 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1662 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1663 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1664 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1665 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1667 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1668 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1670 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1674 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1675 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1679 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1680 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1681 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1683 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1688 stream-match-mask = <0x7f80>; 1689 #global-interrupts = <1>; 1690 #iommu-cells = <1>; 1691 1692 nvidia,memory-controller = <&mc>; 1693 status = "disabled"; 1694 }; 1695 1696 smmu: iommu@12000000 { 1697 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1698 reg = <0x12000000 0x800000>, 1699 <0x11000000 0x800000>; 1700 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1701 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1702 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1716 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1717 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1718 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1719 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1720 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1766 stream-match-mask = <0x7f80>; 1767 #global-interrupts = <2>; 1768 #iommu-cells = <1>; 1769 1770 nvidia,memory-controller = <&mc>; 1771 status = "okay"; 1772 }; 1773 1774 host1x@13e00000 { 1775 compatible = "nvidia,tegra194-host1x"; 1776 reg = <0x13e00000 0x10000>, 1777 <0x13e10000 0x10000>; 1778 reg-names = "hypervisor", "vm"; 1779 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1781 interrupt-names = "syncpt", "host1x"; 1782 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1783 clock-names = "host1x"; 1784 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1785 reset-names = "host1x"; 1786 1787 #address-cells = <1>; 1788 #size-cells = <1>; 1789 1790 ranges = <0x15000000 0x15000000 0x01000000>; 1791 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1792 interconnect-names = "dma-mem"; 1793 iommus = <&smmu TEGRA194_SID_HOST1X>; 1794 1795 nvdec@15140000 { 1796 compatible = "nvidia,tegra194-nvdec"; 1797 reg = <0x15140000 0x00040000>; 1798 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1799 clock-names = "nvdec"; 1800 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1801 reset-names = "nvdec"; 1802 1803 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1804 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1805 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1806 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1807 interconnect-names = "dma-mem", "read-1", "write"; 1808 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1809 dma-coherent; 1810 1811 nvidia,host1x-class = <0xf5>; 1812 }; 1813 1814 display-hub@15200000 { 1815 compatible = "nvidia,tegra194-display"; 1816 reg = <0x15200000 0x00040000>; 1817 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1818 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1819 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1820 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1821 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1822 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1823 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1824 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1825 "wgrp3", "wgrp4", "wgrp5"; 1826 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1827 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1828 clock-names = "disp", "hub"; 1829 status = "disabled"; 1830 1831 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1832 1833 #address-cells = <1>; 1834 #size-cells = <1>; 1835 1836 ranges = <0x15200000 0x15200000 0x40000>; 1837 1838 display@15200000 { 1839 compatible = "nvidia,tegra194-dc"; 1840 reg = <0x15200000 0x10000>; 1841 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1842 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1843 clock-names = "dc"; 1844 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1845 reset-names = "dc"; 1846 1847 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1848 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1849 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1850 interconnect-names = "dma-mem", "read-1"; 1851 1852 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1853 nvidia,head = <0>; 1854 }; 1855 1856 display@15210000 { 1857 compatible = "nvidia,tegra194-dc"; 1858 reg = <0x15210000 0x10000>; 1859 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1860 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1861 clock-names = "dc"; 1862 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 1863 reset-names = "dc"; 1864 1865 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 1866 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1867 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1868 interconnect-names = "dma-mem", "read-1"; 1869 1870 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1871 nvidia,head = <1>; 1872 }; 1873 1874 display@15220000 { 1875 compatible = "nvidia,tegra194-dc"; 1876 reg = <0x15220000 0x10000>; 1877 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1878 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 1879 clock-names = "dc"; 1880 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 1881 reset-names = "dc"; 1882 1883 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1884 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1885 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1886 interconnect-names = "dma-mem", "read-1"; 1887 1888 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1889 nvidia,head = <2>; 1890 }; 1891 1892 display@15230000 { 1893 compatible = "nvidia,tegra194-dc"; 1894 reg = <0x15230000 0x10000>; 1895 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1896 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 1897 clock-names = "dc"; 1898 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 1899 reset-names = "dc"; 1900 1901 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 1902 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1903 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1904 interconnect-names = "dma-mem", "read-1"; 1905 1906 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1907 nvidia,head = <3>; 1908 }; 1909 }; 1910 1911 vic@15340000 { 1912 compatible = "nvidia,tegra194-vic"; 1913 reg = <0x15340000 0x00040000>; 1914 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1915 clocks = <&bpmp TEGRA194_CLK_VIC>; 1916 clock-names = "vic"; 1917 resets = <&bpmp TEGRA194_RESET_VIC>; 1918 reset-names = "vic"; 1919 1920 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 1921 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 1922 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 1923 interconnect-names = "dma-mem", "write"; 1924 iommus = <&smmu TEGRA194_SID_VIC>; 1925 dma-coherent; 1926 }; 1927 1928 nvjpg@15380000 { 1929 compatible = "nvidia,tegra194-nvjpg"; 1930 reg = <0x15380000 0x40000>; 1931 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 1932 clock-names = "nvjpg"; 1933 resets = <&bpmp TEGRA194_RESET_NVJPG>; 1934 reset-names = "nvjpg"; 1935 1936 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 1937 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 1938 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 1939 interconnect-names = "dma-mem", "write"; 1940 iommus = <&smmu TEGRA194_SID_NVJPG>; 1941 dma-coherent; 1942 }; 1943 1944 nvdec@15480000 { 1945 compatible = "nvidia,tegra194-nvdec"; 1946 reg = <0x15480000 0x00040000>; 1947 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 1948 clock-names = "nvdec"; 1949 resets = <&bpmp TEGRA194_RESET_NVDEC>; 1950 reset-names = "nvdec"; 1951 1952 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 1953 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 1954 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 1955 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 1956 interconnect-names = "dma-mem", "read-1", "write"; 1957 iommus = <&smmu TEGRA194_SID_NVDEC>; 1958 dma-coherent; 1959 1960 nvidia,host1x-class = <0xf0>; 1961 }; 1962 1963 nvenc@154c0000 { 1964 compatible = "nvidia,tegra194-nvenc"; 1965 reg = <0x154c0000 0x40000>; 1966 clocks = <&bpmp TEGRA194_CLK_NVENC>; 1967 clock-names = "nvenc"; 1968 resets = <&bpmp TEGRA194_RESET_NVENC>; 1969 reset-names = "nvenc"; 1970 1971 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 1972 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 1973 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 1974 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 1975 interconnect-names = "dma-mem", "read-1", "write"; 1976 iommus = <&smmu TEGRA194_SID_NVENC>; 1977 dma-coherent; 1978 1979 nvidia,host1x-class = <0x21>; 1980 }; 1981 1982 dpaux0: dpaux@155c0000 { 1983 compatible = "nvidia,tegra194-dpaux"; 1984 reg = <0x155c0000 0x10000>; 1985 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1986 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 1987 <&bpmp TEGRA194_CLK_PLLDP>; 1988 clock-names = "dpaux", "parent"; 1989 resets = <&bpmp TEGRA194_RESET_DPAUX>; 1990 reset-names = "dpaux"; 1991 status = "disabled"; 1992 1993 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1994 1995 state_dpaux0_aux: pinmux-aux { 1996 groups = "dpaux-io"; 1997 function = "aux"; 1998 }; 1999 2000 state_dpaux0_i2c: pinmux-i2c { 2001 groups = "dpaux-io"; 2002 function = "i2c"; 2003 }; 2004 2005 state_dpaux0_off: pinmux-off { 2006 groups = "dpaux-io"; 2007 function = "off"; 2008 }; 2009 2010 i2c-bus { 2011 #address-cells = <1>; 2012 #size-cells = <0>; 2013 }; 2014 }; 2015 2016 dpaux1: dpaux@155d0000 { 2017 compatible = "nvidia,tegra194-dpaux"; 2018 reg = <0x155d0000 0x10000>; 2019 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2020 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 2021 <&bpmp TEGRA194_CLK_PLLDP>; 2022 clock-names = "dpaux", "parent"; 2023 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2024 reset-names = "dpaux"; 2025 status = "disabled"; 2026 2027 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2028 2029 state_dpaux1_aux: pinmux-aux { 2030 groups = "dpaux-io"; 2031 function = "aux"; 2032 }; 2033 2034 state_dpaux1_i2c: pinmux-i2c { 2035 groups = "dpaux-io"; 2036 function = "i2c"; 2037 }; 2038 2039 state_dpaux1_off: pinmux-off { 2040 groups = "dpaux-io"; 2041 function = "off"; 2042 }; 2043 2044 i2c-bus { 2045 #address-cells = <1>; 2046 #size-cells = <0>; 2047 }; 2048 }; 2049 2050 dpaux2: dpaux@155e0000 { 2051 compatible = "nvidia,tegra194-dpaux"; 2052 reg = <0x155e0000 0x10000>; 2053 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2054 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2055 <&bpmp TEGRA194_CLK_PLLDP>; 2056 clock-names = "dpaux", "parent"; 2057 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2058 reset-names = "dpaux"; 2059 status = "disabled"; 2060 2061 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2062 2063 state_dpaux2_aux: pinmux-aux { 2064 groups = "dpaux-io"; 2065 function = "aux"; 2066 }; 2067 2068 state_dpaux2_i2c: pinmux-i2c { 2069 groups = "dpaux-io"; 2070 function = "i2c"; 2071 }; 2072 2073 state_dpaux2_off: pinmux-off { 2074 groups = "dpaux-io"; 2075 function = "off"; 2076 }; 2077 2078 i2c-bus { 2079 #address-cells = <1>; 2080 #size-cells = <0>; 2081 }; 2082 }; 2083 2084 dpaux3: dpaux@155f0000 { 2085 compatible = "nvidia,tegra194-dpaux"; 2086 reg = <0x155f0000 0x10000>; 2087 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2088 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2089 <&bpmp TEGRA194_CLK_PLLDP>; 2090 clock-names = "dpaux", "parent"; 2091 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2092 reset-names = "dpaux"; 2093 status = "disabled"; 2094 2095 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2096 2097 state_dpaux3_aux: pinmux-aux { 2098 groups = "dpaux-io"; 2099 function = "aux"; 2100 }; 2101 2102 state_dpaux3_i2c: pinmux-i2c { 2103 groups = "dpaux-io"; 2104 function = "i2c"; 2105 }; 2106 2107 state_dpaux3_off: pinmux-off { 2108 groups = "dpaux-io"; 2109 function = "off"; 2110 }; 2111 2112 i2c-bus { 2113 #address-cells = <1>; 2114 #size-cells = <0>; 2115 }; 2116 }; 2117 2118 nvenc@15a80000 { 2119 compatible = "nvidia,tegra194-nvenc"; 2120 reg = <0x15a80000 0x00040000>; 2121 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2122 clock-names = "nvenc"; 2123 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2124 reset-names = "nvenc"; 2125 2126 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2127 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2128 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2129 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2130 interconnect-names = "dma-mem", "read-1", "write"; 2131 iommus = <&smmu TEGRA194_SID_NVENC1>; 2132 dma-coherent; 2133 2134 nvidia,host1x-class = <0x22>; 2135 }; 2136 2137 sor0: sor@15b00000 { 2138 compatible = "nvidia,tegra194-sor"; 2139 reg = <0x15b00000 0x40000>; 2140 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2141 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2142 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2143 <&bpmp TEGRA194_CLK_PLLD>, 2144 <&bpmp TEGRA194_CLK_PLLDP>, 2145 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2146 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2147 clock-names = "sor", "out", "parent", "dp", "safe", 2148 "pad"; 2149 resets = <&bpmp TEGRA194_RESET_SOR0>; 2150 reset-names = "sor"; 2151 pinctrl-0 = <&state_dpaux0_aux>; 2152 pinctrl-1 = <&state_dpaux0_i2c>; 2153 pinctrl-2 = <&state_dpaux0_off>; 2154 pinctrl-names = "aux", "i2c", "off"; 2155 status = "disabled"; 2156 2157 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2158 nvidia,interface = <0>; 2159 }; 2160 2161 sor1: sor@15b40000 { 2162 compatible = "nvidia,tegra194-sor"; 2163 reg = <0x15b40000 0x40000>; 2164 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2165 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2166 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2167 <&bpmp TEGRA194_CLK_PLLD2>, 2168 <&bpmp TEGRA194_CLK_PLLDP>, 2169 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2170 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2171 clock-names = "sor", "out", "parent", "dp", "safe", 2172 "pad"; 2173 resets = <&bpmp TEGRA194_RESET_SOR1>; 2174 reset-names = "sor"; 2175 pinctrl-0 = <&state_dpaux1_aux>; 2176 pinctrl-1 = <&state_dpaux1_i2c>; 2177 pinctrl-2 = <&state_dpaux1_off>; 2178 pinctrl-names = "aux", "i2c", "off"; 2179 status = "disabled"; 2180 2181 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2182 nvidia,interface = <1>; 2183 }; 2184 2185 sor2: sor@15b80000 { 2186 compatible = "nvidia,tegra194-sor"; 2187 reg = <0x15b80000 0x40000>; 2188 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2189 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2190 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2191 <&bpmp TEGRA194_CLK_PLLD3>, 2192 <&bpmp TEGRA194_CLK_PLLDP>, 2193 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2194 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2195 clock-names = "sor", "out", "parent", "dp", "safe", 2196 "pad"; 2197 resets = <&bpmp TEGRA194_RESET_SOR2>; 2198 reset-names = "sor"; 2199 pinctrl-0 = <&state_dpaux2_aux>; 2200 pinctrl-1 = <&state_dpaux2_i2c>; 2201 pinctrl-2 = <&state_dpaux2_off>; 2202 pinctrl-names = "aux", "i2c", "off"; 2203 status = "disabled"; 2204 2205 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2206 nvidia,interface = <2>; 2207 }; 2208 2209 sor3: sor@15bc0000 { 2210 compatible = "nvidia,tegra194-sor"; 2211 reg = <0x15bc0000 0x40000>; 2212 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2213 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2214 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2215 <&bpmp TEGRA194_CLK_PLLD4>, 2216 <&bpmp TEGRA194_CLK_PLLDP>, 2217 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2218 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2219 clock-names = "sor", "out", "parent", "dp", "safe", 2220 "pad"; 2221 resets = <&bpmp TEGRA194_RESET_SOR3>; 2222 reset-names = "sor"; 2223 pinctrl-0 = <&state_dpaux3_aux>; 2224 pinctrl-1 = <&state_dpaux3_i2c>; 2225 pinctrl-2 = <&state_dpaux3_off>; 2226 pinctrl-names = "aux", "i2c", "off"; 2227 status = "disabled"; 2228 2229 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2230 nvidia,interface = <3>; 2231 }; 2232 }; 2233 2234 gpu@17000000 { 2235 compatible = "nvidia,gv11b"; 2236 reg = <0x17000000 0x1000000>, 2237 <0x18000000 0x1000000>; 2238 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2239 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2240 interrupt-names = "stall", "nonstall"; 2241 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2242 <&bpmp TEGRA194_CLK_GPU_PWR>, 2243 <&bpmp TEGRA194_CLK_FUSE>; 2244 clock-names = "gpu", "pwr", "fuse"; 2245 resets = <&bpmp TEGRA194_RESET_GPU>; 2246 reset-names = "gpu"; 2247 dma-coherent; 2248 2249 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2250 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2251 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2252 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2253 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2254 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2255 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2256 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2257 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2258 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2259 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2260 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2261 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2262 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2263 "read-1", "read-1-hp", "write-1", 2264 "read-2", "read-2-hp", "write-2", 2265 "read-3", "read-3-hp", "write-3"; 2266 }; 2267 }; 2268 2269 pcie@14100000 { 2270 compatible = "nvidia,tegra194-pcie"; 2271 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2272 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2273 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2274 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2275 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2276 reg-names = "appl", "config", "atu_dma", "dbi"; 2277 2278 status = "disabled"; 2279 2280 #address-cells = <3>; 2281 #size-cells = <2>; 2282 device_type = "pci"; 2283 num-lanes = <1>; 2284 linux,pci-domain = <1>; 2285 2286 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2287 clock-names = "core"; 2288 2289 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2290 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2291 reset-names = "apb", "core"; 2292 2293 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2294 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2295 interrupt-names = "intr", "msi"; 2296 2297 #interrupt-cells = <1>; 2298 interrupt-map-mask = <0 0 0 0>; 2299 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2300 2301 nvidia,bpmp = <&bpmp 1>; 2302 2303 nvidia,aspm-cmrt-us = <60>; 2304 nvidia,aspm-pwr-on-t-us = <20>; 2305 nvidia,aspm-l0s-entrance-latency-us = <3>; 2306 2307 bus-range = <0x0 0xff>; 2308 2309 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2310 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2311 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2312 2313 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2314 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2315 interconnect-names = "dma-mem", "write"; 2316 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2317 iommu-map-mask = <0x0>; 2318 dma-coherent; 2319 }; 2320 2321 pcie@14120000 { 2322 compatible = "nvidia,tegra194-pcie"; 2323 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2324 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2325 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2326 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2327 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2328 reg-names = "appl", "config", "atu_dma", "dbi"; 2329 2330 status = "disabled"; 2331 2332 #address-cells = <3>; 2333 #size-cells = <2>; 2334 device_type = "pci"; 2335 num-lanes = <1>; 2336 linux,pci-domain = <2>; 2337 2338 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2339 clock-names = "core"; 2340 2341 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2342 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2343 reset-names = "apb", "core"; 2344 2345 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2346 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2347 interrupt-names = "intr", "msi"; 2348 2349 #interrupt-cells = <1>; 2350 interrupt-map-mask = <0 0 0 0>; 2351 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2352 2353 nvidia,bpmp = <&bpmp 2>; 2354 2355 nvidia,aspm-cmrt-us = <60>; 2356 nvidia,aspm-pwr-on-t-us = <20>; 2357 nvidia,aspm-l0s-entrance-latency-us = <3>; 2358 2359 bus-range = <0x0 0xff>; 2360 2361 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2362 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2363 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2364 2365 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2366 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2367 interconnect-names = "dma-mem", "write"; 2368 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2369 iommu-map-mask = <0x0>; 2370 dma-coherent; 2371 }; 2372 2373 pcie@14140000 { 2374 compatible = "nvidia,tegra194-pcie"; 2375 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2376 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2377 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2378 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2379 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2380 reg-names = "appl", "config", "atu_dma", "dbi"; 2381 2382 status = "disabled"; 2383 2384 #address-cells = <3>; 2385 #size-cells = <2>; 2386 device_type = "pci"; 2387 num-lanes = <1>; 2388 linux,pci-domain = <3>; 2389 2390 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2391 clock-names = "core"; 2392 2393 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2394 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2395 reset-names = "apb", "core"; 2396 2397 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2398 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2399 interrupt-names = "intr", "msi"; 2400 2401 #interrupt-cells = <1>; 2402 interrupt-map-mask = <0 0 0 0>; 2403 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2404 2405 nvidia,bpmp = <&bpmp 3>; 2406 2407 nvidia,aspm-cmrt-us = <60>; 2408 nvidia,aspm-pwr-on-t-us = <20>; 2409 nvidia,aspm-l0s-entrance-latency-us = <3>; 2410 2411 bus-range = <0x0 0xff>; 2412 2413 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2414 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2415 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2416 2417 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2418 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2419 interconnect-names = "dma-mem", "write"; 2420 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2421 iommu-map-mask = <0x0>; 2422 dma-coherent; 2423 }; 2424 2425 pcie@14160000 { 2426 compatible = "nvidia,tegra194-pcie"; 2427 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2428 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2429 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2430 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2431 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2432 reg-names = "appl", "config", "atu_dma", "dbi"; 2433 2434 status = "disabled"; 2435 2436 #address-cells = <3>; 2437 #size-cells = <2>; 2438 device_type = "pci"; 2439 num-lanes = <4>; 2440 linux,pci-domain = <4>; 2441 2442 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2443 clock-names = "core"; 2444 2445 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2446 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2447 reset-names = "apb", "core"; 2448 2449 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2450 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2451 interrupt-names = "intr", "msi"; 2452 2453 #interrupt-cells = <1>; 2454 interrupt-map-mask = <0 0 0 0>; 2455 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2456 2457 nvidia,bpmp = <&bpmp 4>; 2458 2459 nvidia,aspm-cmrt-us = <60>; 2460 nvidia,aspm-pwr-on-t-us = <20>; 2461 nvidia,aspm-l0s-entrance-latency-us = <3>; 2462 2463 bus-range = <0x0 0xff>; 2464 2465 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2466 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2467 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2468 2469 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2470 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2471 interconnect-names = "dma-mem", "write"; 2472 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2473 iommu-map-mask = <0x0>; 2474 dma-coherent; 2475 }; 2476 2477 pcie@14180000 { 2478 compatible = "nvidia,tegra194-pcie"; 2479 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2480 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2481 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2482 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2483 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2484 reg-names = "appl", "config", "atu_dma", "dbi"; 2485 2486 status = "disabled"; 2487 2488 #address-cells = <3>; 2489 #size-cells = <2>; 2490 device_type = "pci"; 2491 num-lanes = <8>; 2492 linux,pci-domain = <0>; 2493 2494 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2495 clock-names = "core"; 2496 2497 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2498 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2499 reset-names = "apb", "core"; 2500 2501 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2502 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2503 interrupt-names = "intr", "msi"; 2504 2505 #interrupt-cells = <1>; 2506 interrupt-map-mask = <0 0 0 0>; 2507 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2508 2509 nvidia,bpmp = <&bpmp 0>; 2510 2511 nvidia,aspm-cmrt-us = <60>; 2512 nvidia,aspm-pwr-on-t-us = <20>; 2513 nvidia,aspm-l0s-entrance-latency-us = <3>; 2514 2515 bus-range = <0x0 0xff>; 2516 2517 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2518 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2519 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2520 2521 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2522 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2523 interconnect-names = "dma-mem", "write"; 2524 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2525 iommu-map-mask = <0x0>; 2526 dma-coherent; 2527 }; 2528 2529 pcie@141a0000 { 2530 compatible = "nvidia,tegra194-pcie"; 2531 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2532 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2533 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2534 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2535 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2536 reg-names = "appl", "config", "atu_dma", "dbi"; 2537 2538 status = "disabled"; 2539 2540 #address-cells = <3>; 2541 #size-cells = <2>; 2542 device_type = "pci"; 2543 num-lanes = <8>; 2544 linux,pci-domain = <5>; 2545 2546 pinctrl-names = "default"; 2547 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2548 2549 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2550 clock-names = "core"; 2551 2552 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2553 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2554 reset-names = "apb", "core"; 2555 2556 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2557 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2558 interrupt-names = "intr", "msi"; 2559 2560 nvidia,bpmp = <&bpmp 5>; 2561 2562 #interrupt-cells = <1>; 2563 interrupt-map-mask = <0 0 0 0>; 2564 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2565 2566 nvidia,aspm-cmrt-us = <60>; 2567 nvidia,aspm-pwr-on-t-us = <20>; 2568 nvidia,aspm-l0s-entrance-latency-us = <3>; 2569 2570 bus-range = <0x0 0xff>; 2571 2572 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2573 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2574 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2575 2576 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2577 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2578 interconnect-names = "dma-mem", "write"; 2579 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2580 iommu-map-mask = <0x0>; 2581 dma-coherent; 2582 }; 2583 2584 pcie-ep@14160000 { 2585 compatible = "nvidia,tegra194-pcie-ep"; 2586 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2587 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2588 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2589 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2590 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2591 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2592 2593 status = "disabled"; 2594 2595 num-lanes = <4>; 2596 num-ib-windows = <2>; 2597 num-ob-windows = <8>; 2598 2599 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2600 clock-names = "core"; 2601 2602 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2603 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2604 reset-names = "apb", "core"; 2605 2606 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2607 interrupt-names = "intr"; 2608 2609 nvidia,bpmp = <&bpmp 4>; 2610 2611 nvidia,aspm-cmrt-us = <60>; 2612 nvidia,aspm-pwr-on-t-us = <20>; 2613 nvidia,aspm-l0s-entrance-latency-us = <3>; 2614 2615 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2616 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2617 interconnect-names = "dma-mem", "write"; 2618 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2619 iommu-map-mask = <0x0>; 2620 dma-coherent; 2621 }; 2622 2623 pcie-ep@14180000 { 2624 compatible = "nvidia,tegra194-pcie-ep"; 2625 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2626 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2627 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2628 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2629 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2630 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2631 2632 status = "disabled"; 2633 2634 num-lanes = <8>; 2635 num-ib-windows = <2>; 2636 num-ob-windows = <8>; 2637 2638 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2639 clock-names = "core"; 2640 2641 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2642 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2643 reset-names = "apb", "core"; 2644 2645 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2646 interrupt-names = "intr"; 2647 2648 nvidia,bpmp = <&bpmp 0>; 2649 2650 nvidia,aspm-cmrt-us = <60>; 2651 nvidia,aspm-pwr-on-t-us = <20>; 2652 nvidia,aspm-l0s-entrance-latency-us = <3>; 2653 2654 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2655 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2656 interconnect-names = "dma-mem", "write"; 2657 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2658 iommu-map-mask = <0x0>; 2659 dma-coherent; 2660 }; 2661 2662 pcie-ep@141a0000 { 2663 compatible = "nvidia,tegra194-pcie-ep"; 2664 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2665 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2666 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2667 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2668 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2669 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2670 2671 status = "disabled"; 2672 2673 num-lanes = <8>; 2674 num-ib-windows = <2>; 2675 num-ob-windows = <8>; 2676 2677 pinctrl-names = "default"; 2678 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2679 2680 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2681 clock-names = "core"; 2682 2683 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2684 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2685 reset-names = "apb", "core"; 2686 2687 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2688 interrupt-names = "intr"; 2689 2690 nvidia,bpmp = <&bpmp 5>; 2691 2692 nvidia,aspm-cmrt-us = <60>; 2693 nvidia,aspm-pwr-on-t-us = <20>; 2694 nvidia,aspm-l0s-entrance-latency-us = <3>; 2695 2696 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2697 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2698 interconnect-names = "dma-mem", "write"; 2699 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2700 iommu-map-mask = <0x0>; 2701 dma-coherent; 2702 }; 2703 2704 sram@40000000 { 2705 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2706 reg = <0x0 0x40000000 0x0 0x50000>; 2707 #address-cells = <1>; 2708 #size-cells = <1>; 2709 ranges = <0x0 0x0 0x40000000 0x50000>; 2710 2711 cpu_bpmp_tx: sram@4e000 { 2712 reg = <0x4e000 0x1000>; 2713 label = "cpu-bpmp-tx"; 2714 pool; 2715 }; 2716 2717 cpu_bpmp_rx: sram@4f000 { 2718 reg = <0x4f000 0x1000>; 2719 label = "cpu-bpmp-rx"; 2720 pool; 2721 }; 2722 }; 2723 2724 bpmp: bpmp { 2725 compatible = "nvidia,tegra186-bpmp"; 2726 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2727 TEGRA_HSP_DB_MASTER_BPMP>; 2728 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2729 #clock-cells = <1>; 2730 #reset-cells = <1>; 2731 #power-domain-cells = <1>; 2732 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2733 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2734 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2735 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2736 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2737 iommus = <&smmu TEGRA194_SID_BPMP>; 2738 2739 bpmp_i2c: i2c { 2740 compatible = "nvidia,tegra186-bpmp-i2c"; 2741 nvidia,bpmp-bus-id = <5>; 2742 #address-cells = <1>; 2743 #size-cells = <0>; 2744 }; 2745 2746 bpmp_thermal: thermal { 2747 compatible = "nvidia,tegra186-bpmp-thermal"; 2748 #thermal-sensor-cells = <1>; 2749 }; 2750 }; 2751 2752 cpus { 2753 compatible = "nvidia,tegra194-ccplex"; 2754 nvidia,bpmp = <&bpmp>; 2755 #address-cells = <1>; 2756 #size-cells = <0>; 2757 2758 cpu0_0: cpu@0 { 2759 compatible = "nvidia,tegra194-carmel"; 2760 device_type = "cpu"; 2761 reg = <0x000>; 2762 enable-method = "psci"; 2763 i-cache-size = <131072>; 2764 i-cache-line-size = <64>; 2765 i-cache-sets = <512>; 2766 d-cache-size = <65536>; 2767 d-cache-line-size = <64>; 2768 d-cache-sets = <256>; 2769 next-level-cache = <&l2c_0>; 2770 }; 2771 2772 cpu0_1: cpu@1 { 2773 compatible = "nvidia,tegra194-carmel"; 2774 device_type = "cpu"; 2775 reg = <0x001>; 2776 enable-method = "psci"; 2777 i-cache-size = <131072>; 2778 i-cache-line-size = <64>; 2779 i-cache-sets = <512>; 2780 d-cache-size = <65536>; 2781 d-cache-line-size = <64>; 2782 d-cache-sets = <256>; 2783 next-level-cache = <&l2c_0>; 2784 }; 2785 2786 cpu1_0: cpu@100 { 2787 compatible = "nvidia,tegra194-carmel"; 2788 device_type = "cpu"; 2789 reg = <0x100>; 2790 enable-method = "psci"; 2791 i-cache-size = <131072>; 2792 i-cache-line-size = <64>; 2793 i-cache-sets = <512>; 2794 d-cache-size = <65536>; 2795 d-cache-line-size = <64>; 2796 d-cache-sets = <256>; 2797 next-level-cache = <&l2c_1>; 2798 }; 2799 2800 cpu1_1: cpu@101 { 2801 compatible = "nvidia,tegra194-carmel"; 2802 device_type = "cpu"; 2803 reg = <0x101>; 2804 enable-method = "psci"; 2805 i-cache-size = <131072>; 2806 i-cache-line-size = <64>; 2807 i-cache-sets = <512>; 2808 d-cache-size = <65536>; 2809 d-cache-line-size = <64>; 2810 d-cache-sets = <256>; 2811 next-level-cache = <&l2c_1>; 2812 }; 2813 2814 cpu2_0: cpu@200 { 2815 compatible = "nvidia,tegra194-carmel"; 2816 device_type = "cpu"; 2817 reg = <0x200>; 2818 enable-method = "psci"; 2819 i-cache-size = <131072>; 2820 i-cache-line-size = <64>; 2821 i-cache-sets = <512>; 2822 d-cache-size = <65536>; 2823 d-cache-line-size = <64>; 2824 d-cache-sets = <256>; 2825 next-level-cache = <&l2c_2>; 2826 }; 2827 2828 cpu2_1: cpu@201 { 2829 compatible = "nvidia,tegra194-carmel"; 2830 device_type = "cpu"; 2831 reg = <0x201>; 2832 enable-method = "psci"; 2833 i-cache-size = <131072>; 2834 i-cache-line-size = <64>; 2835 i-cache-sets = <512>; 2836 d-cache-size = <65536>; 2837 d-cache-line-size = <64>; 2838 d-cache-sets = <256>; 2839 next-level-cache = <&l2c_2>; 2840 }; 2841 2842 cpu3_0: cpu@300 { 2843 compatible = "nvidia,tegra194-carmel"; 2844 device_type = "cpu"; 2845 reg = <0x300>; 2846 enable-method = "psci"; 2847 i-cache-size = <131072>; 2848 i-cache-line-size = <64>; 2849 i-cache-sets = <512>; 2850 d-cache-size = <65536>; 2851 d-cache-line-size = <64>; 2852 d-cache-sets = <256>; 2853 next-level-cache = <&l2c_3>; 2854 }; 2855 2856 cpu3_1: cpu@301 { 2857 compatible = "nvidia,tegra194-carmel"; 2858 device_type = "cpu"; 2859 reg = <0x301>; 2860 enable-method = "psci"; 2861 i-cache-size = <131072>; 2862 i-cache-line-size = <64>; 2863 i-cache-sets = <512>; 2864 d-cache-size = <65536>; 2865 d-cache-line-size = <64>; 2866 d-cache-sets = <256>; 2867 next-level-cache = <&l2c_3>; 2868 }; 2869 2870 cpu-map { 2871 cluster0 { 2872 core0 { 2873 cpu = <&cpu0_0>; 2874 }; 2875 2876 core1 { 2877 cpu = <&cpu0_1>; 2878 }; 2879 }; 2880 2881 cluster1 { 2882 core0 { 2883 cpu = <&cpu1_0>; 2884 }; 2885 2886 core1 { 2887 cpu = <&cpu1_1>; 2888 }; 2889 }; 2890 2891 cluster2 { 2892 core0 { 2893 cpu = <&cpu2_0>; 2894 }; 2895 2896 core1 { 2897 cpu = <&cpu2_1>; 2898 }; 2899 }; 2900 2901 cluster3 { 2902 core0 { 2903 cpu = <&cpu3_0>; 2904 }; 2905 2906 core1 { 2907 cpu = <&cpu3_1>; 2908 }; 2909 }; 2910 }; 2911 2912 l2c_0: l2-cache0 { 2913 cache-size = <2097152>; 2914 cache-line-size = <64>; 2915 cache-sets = <2048>; 2916 next-level-cache = <&l3c>; 2917 }; 2918 2919 l2c_1: l2-cache1 { 2920 cache-size = <2097152>; 2921 cache-line-size = <64>; 2922 cache-sets = <2048>; 2923 next-level-cache = <&l3c>; 2924 }; 2925 2926 l2c_2: l2-cache2 { 2927 cache-size = <2097152>; 2928 cache-line-size = <64>; 2929 cache-sets = <2048>; 2930 next-level-cache = <&l3c>; 2931 }; 2932 2933 l2c_3: l2-cache3 { 2934 cache-size = <2097152>; 2935 cache-line-size = <64>; 2936 cache-sets = <2048>; 2937 next-level-cache = <&l3c>; 2938 }; 2939 2940 l3c: l3-cache { 2941 cache-size = <4194304>; 2942 cache-line-size = <64>; 2943 cache-sets = <4096>; 2944 }; 2945 }; 2946 2947 pmu { 2948 compatible = "nvidia,carmel-pmu"; 2949 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2950 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2951 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 2952 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 2953 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 2954 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 2955 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 2956 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 2957 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 2958 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 2959 }; 2960 2961 psci { 2962 compatible = "arm,psci-1.0"; 2963 status = "okay"; 2964 method = "smc"; 2965 }; 2966 2967 sound { 2968 status = "disabled"; 2969 2970 clocks = <&bpmp TEGRA194_CLK_PLLA>, 2971 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2972 clock-names = "pll_a", "plla_out0"; 2973 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 2974 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 2975 <&bpmp TEGRA194_CLK_AUD_MCLK>; 2976 assigned-clock-parents = <0>, 2977 <&bpmp TEGRA194_CLK_PLLA>, 2978 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 2979 /* 2980 * PLLA supports dynamic ramp. Below initial rate is chosen 2981 * for this to work and oscillate between base rates required 2982 * for 8x and 11.025x sample rate streams. 2983 */ 2984 assigned-clock-rates = <258000000>; 2985 }; 2986 2987 tcu: serial { 2988 compatible = "nvidia,tegra194-tcu"; 2989 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 2990 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 2991 mbox-names = "rx", "tx"; 2992 }; 2993 2994 thermal-zones { 2995 cpu-thermal { 2996 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 2997 status = "disabled"; 2998 }; 2999 3000 gpu-thermal { 3001 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3002 status = "disabled"; 3003 }; 3004 3005 aux-thermal { 3006 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3007 status = "disabled"; 3008 }; 3009 3010 pllx-thermal { 3011 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3012 status = "disabled"; 3013 }; 3014 3015 ao-thermal { 3016 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3017 status = "disabled"; 3018 }; 3019 3020 tj-thermal { 3021 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3022 status = "disabled"; 3023 }; 3024 }; 3025 3026 timer { 3027 compatible = "arm,armv8-timer"; 3028 interrupts = <GIC_PPI 13 3029 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3030 <GIC_PPI 14 3031 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3032 <GIC_PPI 11 3033 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3034 <GIC_PPI 10 3035 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3036 interrupt-parent = <&gic>; 3037 always-on; 3038 }; 3039}; 3040