1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>; 26 27 apbmisc: misc@100000 { 28 compatible = "nvidia,tegra194-misc"; 29 reg = <0x0 0x00100000 0x0 0xf000>, 30 <0x0 0x0010f000 0x0 0x1000>; 31 }; 32 33 gpio: gpio@2200000 { 34 compatible = "nvidia,tegra194-gpio"; 35 reg-names = "security", "gpio"; 36 reg = <0x0 0x2200000 0x0 0x10000>, 37 <0x0 0x2210000 0x0 0x10000>; 38 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 86 #interrupt-cells = <2>; 87 interrupt-controller; 88 #gpio-cells = <2>; 89 gpio-controller; 90 gpio-ranges = <&pinmux 0 0 169>; 91 }; 92 93 cbb-noc@2300000 { 94 compatible = "nvidia,tegra194-cbb-noc"; 95 reg = <0x0 0x02300000 0x0 0x1000>; 96 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 98 nvidia,axi2apb = <&axi2apb>; 99 nvidia,apbmisc = <&apbmisc>; 100 status = "okay"; 101 }; 102 103 axi2apb: axi2apb@2390000 { 104 compatible = "nvidia,tegra194-axi2apb"; 105 reg = <0x0 0x2390000 0x0 0x1000>, 106 <0x0 0x23a0000 0x0 0x1000>, 107 <0x0 0x23b0000 0x0 0x1000>, 108 <0x0 0x23c0000 0x0 0x1000>, 109 <0x0 0x23d0000 0x0 0x1000>, 110 <0x0 0x23e0000 0x0 0x1000>; 111 status = "okay"; 112 }; 113 114 ethernet@2490000 { 115 compatible = "nvidia,tegra194-eqos", 116 "nvidia,tegra186-eqos", 117 "snps,dwc-qos-ethernet-4.10"; 118 reg = <0x0 0x02490000 0x0 0x10000>; 119 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 120 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 121 <&bpmp TEGRA194_CLK_EQOS_AXI>, 122 <&bpmp TEGRA194_CLK_EQOS_RX>, 123 <&bpmp TEGRA194_CLK_EQOS_TX>, 124 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 125 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 126 resets = <&bpmp TEGRA194_RESET_EQOS>; 127 reset-names = "eqos"; 128 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 129 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 130 interconnect-names = "dma-mem", "write"; 131 iommus = <&smmu TEGRA194_SID_EQOS>; 132 status = "disabled"; 133 134 snps,write-requests = <1>; 135 snps,read-requests = <3>; 136 snps,burst-map = <0x7>; 137 snps,txpbl = <16>; 138 snps,rxpbl = <8>; 139 }; 140 141 gpcdma: dma-controller@2600000 { 142 compatible = "nvidia,tegra194-gpcdma", 143 "nvidia,tegra186-gpcdma"; 144 reg = <0x0 0x2600000 0x0 0x210000>; 145 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 146 reset-names = "gpcdma"; 147 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 179 #dma-cells = <1>; 180 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 181 dma-coherent; 182 dma-channel-mask = <0xfffffffe>; 183 status = "okay"; 184 }; 185 186 aconnect@2900000 { 187 compatible = "nvidia,tegra194-aconnect", 188 "nvidia,tegra210-aconnect"; 189 clocks = <&bpmp TEGRA194_CLK_APE>, 190 <&bpmp TEGRA194_CLK_APB2APE>; 191 clock-names = "ape", "apb2ape"; 192 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 193 status = "disabled"; 194 195 #address-cells = <2>; 196 #size-cells = <2>; 197 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 198 199 adma: dma-controller@2930000 { 200 compatible = "nvidia,tegra194-adma", 201 "nvidia,tegra186-adma"; 202 reg = <0x0 0x02930000 0x0 0x20000>; 203 interrupt-parent = <&agic>; 204 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 236 #dma-cells = <1>; 237 clocks = <&bpmp TEGRA194_CLK_AHUB>; 238 clock-names = "d_audio"; 239 status = "disabled"; 240 }; 241 242 agic: interrupt-controller@2a40000 { 243 compatible = "nvidia,tegra194-agic", 244 "nvidia,tegra210-agic"; 245 #interrupt-cells = <3>; 246 interrupt-controller; 247 reg = <0x0 0x02a41000 0x0 0x1000>, 248 <0x0 0x02a42000 0x0 0x2000>; 249 interrupts = <GIC_SPI 145 250 (GIC_CPU_MASK_SIMPLE(4) | 251 IRQ_TYPE_LEVEL_HIGH)>; 252 clocks = <&bpmp TEGRA194_CLK_APE>; 253 clock-names = "clk"; 254 status = "disabled"; 255 }; 256 257 tegra_ahub: ahub@2900800 { 258 compatible = "nvidia,tegra194-ahub", 259 "nvidia,tegra186-ahub"; 260 reg = <0x0 0x02900800 0x0 0x800>; 261 clocks = <&bpmp TEGRA194_CLK_AHUB>; 262 clock-names = "ahub"; 263 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 264 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 265 status = "disabled"; 266 267 #address-cells = <2>; 268 #size-cells = <2>; 269 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 270 271 tegra_admaif: admaif@290f000 { 272 compatible = "nvidia,tegra194-admaif", 273 "nvidia,tegra186-admaif"; 274 reg = <0x0 0x0290f000 0x0 0x1000>; 275 dmas = <&adma 1>, <&adma 1>, 276 <&adma 2>, <&adma 2>, 277 <&adma 3>, <&adma 3>, 278 <&adma 4>, <&adma 4>, 279 <&adma 5>, <&adma 5>, 280 <&adma 6>, <&adma 6>, 281 <&adma 7>, <&adma 7>, 282 <&adma 8>, <&adma 8>, 283 <&adma 9>, <&adma 9>, 284 <&adma 10>, <&adma 10>, 285 <&adma 11>, <&adma 11>, 286 <&adma 12>, <&adma 12>, 287 <&adma 13>, <&adma 13>, 288 <&adma 14>, <&adma 14>, 289 <&adma 15>, <&adma 15>, 290 <&adma 16>, <&adma 16>, 291 <&adma 17>, <&adma 17>, 292 <&adma 18>, <&adma 18>, 293 <&adma 19>, <&adma 19>, 294 <&adma 20>, <&adma 20>; 295 dma-names = "rx1", "tx1", 296 "rx2", "tx2", 297 "rx3", "tx3", 298 "rx4", "tx4", 299 "rx5", "tx5", 300 "rx6", "tx6", 301 "rx7", "tx7", 302 "rx8", "tx8", 303 "rx9", "tx9", 304 "rx10", "tx10", 305 "rx11", "tx11", 306 "rx12", "tx12", 307 "rx13", "tx13", 308 "rx14", "tx14", 309 "rx15", "tx15", 310 "rx16", "tx16", 311 "rx17", "tx17", 312 "rx18", "tx18", 313 "rx19", "tx19", 314 "rx20", "tx20"; 315 status = "disabled"; 316 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 317 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 318 interconnect-names = "dma-mem", "write"; 319 iommus = <&smmu TEGRA194_SID_APE>; 320 }; 321 322 tegra_i2s1: i2s@2901000 { 323 compatible = "nvidia,tegra194-i2s", 324 "nvidia,tegra210-i2s"; 325 reg = <0x0 0x2901000 0x0 0x100>; 326 clocks = <&bpmp TEGRA194_CLK_I2S1>, 327 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 328 clock-names = "i2s", "sync_input"; 329 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 330 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 331 assigned-clock-rates = <1536000>; 332 sound-name-prefix = "I2S1"; 333 status = "disabled"; 334 }; 335 336 tegra_i2s2: i2s@2901100 { 337 compatible = "nvidia,tegra194-i2s", 338 "nvidia,tegra210-i2s"; 339 reg = <0x0 0x2901100 0x0 0x100>; 340 clocks = <&bpmp TEGRA194_CLK_I2S2>, 341 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 342 clock-names = "i2s", "sync_input"; 343 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 344 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 345 assigned-clock-rates = <1536000>; 346 sound-name-prefix = "I2S2"; 347 status = "disabled"; 348 }; 349 350 tegra_i2s3: i2s@2901200 { 351 compatible = "nvidia,tegra194-i2s", 352 "nvidia,tegra210-i2s"; 353 reg = <0x0 0x2901200 0x0 0x100>; 354 clocks = <&bpmp TEGRA194_CLK_I2S3>, 355 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 356 clock-names = "i2s", "sync_input"; 357 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 358 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 359 assigned-clock-rates = <1536000>; 360 sound-name-prefix = "I2S3"; 361 status = "disabled"; 362 }; 363 364 tegra_i2s4: i2s@2901300 { 365 compatible = "nvidia,tegra194-i2s", 366 "nvidia,tegra210-i2s"; 367 reg = <0x0 0x2901300 0x0 0x100>; 368 clocks = <&bpmp TEGRA194_CLK_I2S4>, 369 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 370 clock-names = "i2s", "sync_input"; 371 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 372 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 373 assigned-clock-rates = <1536000>; 374 sound-name-prefix = "I2S4"; 375 status = "disabled"; 376 }; 377 378 tegra_i2s5: i2s@2901400 { 379 compatible = "nvidia,tegra194-i2s", 380 "nvidia,tegra210-i2s"; 381 reg = <0x0 0x2901400 0x0 0x100>; 382 clocks = <&bpmp TEGRA194_CLK_I2S5>, 383 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 384 clock-names = "i2s", "sync_input"; 385 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 386 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 387 assigned-clock-rates = <1536000>; 388 sound-name-prefix = "I2S5"; 389 status = "disabled"; 390 }; 391 392 tegra_i2s6: i2s@2901500 { 393 compatible = "nvidia,tegra194-i2s", 394 "nvidia,tegra210-i2s"; 395 reg = <0x0 0x2901500 0x0 0x100>; 396 clocks = <&bpmp TEGRA194_CLK_I2S6>, 397 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 398 clock-names = "i2s", "sync_input"; 399 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 400 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 401 assigned-clock-rates = <1536000>; 402 sound-name-prefix = "I2S6"; 403 status = "disabled"; 404 }; 405 406 tegra_dmic1: dmic@2904000 { 407 compatible = "nvidia,tegra194-dmic", 408 "nvidia,tegra210-dmic"; 409 reg = <0x0 0x2904000 0x0 0x100>; 410 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 411 clock-names = "dmic"; 412 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 413 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 414 assigned-clock-rates = <3072000>; 415 sound-name-prefix = "DMIC1"; 416 status = "disabled"; 417 }; 418 419 tegra_dmic2: dmic@2904100 { 420 compatible = "nvidia,tegra194-dmic", 421 "nvidia,tegra210-dmic"; 422 reg = <0x0 0x2904100 0x0 0x100>; 423 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 424 clock-names = "dmic"; 425 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 426 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 427 assigned-clock-rates = <3072000>; 428 sound-name-prefix = "DMIC2"; 429 status = "disabled"; 430 }; 431 432 tegra_dmic3: dmic@2904200 { 433 compatible = "nvidia,tegra194-dmic", 434 "nvidia,tegra210-dmic"; 435 reg = <0x0 0x2904200 0x0 0x100>; 436 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 437 clock-names = "dmic"; 438 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 439 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 440 assigned-clock-rates = <3072000>; 441 sound-name-prefix = "DMIC3"; 442 status = "disabled"; 443 }; 444 445 tegra_dmic4: dmic@2904300 { 446 compatible = "nvidia,tegra194-dmic", 447 "nvidia,tegra210-dmic"; 448 reg = <0x0 0x2904300 0x0 0x100>; 449 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 450 clock-names = "dmic"; 451 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 452 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 453 assigned-clock-rates = <3072000>; 454 sound-name-prefix = "DMIC4"; 455 status = "disabled"; 456 }; 457 458 tegra_dspk1: dspk@2905000 { 459 compatible = "nvidia,tegra194-dspk", 460 "nvidia,tegra186-dspk"; 461 reg = <0x0 0x2905000 0x0 0x100>; 462 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 463 clock-names = "dspk"; 464 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 465 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 466 assigned-clock-rates = <12288000>; 467 sound-name-prefix = "DSPK1"; 468 status = "disabled"; 469 }; 470 471 tegra_dspk2: dspk@2905100 { 472 compatible = "nvidia,tegra194-dspk", 473 "nvidia,tegra186-dspk"; 474 reg = <0x0 0x2905100 0x0 0x100>; 475 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 476 clock-names = "dspk"; 477 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 478 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 479 assigned-clock-rates = <12288000>; 480 sound-name-prefix = "DSPK2"; 481 status = "disabled"; 482 }; 483 484 tegra_sfc1: sfc@2902000 { 485 compatible = "nvidia,tegra194-sfc", 486 "nvidia,tegra210-sfc"; 487 reg = <0x0 0x2902000 0x0 0x200>; 488 sound-name-prefix = "SFC1"; 489 status = "disabled"; 490 }; 491 492 tegra_sfc2: sfc@2902200 { 493 compatible = "nvidia,tegra194-sfc", 494 "nvidia,tegra210-sfc"; 495 reg = <0x0 0x2902200 0x0 0x200>; 496 sound-name-prefix = "SFC2"; 497 status = "disabled"; 498 }; 499 500 tegra_sfc3: sfc@2902400 { 501 compatible = "nvidia,tegra194-sfc", 502 "nvidia,tegra210-sfc"; 503 reg = <0x0 0x2902400 0x0 0x200>; 504 sound-name-prefix = "SFC3"; 505 status = "disabled"; 506 }; 507 508 tegra_sfc4: sfc@2902600 { 509 compatible = "nvidia,tegra194-sfc", 510 "nvidia,tegra210-sfc"; 511 reg = <0x0 0x2902600 0x0 0x200>; 512 sound-name-prefix = "SFC4"; 513 status = "disabled"; 514 }; 515 516 tegra_mvc1: mvc@290a000 { 517 compatible = "nvidia,tegra194-mvc", 518 "nvidia,tegra210-mvc"; 519 reg = <0x0 0x290a000 0x0 0x200>; 520 sound-name-prefix = "MVC1"; 521 status = "disabled"; 522 }; 523 524 tegra_mvc2: mvc@290a200 { 525 compatible = "nvidia,tegra194-mvc", 526 "nvidia,tegra210-mvc"; 527 reg = <0x0 0x290a200 0x0 0x200>; 528 sound-name-prefix = "MVC2"; 529 status = "disabled"; 530 }; 531 532 tegra_amx1: amx@2903000 { 533 compatible = "nvidia,tegra194-amx"; 534 reg = <0x0 0x2903000 0x0 0x100>; 535 sound-name-prefix = "AMX1"; 536 status = "disabled"; 537 }; 538 539 tegra_amx2: amx@2903100 { 540 compatible = "nvidia,tegra194-amx"; 541 reg = <0x0 0x2903100 0x0 0x100>; 542 sound-name-prefix = "AMX2"; 543 status = "disabled"; 544 }; 545 546 tegra_amx3: amx@2903200 { 547 compatible = "nvidia,tegra194-amx"; 548 reg = <0x0 0x2903200 0x0 0x100>; 549 sound-name-prefix = "AMX3"; 550 status = "disabled"; 551 }; 552 553 tegra_amx4: amx@2903300 { 554 compatible = "nvidia,tegra194-amx"; 555 reg = <0x0 0x2903300 0x0 0x100>; 556 sound-name-prefix = "AMX4"; 557 status = "disabled"; 558 }; 559 560 tegra_adx1: adx@2903800 { 561 compatible = "nvidia,tegra194-adx", 562 "nvidia,tegra210-adx"; 563 reg = <0x0 0x2903800 0x0 0x100>; 564 sound-name-prefix = "ADX1"; 565 status = "disabled"; 566 }; 567 568 tegra_adx2: adx@2903900 { 569 compatible = "nvidia,tegra194-adx", 570 "nvidia,tegra210-adx"; 571 reg = <0x0 0x2903900 0x0 0x100>; 572 sound-name-prefix = "ADX2"; 573 status = "disabled"; 574 }; 575 576 tegra_adx3: adx@2903a00 { 577 compatible = "nvidia,tegra194-adx", 578 "nvidia,tegra210-adx"; 579 reg = <0x0 0x2903a00 0x0 0x100>; 580 sound-name-prefix = "ADX3"; 581 status = "disabled"; 582 }; 583 584 tegra_adx4: adx@2903b00 { 585 compatible = "nvidia,tegra194-adx", 586 "nvidia,tegra210-adx"; 587 reg = <0x0 0x2903b00 0x0 0x100>; 588 sound-name-prefix = "ADX4"; 589 status = "disabled"; 590 }; 591 592 tegra_ope1: processing-engine@2908000 { 593 compatible = "nvidia,tegra194-ope", 594 "nvidia,tegra210-ope"; 595 reg = <0x0 0x2908000 0x0 0x100>; 596 sound-name-prefix = "OPE1"; 597 status = "disabled"; 598 599 #address-cells = <2>; 600 #size-cells = <2>; 601 ranges; 602 603 equalizer@2908100 { 604 compatible = "nvidia,tegra194-peq", 605 "nvidia,tegra210-peq"; 606 reg = <0x0 0x2908100 0x0 0x100>; 607 }; 608 609 dynamic-range-compressor@2908200 { 610 compatible = "nvidia,tegra194-mbdrc", 611 "nvidia,tegra210-mbdrc"; 612 reg = <0x0 0x2908200 0x0 0x200>; 613 }; 614 }; 615 616 tegra_amixer: amixer@290bb00 { 617 compatible = "nvidia,tegra194-amixer", 618 "nvidia,tegra210-amixer"; 619 reg = <0x0 0x290bb00 0x0 0x800>; 620 sound-name-prefix = "MIXER1"; 621 status = "disabled"; 622 }; 623 624 tegra_asrc: asrc@2910000 { 625 compatible = "nvidia,tegra194-asrc", 626 "nvidia,tegra186-asrc"; 627 reg = <0x0 0x2910000 0x0 0x2000>; 628 sound-name-prefix = "ASRC1"; 629 status = "disabled"; 630 }; 631 }; 632 }; 633 634 pinmux: pinmux@2430000 { 635 compatible = "nvidia,tegra194-pinmux"; 636 reg = <0x0 0x2430000 0x0 0x17000>; 637 status = "okay"; 638 639 pex_rst_c5_out_state: pinmux-pex-rst-c5-out { 640 pex_rst { 641 nvidia,pins = "pex_l5_rst_n_pgg1"; 642 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 643 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 644 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 645 nvidia,tristate = <TEGRA_PIN_DISABLE>; 646 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 647 }; 648 }; 649 650 clkreq_c5_bi_dir_state: pinmux-clkreq-c5-bi-dir { 651 clkreq { 652 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 653 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 654 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 655 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 656 nvidia,tristate = <TEGRA_PIN_DISABLE>; 657 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 658 }; 659 }; 660 }; 661 662 mc: memory-controller@2c00000 { 663 compatible = "nvidia,tegra194-mc"; 664 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 665 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 666 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 667 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 668 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 669 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 670 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 671 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 672 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 673 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 674 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 675 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 676 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 677 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 678 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 679 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 680 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 681 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 682 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 683 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 684 "ch11", "ch12", "ch13", "ch14", "ch15"; 685 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 686 #interconnect-cells = <1>; 687 status = "disabled"; 688 689 #address-cells = <2>; 690 #size-cells = <2>; 691 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 692 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 693 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 694 695 /* 696 * Bit 39 of addresses passing through the memory 697 * controller selects the XBAR format used when memory 698 * is accessed. This is used to transparently access 699 * memory in the XBAR format used by the discrete GPU 700 * (bit 39 set) or Tegra (bit 39 clear). 701 * 702 * As a consequence, the operating system must ensure 703 * that bit 39 is never used implicitly, for example 704 * via an I/O virtual address mapping of an IOMMU. If 705 * devices require access to the XBAR switch, their 706 * drivers must set this bit explicitly. 707 * 708 * Limit the DMA range for memory clients to [38:0]. 709 */ 710 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 711 712 emc: external-memory-controller@2c60000 { 713 compatible = "nvidia,tegra194-emc"; 714 reg = <0x0 0x02c60000 0x0 0x90000>, 715 <0x0 0x01780000 0x0 0x80000>; 716 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&bpmp TEGRA194_CLK_EMC>; 718 clock-names = "emc"; 719 720 #interconnect-cells = <0>; 721 722 nvidia,bpmp = <&bpmp>; 723 }; 724 }; 725 726 timer@3010000 { 727 compatible = "nvidia,tegra186-timer"; 728 reg = <0x0 0x03010000 0x0 0x000e0000>; 729 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 739 status = "okay"; 740 }; 741 742 uarta: serial@3100000 { 743 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 744 reg = <0x0 0x03100000 0x0 0x40>; 745 reg-shift = <2>; 746 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&bpmp TEGRA194_CLK_UARTA>; 748 clock-names = "serial"; 749 resets = <&bpmp TEGRA194_RESET_UARTA>; 750 reset-names = "serial"; 751 status = "disabled"; 752 }; 753 754 uartb: serial@3110000 { 755 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 756 reg = <0x0 0x03110000 0x0 0x40>; 757 reg-shift = <2>; 758 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&bpmp TEGRA194_CLK_UARTB>; 760 clock-names = "serial"; 761 resets = <&bpmp TEGRA194_RESET_UARTB>; 762 reset-names = "serial"; 763 status = "disabled"; 764 }; 765 766 uartd: serial@3130000 { 767 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 768 reg = <0x0 0x03130000 0x0 0x40>; 769 reg-shift = <2>; 770 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&bpmp TEGRA194_CLK_UARTD>; 772 clock-names = "serial"; 773 resets = <&bpmp TEGRA194_RESET_UARTD>; 774 reset-names = "serial"; 775 status = "disabled"; 776 }; 777 778 uarte: serial@3140000 { 779 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 780 reg = <0x0 0x03140000 0x0 0x40>; 781 reg-shift = <2>; 782 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 783 clocks = <&bpmp TEGRA194_CLK_UARTE>; 784 clock-names = "serial"; 785 resets = <&bpmp TEGRA194_RESET_UARTE>; 786 reset-names = "serial"; 787 status = "disabled"; 788 }; 789 790 uartf: serial@3150000 { 791 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 792 reg = <0x0 0x03150000 0x0 0x40>; 793 reg-shift = <2>; 794 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&bpmp TEGRA194_CLK_UARTF>; 796 clock-names = "serial"; 797 resets = <&bpmp TEGRA194_RESET_UARTF>; 798 reset-names = "serial"; 799 status = "disabled"; 800 }; 801 802 gen1_i2c: i2c@3160000 { 803 compatible = "nvidia,tegra194-i2c"; 804 reg = <0x0 0x03160000 0x0 0x10000>; 805 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 clocks = <&bpmp TEGRA194_CLK_I2C1>; 809 clock-names = "div-clk"; 810 resets = <&bpmp TEGRA194_RESET_I2C1>; 811 reset-names = "i2c"; 812 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 813 dma-coherent; 814 dmas = <&gpcdma 21>, <&gpcdma 21>; 815 dma-names = "rx", "tx"; 816 status = "disabled"; 817 }; 818 819 uarth: serial@3170000 { 820 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 821 reg = <0x0 0x03170000 0x0 0x40>; 822 reg-shift = <2>; 823 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&bpmp TEGRA194_CLK_UARTH>; 825 clock-names = "serial"; 826 resets = <&bpmp TEGRA194_RESET_UARTH>; 827 reset-names = "serial"; 828 status = "disabled"; 829 }; 830 831 cam_i2c: i2c@3180000 { 832 compatible = "nvidia,tegra194-i2c"; 833 reg = <0x0 0x03180000 0x0 0x10000>; 834 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 clocks = <&bpmp TEGRA194_CLK_I2C3>; 838 clock-names = "div-clk"; 839 resets = <&bpmp TEGRA194_RESET_I2C3>; 840 reset-names = "i2c"; 841 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 842 dma-coherent; 843 dmas = <&gpcdma 23>, <&gpcdma 23>; 844 dma-names = "rx", "tx"; 845 status = "disabled"; 846 }; 847 848 /* shares pads with dpaux1 */ 849 dp_aux_ch1_i2c: i2c@3190000 { 850 compatible = "nvidia,tegra194-i2c"; 851 reg = <0x0 0x03190000 0x0 0x10000>; 852 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 clocks = <&bpmp TEGRA194_CLK_I2C4>; 856 clock-names = "div-clk"; 857 resets = <&bpmp TEGRA194_RESET_I2C4>; 858 reset-names = "i2c"; 859 pinctrl-0 = <&state_dpaux1_i2c>; 860 pinctrl-1 = <&state_dpaux1_off>; 861 pinctrl-names = "default", "idle"; 862 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 863 dma-coherent; 864 dmas = <&gpcdma 26>, <&gpcdma 26>; 865 dma-names = "rx", "tx"; 866 status = "disabled"; 867 }; 868 869 /* shares pads with dpaux0 */ 870 dp_aux_ch0_i2c: i2c@31b0000 { 871 compatible = "nvidia,tegra194-i2c"; 872 reg = <0x0 0x031b0000 0x0 0x10000>; 873 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 clocks = <&bpmp TEGRA194_CLK_I2C6>; 877 clock-names = "div-clk"; 878 resets = <&bpmp TEGRA194_RESET_I2C6>; 879 reset-names = "i2c"; 880 pinctrl-0 = <&state_dpaux0_i2c>; 881 pinctrl-1 = <&state_dpaux0_off>; 882 pinctrl-names = "default", "idle"; 883 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 884 dma-coherent; 885 dmas = <&gpcdma 30>, <&gpcdma 30>; 886 dma-names = "rx", "tx"; 887 status = "disabled"; 888 }; 889 890 /* shares pads with dpaux2 */ 891 dp_aux_ch2_i2c: i2c@31c0000 { 892 compatible = "nvidia,tegra194-i2c"; 893 reg = <0x0 0x031c0000 0x0 0x10000>; 894 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 clocks = <&bpmp TEGRA194_CLK_I2C7>; 898 clock-names = "div-clk"; 899 resets = <&bpmp TEGRA194_RESET_I2C7>; 900 reset-names = "i2c"; 901 pinctrl-0 = <&state_dpaux2_i2c>; 902 pinctrl-1 = <&state_dpaux2_off>; 903 pinctrl-names = "default", "idle"; 904 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 905 dma-coherent; 906 dmas = <&gpcdma 27>, <&gpcdma 27>; 907 dma-names = "rx", "tx"; 908 status = "disabled"; 909 }; 910 911 /* shares pads with dpaux3 */ 912 dp_aux_ch3_i2c: i2c@31e0000 { 913 compatible = "nvidia,tegra194-i2c"; 914 reg = <0x0 0x031e0000 0x0 0x10000>; 915 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 clocks = <&bpmp TEGRA194_CLK_I2C9>; 919 clock-names = "div-clk"; 920 resets = <&bpmp TEGRA194_RESET_I2C9>; 921 reset-names = "i2c"; 922 pinctrl-0 = <&state_dpaux3_i2c>; 923 pinctrl-1 = <&state_dpaux3_off>; 924 pinctrl-names = "default", "idle"; 925 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 926 dma-coherent; 927 dmas = <&gpcdma 31>, <&gpcdma 31>; 928 dma-names = "rx", "tx"; 929 status = "disabled"; 930 }; 931 932 spi@3270000 { 933 compatible = "nvidia,tegra194-qspi"; 934 reg = <0x0 0x3270000 0x0 0x1000>; 935 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 939 <&bpmp TEGRA194_CLK_QSPI0_PM>; 940 clock-names = "qspi", "qspi_out"; 941 resets = <&bpmp TEGRA194_RESET_QSPI0>; 942 status = "disabled"; 943 }; 944 945 spi@3300000 { 946 compatible = "nvidia,tegra194-qspi"; 947 reg = <0x0 0x3300000 0x0 0x1000>; 948 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 952 <&bpmp TEGRA194_CLK_QSPI1_PM>; 953 clock-names = "qspi", "qspi_out"; 954 resets = <&bpmp TEGRA194_RESET_QSPI1>; 955 status = "disabled"; 956 }; 957 958 pwm1: pwm@3280000 { 959 compatible = "nvidia,tegra194-pwm", 960 "nvidia,tegra186-pwm"; 961 reg = <0x0 0x3280000 0x0 0x10000>; 962 clocks = <&bpmp TEGRA194_CLK_PWM1>; 963 resets = <&bpmp TEGRA194_RESET_PWM1>; 964 reset-names = "pwm"; 965 status = "disabled"; 966 #pwm-cells = <2>; 967 }; 968 969 pwm2: pwm@3290000 { 970 compatible = "nvidia,tegra194-pwm", 971 "nvidia,tegra186-pwm"; 972 reg = <0x0 0x3290000 0x0 0x10000>; 973 clocks = <&bpmp TEGRA194_CLK_PWM2>; 974 resets = <&bpmp TEGRA194_RESET_PWM2>; 975 reset-names = "pwm"; 976 status = "disabled"; 977 #pwm-cells = <2>; 978 }; 979 980 pwm3: pwm@32a0000 { 981 compatible = "nvidia,tegra194-pwm", 982 "nvidia,tegra186-pwm"; 983 reg = <0x0 0x32a0000 0x0 0x10000>; 984 clocks = <&bpmp TEGRA194_CLK_PWM3>; 985 resets = <&bpmp TEGRA194_RESET_PWM3>; 986 reset-names = "pwm"; 987 status = "disabled"; 988 #pwm-cells = <2>; 989 }; 990 991 pwm5: pwm@32c0000 { 992 compatible = "nvidia,tegra194-pwm", 993 "nvidia,tegra186-pwm"; 994 reg = <0x0 0x32c0000 0x0 0x10000>; 995 clocks = <&bpmp TEGRA194_CLK_PWM5>; 996 resets = <&bpmp TEGRA194_RESET_PWM5>; 997 reset-names = "pwm"; 998 status = "disabled"; 999 #pwm-cells = <2>; 1000 }; 1001 1002 pwm6: pwm@32d0000 { 1003 compatible = "nvidia,tegra194-pwm", 1004 "nvidia,tegra186-pwm"; 1005 reg = <0x0 0x32d0000 0x0 0x10000>; 1006 clocks = <&bpmp TEGRA194_CLK_PWM6>; 1007 resets = <&bpmp TEGRA194_RESET_PWM6>; 1008 reset-names = "pwm"; 1009 status = "disabled"; 1010 #pwm-cells = <2>; 1011 }; 1012 1013 pwm7: pwm@32e0000 { 1014 compatible = "nvidia,tegra194-pwm", 1015 "nvidia,tegra186-pwm"; 1016 reg = <0x0 0x32e0000 0x0 0x10000>; 1017 clocks = <&bpmp TEGRA194_CLK_PWM7>; 1018 resets = <&bpmp TEGRA194_RESET_PWM7>; 1019 reset-names = "pwm"; 1020 status = "disabled"; 1021 #pwm-cells = <2>; 1022 }; 1023 1024 pwm8: pwm@32f0000 { 1025 compatible = "nvidia,tegra194-pwm", 1026 "nvidia,tegra186-pwm"; 1027 reg = <0x0 0x32f0000 0x0 0x10000>; 1028 clocks = <&bpmp TEGRA194_CLK_PWM8>; 1029 resets = <&bpmp TEGRA194_RESET_PWM8>; 1030 reset-names = "pwm"; 1031 status = "disabled"; 1032 #pwm-cells = <2>; 1033 }; 1034 1035 sdmmc1: mmc@3400000 { 1036 compatible = "nvidia,tegra194-sdhci"; 1037 reg = <0x0 0x03400000 0x0 0x10000>; 1038 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1040 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1041 clock-names = "sdhci", "tmclk"; 1042 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1043 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1044 assigned-clock-parents = 1045 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1046 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1047 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 1048 reset-names = "sdhci"; 1049 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1050 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1051 interconnect-names = "dma-mem", "write"; 1052 iommus = <&smmu TEGRA194_SID_SDMMC1>; 1053 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1054 pinctrl-0 = <&sdmmc1_3v3>; 1055 pinctrl-1 = <&sdmmc1_1v8>; 1056 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 1057 <0x07>; 1058 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1059 <0x07>; 1060 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1061 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1062 <0x07>; 1063 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1064 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1065 nvidia,default-tap = <0x9>; 1066 nvidia,default-trim = <0x5>; 1067 sd-uhs-sdr25; 1068 sd-uhs-sdr50; 1069 sd-uhs-ddr50; 1070 sd-uhs-sdr104; 1071 status = "disabled"; 1072 }; 1073 1074 sdmmc3: mmc@3440000 { 1075 compatible = "nvidia,tegra194-sdhci"; 1076 reg = <0x0 0x03440000 0x0 0x10000>; 1077 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1079 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1080 clock-names = "sdhci", "tmclk"; 1081 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1082 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1083 assigned-clock-parents = 1084 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1085 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1086 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1087 reset-names = "sdhci"; 1088 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1089 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1090 interconnect-names = "dma-mem", "write"; 1091 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1092 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1093 pinctrl-0 = <&sdmmc3_3v3>; 1094 pinctrl-1 = <&sdmmc3_1v8>; 1095 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1096 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1097 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1098 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1099 <0x07>; 1100 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1101 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1102 <0x07>; 1103 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1104 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1105 nvidia,default-tap = <0x9>; 1106 nvidia,default-trim = <0x5>; 1107 sd-uhs-sdr25; 1108 sd-uhs-sdr50; 1109 sd-uhs-ddr50; 1110 sd-uhs-sdr104; 1111 status = "disabled"; 1112 }; 1113 1114 sdmmc4: mmc@3460000 { 1115 compatible = "nvidia,tegra194-sdhci"; 1116 reg = <0x0 0x03460000 0x0 0x10000>; 1117 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1119 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1120 clock-names = "sdhci", "tmclk"; 1121 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1122 <&bpmp TEGRA194_CLK_PLLC4>; 1123 assigned-clock-parents = 1124 <&bpmp TEGRA194_CLK_PLLC4>; 1125 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1126 reset-names = "sdhci"; 1127 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1128 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1129 interconnect-names = "dma-mem", "write"; 1130 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1131 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1132 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1133 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1134 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1135 <0x0a>; 1136 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1137 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1138 <0x0a>; 1139 nvidia,default-tap = <0x8>; 1140 nvidia,default-trim = <0x14>; 1141 nvidia,dqs-trim = <40>; 1142 cap-mmc-highspeed; 1143 mmc-ddr-1_8v; 1144 mmc-hs200-1_8v; 1145 mmc-hs400-1_8v; 1146 mmc-hs400-enhanced-strobe; 1147 supports-cqe; 1148 status = "disabled"; 1149 }; 1150 1151 hda@3510000 { 1152 compatible = "nvidia,tegra194-hda"; 1153 reg = <0x0 0x3510000 0x0 0x10000>; 1154 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1155 clocks = <&bpmp TEGRA194_CLK_HDA>, 1156 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1157 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1158 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1159 resets = <&bpmp TEGRA194_RESET_HDA>, 1160 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1161 reset-names = "hda", "hda2hdmi"; 1162 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1163 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1164 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1165 interconnect-names = "dma-mem", "write"; 1166 iommus = <&smmu TEGRA194_SID_HDA>; 1167 status = "disabled"; 1168 }; 1169 1170 xusb_padctl: padctl@3520000 { 1171 compatible = "nvidia,tegra194-xusb-padctl"; 1172 reg = <0x0 0x03520000 0x0 0x1000>, 1173 <0x0 0x03540000 0x0 0x1000>; 1174 reg-names = "padctl", "ao"; 1175 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1176 1177 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1178 reset-names = "padctl"; 1179 1180 status = "disabled"; 1181 1182 pads { 1183 usb2 { 1184 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1185 clock-names = "trk"; 1186 1187 lanes { 1188 usb2-0 { 1189 nvidia,function = "xusb"; 1190 status = "disabled"; 1191 #phy-cells = <0>; 1192 }; 1193 1194 usb2-1 { 1195 nvidia,function = "xusb"; 1196 status = "disabled"; 1197 #phy-cells = <0>; 1198 }; 1199 1200 usb2-2 { 1201 nvidia,function = "xusb"; 1202 status = "disabled"; 1203 #phy-cells = <0>; 1204 }; 1205 1206 usb2-3 { 1207 nvidia,function = "xusb"; 1208 status = "disabled"; 1209 #phy-cells = <0>; 1210 }; 1211 }; 1212 }; 1213 1214 usb3 { 1215 lanes { 1216 usb3-0 { 1217 nvidia,function = "xusb"; 1218 status = "disabled"; 1219 #phy-cells = <0>; 1220 }; 1221 1222 usb3-1 { 1223 nvidia,function = "xusb"; 1224 status = "disabled"; 1225 #phy-cells = <0>; 1226 }; 1227 1228 usb3-2 { 1229 nvidia,function = "xusb"; 1230 status = "disabled"; 1231 #phy-cells = <0>; 1232 }; 1233 1234 usb3-3 { 1235 nvidia,function = "xusb"; 1236 status = "disabled"; 1237 #phy-cells = <0>; 1238 }; 1239 }; 1240 }; 1241 }; 1242 1243 ports { 1244 usb2-0 { 1245 status = "disabled"; 1246 }; 1247 1248 usb2-1 { 1249 status = "disabled"; 1250 }; 1251 1252 usb2-2 { 1253 status = "disabled"; 1254 }; 1255 1256 usb2-3 { 1257 status = "disabled"; 1258 }; 1259 1260 usb3-0 { 1261 status = "disabled"; 1262 }; 1263 1264 usb3-1 { 1265 status = "disabled"; 1266 }; 1267 1268 usb3-2 { 1269 status = "disabled"; 1270 }; 1271 1272 usb3-3 { 1273 status = "disabled"; 1274 }; 1275 }; 1276 }; 1277 1278 usb@3550000 { 1279 compatible = "nvidia,tegra194-xudc"; 1280 reg = <0x0 0x03550000 0x0 0x8000>, 1281 <0x0 0x03558000 0x0 0x1000>; 1282 reg-names = "base", "fpci"; 1283 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1284 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1285 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1286 <&bpmp TEGRA194_CLK_XUSB_SS>, 1287 <&bpmp TEGRA194_CLK_XUSB_FS>; 1288 clock-names = "dev", "ss", "ss_src", "fs_src"; 1289 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1290 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1291 interconnect-names = "dma-mem", "write"; 1292 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1293 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1294 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1295 power-domain-names = "dev", "ss"; 1296 nvidia,xusb-padctl = <&xusb_padctl>; 1297 status = "disabled"; 1298 }; 1299 1300 usb@3610000 { 1301 compatible = "nvidia,tegra194-xusb"; 1302 reg = <0x0 0x03610000 0x0 0x40000>, 1303 <0x0 0x03600000 0x0 0x10000>; 1304 reg-names = "hcd", "fpci"; 1305 1306 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1308 1309 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1310 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1311 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1312 <&bpmp TEGRA194_CLK_XUSB_SS>, 1313 <&bpmp TEGRA194_CLK_CLK_M>, 1314 <&bpmp TEGRA194_CLK_XUSB_FS>, 1315 <&bpmp TEGRA194_CLK_UTMIPLL>, 1316 <&bpmp TEGRA194_CLK_CLK_M>, 1317 <&bpmp TEGRA194_CLK_PLLE>; 1318 clock-names = "xusb_host", "xusb_falcon_src", 1319 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1320 "xusb_fs_src", "pll_u_480m", "clk_m", 1321 "pll_e"; 1322 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1323 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1324 interconnect-names = "dma-mem", "write"; 1325 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1326 1327 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1328 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1329 power-domain-names = "xusb_host", "xusb_ss"; 1330 1331 nvidia,xusb-padctl = <&xusb_padctl>; 1332 status = "disabled"; 1333 }; 1334 1335 fuse@3820000 { 1336 compatible = "nvidia,tegra194-efuse"; 1337 reg = <0x0 0x03820000 0x0 0x10000>; 1338 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1339 clock-names = "fuse"; 1340 }; 1341 1342 gic: interrupt-controller@3881000 { 1343 compatible = "arm,gic-400"; 1344 #interrupt-cells = <3>; 1345 interrupt-controller; 1346 reg = <0x0 0x03881000 0x0 0x1000>, 1347 <0x0 0x03882000 0x0 0x2000>, 1348 <0x0 0x03884000 0x0 0x2000>, 1349 <0x0 0x03886000 0x0 0x2000>; 1350 interrupts = <GIC_PPI 9 1351 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1352 interrupt-parent = <&gic>; 1353 }; 1354 1355 cec@3960000 { 1356 compatible = "nvidia,tegra194-cec"; 1357 reg = <0x0 0x03960000 0x0 0x10000>; 1358 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1359 clocks = <&bpmp TEGRA194_CLK_CEC>; 1360 clock-names = "cec"; 1361 status = "disabled"; 1362 }; 1363 1364 hte_lic: hardware-timestamp@3aa0000 { 1365 compatible = "nvidia,tegra194-gte-lic"; 1366 reg = <0x0 0x3aa0000 0x0 0x10000>; 1367 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1368 nvidia,int-threshold = <1>; 1369 nvidia,slices = <11>; 1370 #timestamp-cells = <1>; 1371 status = "okay"; 1372 }; 1373 1374 hsp_top0: hsp@3c00000 { 1375 compatible = "nvidia,tegra194-hsp"; 1376 reg = <0x0 0x03c00000 0x0 0xa0000>; 1377 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1386 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1387 "shared3", "shared4", "shared5", "shared6", 1388 "shared7"; 1389 #mbox-cells = <2>; 1390 }; 1391 1392 p2u_hsio_0: phy@3e10000 { 1393 compatible = "nvidia,tegra194-p2u"; 1394 reg = <0x0 0x03e10000 0x0 0x10000>; 1395 reg-names = "ctl"; 1396 1397 #phy-cells = <0>; 1398 }; 1399 1400 p2u_hsio_1: phy@3e20000 { 1401 compatible = "nvidia,tegra194-p2u"; 1402 reg = <0x0 0x03e20000 0x0 0x10000>; 1403 reg-names = "ctl"; 1404 1405 #phy-cells = <0>; 1406 }; 1407 1408 p2u_hsio_2: phy@3e30000 { 1409 compatible = "nvidia,tegra194-p2u"; 1410 reg = <0x0 0x03e30000 0x0 0x10000>; 1411 reg-names = "ctl"; 1412 1413 #phy-cells = <0>; 1414 }; 1415 1416 p2u_hsio_3: phy@3e40000 { 1417 compatible = "nvidia,tegra194-p2u"; 1418 reg = <0x0 0x03e40000 0x0 0x10000>; 1419 reg-names = "ctl"; 1420 1421 #phy-cells = <0>; 1422 }; 1423 1424 p2u_hsio_4: phy@3e50000 { 1425 compatible = "nvidia,tegra194-p2u"; 1426 reg = <0x0 0x03e50000 0x0 0x10000>; 1427 reg-names = "ctl"; 1428 1429 #phy-cells = <0>; 1430 }; 1431 1432 p2u_hsio_5: phy@3e60000 { 1433 compatible = "nvidia,tegra194-p2u"; 1434 reg = <0x0 0x03e60000 0x0 0x10000>; 1435 reg-names = "ctl"; 1436 1437 #phy-cells = <0>; 1438 }; 1439 1440 p2u_hsio_6: phy@3e70000 { 1441 compatible = "nvidia,tegra194-p2u"; 1442 reg = <0x0 0x03e70000 0x0 0x10000>; 1443 reg-names = "ctl"; 1444 1445 #phy-cells = <0>; 1446 }; 1447 1448 p2u_hsio_7: phy@3e80000 { 1449 compatible = "nvidia,tegra194-p2u"; 1450 reg = <0x0 0x03e80000 0x0 0x10000>; 1451 reg-names = "ctl"; 1452 1453 #phy-cells = <0>; 1454 }; 1455 1456 p2u_hsio_8: phy@3e90000 { 1457 compatible = "nvidia,tegra194-p2u"; 1458 reg = <0x0 0x03e90000 0x0 0x10000>; 1459 reg-names = "ctl"; 1460 1461 #phy-cells = <0>; 1462 }; 1463 1464 p2u_hsio_9: phy@3ea0000 { 1465 compatible = "nvidia,tegra194-p2u"; 1466 reg = <0x0 0x03ea0000 0x0 0x10000>; 1467 reg-names = "ctl"; 1468 1469 #phy-cells = <0>; 1470 }; 1471 1472 p2u_nvhs_0: phy@3eb0000 { 1473 compatible = "nvidia,tegra194-p2u"; 1474 reg = <0x0 0x03eb0000 0x0 0x10000>; 1475 reg-names = "ctl"; 1476 1477 #phy-cells = <0>; 1478 }; 1479 1480 p2u_nvhs_1: phy@3ec0000 { 1481 compatible = "nvidia,tegra194-p2u"; 1482 reg = <0x0 0x03ec0000 0x0 0x10000>; 1483 reg-names = "ctl"; 1484 1485 #phy-cells = <0>; 1486 }; 1487 1488 p2u_nvhs_2: phy@3ed0000 { 1489 compatible = "nvidia,tegra194-p2u"; 1490 reg = <0x0 0x03ed0000 0x0 0x10000>; 1491 reg-names = "ctl"; 1492 1493 #phy-cells = <0>; 1494 }; 1495 1496 p2u_nvhs_3: phy@3ee0000 { 1497 compatible = "nvidia,tegra194-p2u"; 1498 reg = <0x0 0x03ee0000 0x0 0x10000>; 1499 reg-names = "ctl"; 1500 1501 #phy-cells = <0>; 1502 }; 1503 1504 p2u_nvhs_4: phy@3ef0000 { 1505 compatible = "nvidia,tegra194-p2u"; 1506 reg = <0x0 0x03ef0000 0x0 0x10000>; 1507 reg-names = "ctl"; 1508 1509 #phy-cells = <0>; 1510 }; 1511 1512 p2u_nvhs_5: phy@3f00000 { 1513 compatible = "nvidia,tegra194-p2u"; 1514 reg = <0x0 0x03f00000 0x0 0x10000>; 1515 reg-names = "ctl"; 1516 1517 #phy-cells = <0>; 1518 }; 1519 1520 p2u_nvhs_6: phy@3f10000 { 1521 compatible = "nvidia,tegra194-p2u"; 1522 reg = <0x0 0x03f10000 0x0 0x10000>; 1523 reg-names = "ctl"; 1524 1525 #phy-cells = <0>; 1526 }; 1527 1528 p2u_nvhs_7: phy@3f20000 { 1529 compatible = "nvidia,tegra194-p2u"; 1530 reg = <0x0 0x03f20000 0x0 0x10000>; 1531 reg-names = "ctl"; 1532 1533 #phy-cells = <0>; 1534 }; 1535 1536 p2u_hsio_10: phy@3f30000 { 1537 compatible = "nvidia,tegra194-p2u"; 1538 reg = <0x0 0x03f30000 0x0 0x10000>; 1539 reg-names = "ctl"; 1540 1541 #phy-cells = <0>; 1542 }; 1543 1544 p2u_hsio_11: phy@3f40000 { 1545 compatible = "nvidia,tegra194-p2u"; 1546 reg = <0x0 0x03f40000 0x0 0x10000>; 1547 reg-names = "ctl"; 1548 1549 #phy-cells = <0>; 1550 }; 1551 1552 sce-noc@b600000 { 1553 compatible = "nvidia,tegra194-sce-noc"; 1554 reg = <0x0 0xb600000 0x0 0x1000>; 1555 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1556 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1557 nvidia,axi2apb = <&axi2apb>; 1558 nvidia,apbmisc = <&apbmisc>; 1559 status = "okay"; 1560 }; 1561 1562 rce-noc@be00000 { 1563 compatible = "nvidia,tegra194-rce-noc"; 1564 reg = <0x0 0xbe00000 0x0 0x1000>; 1565 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1566 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1567 nvidia,axi2apb = <&axi2apb>; 1568 nvidia,apbmisc = <&apbmisc>; 1569 status = "okay"; 1570 }; 1571 1572 hsp_aon: hsp@c150000 { 1573 compatible = "nvidia,tegra194-hsp"; 1574 reg = <0x0 0x0c150000 0x0 0x90000>; 1575 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1579 /* 1580 * Shared interrupt 0 is routed only to AON/SPE, so 1581 * we only have 4 shared interrupts for the CCPLEX. 1582 */ 1583 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1584 #mbox-cells = <2>; 1585 }; 1586 1587 hte_aon: hardware-timestamp@c1e0000 { 1588 compatible = "nvidia,tegra194-gte-aon"; 1589 reg = <0x0 0xc1e0000 0x0 0x10000>; 1590 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1591 nvidia,int-threshold = <1>; 1592 nvidia,slices = <3>; 1593 #timestamp-cells = <1>; 1594 status = "okay"; 1595 }; 1596 1597 gen2_i2c: i2c@c240000 { 1598 compatible = "nvidia,tegra194-i2c"; 1599 reg = <0x0 0x0c240000 0x0 0x10000>; 1600 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1604 clock-names = "div-clk"; 1605 resets = <&bpmp TEGRA194_RESET_I2C2>; 1606 reset-names = "i2c"; 1607 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1608 dma-coherent; 1609 dmas = <&gpcdma 22>, <&gpcdma 22>; 1610 dma-names = "rx", "tx"; 1611 status = "disabled"; 1612 }; 1613 1614 gen8_i2c: i2c@c250000 { 1615 compatible = "nvidia,tegra194-i2c"; 1616 reg = <0x0 0x0c250000 0x0 0x10000>; 1617 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1618 #address-cells = <1>; 1619 #size-cells = <0>; 1620 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1621 clock-names = "div-clk"; 1622 resets = <&bpmp TEGRA194_RESET_I2C8>; 1623 reset-names = "i2c"; 1624 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1625 dma-coherent; 1626 dmas = <&gpcdma 0>, <&gpcdma 0>; 1627 dma-names = "rx", "tx"; 1628 status = "disabled"; 1629 }; 1630 1631 uartc: serial@c280000 { 1632 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1633 reg = <0x0 0x0c280000 0x0 0x40>; 1634 reg-shift = <2>; 1635 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1636 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1637 clock-names = "serial"; 1638 resets = <&bpmp TEGRA194_RESET_UARTC>; 1639 reset-names = "serial"; 1640 status = "disabled"; 1641 }; 1642 1643 uartg: serial@c290000 { 1644 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1645 reg = <0x0 0x0c290000 0x0 0x40>; 1646 reg-shift = <2>; 1647 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1648 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1649 clock-names = "serial"; 1650 resets = <&bpmp TEGRA194_RESET_UARTG>; 1651 reset-names = "serial"; 1652 status = "disabled"; 1653 }; 1654 1655 rtc: rtc@c2a0000 { 1656 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1657 reg = <0x0 0x0c2a0000 0x0 0x10000>; 1658 interrupt-parent = <&pmc>; 1659 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1660 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1661 clock-names = "rtc"; 1662 status = "disabled"; 1663 }; 1664 1665 gpio_aon: gpio@c2f0000 { 1666 compatible = "nvidia,tegra194-gpio-aon"; 1667 reg-names = "security", "gpio"; 1668 reg = <0x0 0xc2f0000 0x0 0x1000>, 1669 <0x0 0xc2f1000 0x0 0x1000>; 1670 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1674 gpio-controller; 1675 #gpio-cells = <2>; 1676 interrupt-controller; 1677 #interrupt-cells = <2>; 1678 gpio-ranges = <&pinmux_aon 0 0 30>; 1679 }; 1680 1681 pinmux_aon: pinmux@c300000 { 1682 compatible = "nvidia,tegra194-pinmux-aon"; 1683 reg = <0x0 0xc300000 0x0 0x4000>; 1684 1685 status = "okay"; 1686 }; 1687 1688 pwm4: pwm@c340000 { 1689 compatible = "nvidia,tegra194-pwm", 1690 "nvidia,tegra186-pwm"; 1691 reg = <0x0 0xc340000 0x0 0x10000>; 1692 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1693 resets = <&bpmp TEGRA194_RESET_PWM4>; 1694 reset-names = "pwm"; 1695 status = "disabled"; 1696 #pwm-cells = <2>; 1697 }; 1698 1699 pmc: pmc@c360000 { 1700 compatible = "nvidia,tegra194-pmc"; 1701 reg = <0x0 0x0c360000 0x0 0x10000>, 1702 <0x0 0x0c370000 0x0 0x10000>, 1703 <0x0 0x0c380000 0x0 0x10000>, 1704 <0x0 0x0c390000 0x0 0x10000>, 1705 <0x0 0x0c3a0000 0x0 0x10000>; 1706 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1707 1708 #interrupt-cells = <2>; 1709 interrupt-controller; 1710 sdmmc1_3v3: sdmmc1-3v3 { 1711 pins = "sdmmc1-hv"; 1712 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1713 }; 1714 1715 sdmmc1_1v8: sdmmc1-1v8 { 1716 pins = "sdmmc1-hv"; 1717 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1718 }; 1719 sdmmc3_3v3: sdmmc3-3v3 { 1720 pins = "sdmmc3-hv"; 1721 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1722 }; 1723 1724 sdmmc3_1v8: sdmmc3-1v8 { 1725 pins = "sdmmc3-hv"; 1726 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1727 }; 1728 1729 }; 1730 1731 aon-noc@c600000 { 1732 compatible = "nvidia,tegra194-aon-noc"; 1733 reg = <0x0 0xc600000 0x0 0x1000>; 1734 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1736 nvidia,apbmisc = <&apbmisc>; 1737 status = "okay"; 1738 }; 1739 1740 bpmp-noc@d600000 { 1741 compatible = "nvidia,tegra194-bpmp-noc"; 1742 reg = <0x0 0xd600000 0x0 0x1000>; 1743 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1745 nvidia,axi2apb = <&axi2apb>; 1746 nvidia,apbmisc = <&apbmisc>; 1747 status = "okay"; 1748 }; 1749 1750 iommu@10000000 { 1751 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1752 reg = <0x0 0x10000000 0x0 0x800000>; 1753 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1816 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1817 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1818 stream-match-mask = <0x7f80>; 1819 #global-interrupts = <1>; 1820 #iommu-cells = <1>; 1821 1822 nvidia,memory-controller = <&mc>; 1823 status = "disabled"; 1824 }; 1825 1826 smmu: iommu@12000000 { 1827 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1828 reg = <0x0 0x12000000 0x0 0x800000>, 1829 <0x0 0x11000000 0x0 0x800000>; 1830 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1896 stream-match-mask = <0x7f80>; 1897 #global-interrupts = <2>; 1898 #iommu-cells = <1>; 1899 1900 nvidia,memory-controller = <&mc>; 1901 status = "okay"; 1902 }; 1903 1904 host1x@13e00000 { 1905 compatible = "nvidia,tegra194-host1x"; 1906 reg = <0x0 0x13e00000 0x0 0x10000>, 1907 <0x0 0x13e10000 0x0 0x10000>; 1908 reg-names = "hypervisor", "vm"; 1909 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1911 interrupt-names = "syncpt", "host1x"; 1912 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1913 clock-names = "host1x"; 1914 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1915 reset-names = "host1x"; 1916 1917 #address-cells = <2>; 1918 #size-cells = <2>; 1919 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02800000>; 1920 1921 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1922 interconnect-names = "dma-mem"; 1923 iommus = <&smmu TEGRA194_SID_HOST1X>; 1924 1925 /* Context isolation domains */ 1926 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1927 <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1928 <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1929 <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1930 <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1931 <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1932 <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1933 <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1934 1935 nvdec@15140000 { 1936 compatible = "nvidia,tegra194-nvdec"; 1937 reg = <0x0 0x15140000 0x0 0x00040000>; 1938 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1939 clock-names = "nvdec"; 1940 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1941 reset-names = "nvdec"; 1942 1943 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1944 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1945 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1946 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1947 interconnect-names = "dma-mem", "read-1", "write"; 1948 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1949 dma-coherent; 1950 1951 nvidia,host1x-class = <0xf5>; 1952 }; 1953 1954 display-hub@15200000 { 1955 compatible = "nvidia,tegra194-display"; 1956 reg = <0x0 0x15200000 0x0 0x00040000>; 1957 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1958 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1959 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1960 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1961 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1962 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1963 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1964 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1965 "wgrp3", "wgrp4", "wgrp5"; 1966 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1967 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1968 clock-names = "disp", "hub"; 1969 status = "disabled"; 1970 1971 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1972 1973 #address-cells = <2>; 1974 #size-cells = <2>; 1975 ranges = <0x0 0x15200000 0x0 0x15200000 0x0 0x40000>; 1976 1977 display@15200000 { 1978 compatible = "nvidia,tegra194-dc"; 1979 reg = <0x0 0x15200000 0x0 0x10000>; 1980 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1981 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1982 clock-names = "dc"; 1983 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1984 reset-names = "dc"; 1985 1986 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1987 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1988 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1989 interconnect-names = "dma-mem", "read-1"; 1990 1991 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1992 nvidia,head = <0>; 1993 }; 1994 1995 display@15210000 { 1996 compatible = "nvidia,tegra194-dc"; 1997 reg = <0x0 0x15210000 0x0 0x10000>; 1998 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1999 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 2000 clock-names = "dc"; 2001 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 2002 reset-names = "dc"; 2003 2004 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 2005 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2006 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2007 interconnect-names = "dma-mem", "read-1"; 2008 2009 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2010 nvidia,head = <1>; 2011 }; 2012 2013 display@15220000 { 2014 compatible = "nvidia,tegra194-dc"; 2015 reg = <0x0 0x15220000 0x0 0x10000>; 2016 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2017 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 2018 clock-names = "dc"; 2019 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 2020 reset-names = "dc"; 2021 2022 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2023 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2024 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2025 interconnect-names = "dma-mem", "read-1"; 2026 2027 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2028 nvidia,head = <2>; 2029 }; 2030 2031 display@15230000 { 2032 compatible = "nvidia,tegra194-dc"; 2033 reg = <0x0 0x15230000 0x0 0x10000>; 2034 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2035 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 2036 clock-names = "dc"; 2037 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 2038 reset-names = "dc"; 2039 2040 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2041 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2042 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2043 interconnect-names = "dma-mem", "read-1"; 2044 2045 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2046 nvidia,head = <3>; 2047 }; 2048 }; 2049 2050 vic@15340000 { 2051 compatible = "nvidia,tegra194-vic"; 2052 reg = <0x0 0x15340000 0x0 0x00040000>; 2053 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2054 clocks = <&bpmp TEGRA194_CLK_VIC>; 2055 clock-names = "vic"; 2056 resets = <&bpmp TEGRA194_RESET_VIC>; 2057 reset-names = "vic"; 2058 2059 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2060 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2061 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2062 interconnect-names = "dma-mem", "write"; 2063 iommus = <&smmu TEGRA194_SID_VIC>; 2064 dma-coherent; 2065 }; 2066 2067 nvjpg@15380000 { 2068 compatible = "nvidia,tegra194-nvjpg"; 2069 reg = <0x0 0x15380000 0x0 0x40000>; 2070 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2071 clock-names = "nvjpg"; 2072 resets = <&bpmp TEGRA194_RESET_NVJPG>; 2073 reset-names = "nvjpg"; 2074 2075 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2076 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2077 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2078 interconnect-names = "dma-mem", "write"; 2079 iommus = <&smmu TEGRA194_SID_NVJPG>; 2080 dma-coherent; 2081 }; 2082 2083 nvdec@15480000 { 2084 compatible = "nvidia,tegra194-nvdec"; 2085 reg = <0x0 0x15480000 0x0 0x00040000>; 2086 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 2087 clock-names = "nvdec"; 2088 resets = <&bpmp TEGRA194_RESET_NVDEC>; 2089 reset-names = "nvdec"; 2090 2091 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 2092 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 2093 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 2094 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 2095 interconnect-names = "dma-mem", "read-1", "write"; 2096 iommus = <&smmu TEGRA194_SID_NVDEC>; 2097 dma-coherent; 2098 2099 nvidia,host1x-class = <0xf0>; 2100 }; 2101 2102 nvenc@154c0000 { 2103 compatible = "nvidia,tegra194-nvenc"; 2104 reg = <0x0 0x154c0000 0x0 0x40000>; 2105 clocks = <&bpmp TEGRA194_CLK_NVENC>; 2106 clock-names = "nvenc"; 2107 resets = <&bpmp TEGRA194_RESET_NVENC>; 2108 reset-names = "nvenc"; 2109 2110 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2111 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2112 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2113 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2114 interconnect-names = "dma-mem", "read-1", "write"; 2115 iommus = <&smmu TEGRA194_SID_NVENC>; 2116 dma-coherent; 2117 2118 nvidia,host1x-class = <0x21>; 2119 }; 2120 2121 dpaux0: dpaux@155c0000 { 2122 compatible = "nvidia,tegra194-dpaux"; 2123 reg = <0x0 0x155c0000 0x0 0x10000>; 2124 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 2125 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 2126 <&bpmp TEGRA194_CLK_PLLDP>; 2127 clock-names = "dpaux", "parent"; 2128 resets = <&bpmp TEGRA194_RESET_DPAUX>; 2129 reset-names = "dpaux"; 2130 status = "disabled"; 2131 2132 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2133 2134 state_dpaux0_aux: pinmux-aux { 2135 groups = "dpaux-io"; 2136 function = "aux"; 2137 }; 2138 2139 state_dpaux0_i2c: pinmux-i2c { 2140 groups = "dpaux-io"; 2141 function = "i2c"; 2142 }; 2143 2144 state_dpaux0_off: pinmux-off { 2145 groups = "dpaux-io"; 2146 function = "off"; 2147 }; 2148 2149 i2c-bus { 2150 #address-cells = <1>; 2151 #size-cells = <0>; 2152 }; 2153 }; 2154 2155 dpaux1: dpaux@155d0000 { 2156 compatible = "nvidia,tegra194-dpaux"; 2157 reg = <0x0 0x155d0000 0x0 0x10000>; 2158 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2159 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 2160 <&bpmp TEGRA194_CLK_PLLDP>; 2161 clock-names = "dpaux", "parent"; 2162 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2163 reset-names = "dpaux"; 2164 status = "disabled"; 2165 2166 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2167 2168 state_dpaux1_aux: pinmux-aux { 2169 groups = "dpaux-io"; 2170 function = "aux"; 2171 }; 2172 2173 state_dpaux1_i2c: pinmux-i2c { 2174 groups = "dpaux-io"; 2175 function = "i2c"; 2176 }; 2177 2178 state_dpaux1_off: pinmux-off { 2179 groups = "dpaux-io"; 2180 function = "off"; 2181 }; 2182 2183 i2c-bus { 2184 #address-cells = <1>; 2185 #size-cells = <0>; 2186 }; 2187 }; 2188 2189 dpaux2: dpaux@155e0000 { 2190 compatible = "nvidia,tegra194-dpaux"; 2191 reg = <0x0 0x155e0000 0x0 0x10000>; 2192 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2193 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2194 <&bpmp TEGRA194_CLK_PLLDP>; 2195 clock-names = "dpaux", "parent"; 2196 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2197 reset-names = "dpaux"; 2198 status = "disabled"; 2199 2200 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2201 2202 state_dpaux2_aux: pinmux-aux { 2203 groups = "dpaux-io"; 2204 function = "aux"; 2205 }; 2206 2207 state_dpaux2_i2c: pinmux-i2c { 2208 groups = "dpaux-io"; 2209 function = "i2c"; 2210 }; 2211 2212 state_dpaux2_off: pinmux-off { 2213 groups = "dpaux-io"; 2214 function = "off"; 2215 }; 2216 2217 i2c-bus { 2218 #address-cells = <1>; 2219 #size-cells = <0>; 2220 }; 2221 }; 2222 2223 dpaux3: dpaux@155f0000 { 2224 compatible = "nvidia,tegra194-dpaux"; 2225 reg = <0x0 0x155f0000 0x0 0x10000>; 2226 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2227 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2228 <&bpmp TEGRA194_CLK_PLLDP>; 2229 clock-names = "dpaux", "parent"; 2230 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2231 reset-names = "dpaux"; 2232 status = "disabled"; 2233 2234 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2235 2236 state_dpaux3_aux: pinmux-aux { 2237 groups = "dpaux-io"; 2238 function = "aux"; 2239 }; 2240 2241 state_dpaux3_i2c: pinmux-i2c { 2242 groups = "dpaux-io"; 2243 function = "i2c"; 2244 }; 2245 2246 state_dpaux3_off: pinmux-off { 2247 groups = "dpaux-io"; 2248 function = "off"; 2249 }; 2250 2251 i2c-bus { 2252 #address-cells = <1>; 2253 #size-cells = <0>; 2254 }; 2255 }; 2256 2257 nvenc@15a80000 { 2258 compatible = "nvidia,tegra194-nvenc"; 2259 reg = <0x0 0x15a80000 0x0 0x00040000>; 2260 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2261 clock-names = "nvenc"; 2262 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2263 reset-names = "nvenc"; 2264 2265 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2266 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2267 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2268 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2269 interconnect-names = "dma-mem", "read-1", "write"; 2270 iommus = <&smmu TEGRA194_SID_NVENC1>; 2271 dma-coherent; 2272 2273 nvidia,host1x-class = <0x22>; 2274 }; 2275 2276 sor0: sor@15b00000 { 2277 compatible = "nvidia,tegra194-sor"; 2278 reg = <0x0 0x15b00000 0x0 0x40000>; 2279 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2280 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2281 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2282 <&bpmp TEGRA194_CLK_PLLD>, 2283 <&bpmp TEGRA194_CLK_PLLDP>, 2284 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2285 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2286 clock-names = "sor", "out", "parent", "dp", "safe", 2287 "pad"; 2288 resets = <&bpmp TEGRA194_RESET_SOR0>; 2289 reset-names = "sor"; 2290 pinctrl-0 = <&state_dpaux0_aux>; 2291 pinctrl-1 = <&state_dpaux0_i2c>; 2292 pinctrl-2 = <&state_dpaux0_off>; 2293 pinctrl-names = "aux", "i2c", "off"; 2294 status = "disabled"; 2295 2296 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2297 nvidia,interface = <0>; 2298 }; 2299 2300 sor1: sor@15b40000 { 2301 compatible = "nvidia,tegra194-sor"; 2302 reg = <0x0 0x15b40000 0x0 0x40000>; 2303 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2304 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2305 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2306 <&bpmp TEGRA194_CLK_PLLD2>, 2307 <&bpmp TEGRA194_CLK_PLLDP>, 2308 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2309 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2310 clock-names = "sor", "out", "parent", "dp", "safe", 2311 "pad"; 2312 resets = <&bpmp TEGRA194_RESET_SOR1>; 2313 reset-names = "sor"; 2314 pinctrl-0 = <&state_dpaux1_aux>; 2315 pinctrl-1 = <&state_dpaux1_i2c>; 2316 pinctrl-2 = <&state_dpaux1_off>; 2317 pinctrl-names = "aux", "i2c", "off"; 2318 status = "disabled"; 2319 2320 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2321 nvidia,interface = <1>; 2322 }; 2323 2324 sor2: sor@15b80000 { 2325 compatible = "nvidia,tegra194-sor"; 2326 reg = <0x0 0x15b80000 0x0 0x40000>; 2327 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2328 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2329 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2330 <&bpmp TEGRA194_CLK_PLLD3>, 2331 <&bpmp TEGRA194_CLK_PLLDP>, 2332 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2333 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2334 clock-names = "sor", "out", "parent", "dp", "safe", 2335 "pad"; 2336 resets = <&bpmp TEGRA194_RESET_SOR2>; 2337 reset-names = "sor"; 2338 pinctrl-0 = <&state_dpaux2_aux>; 2339 pinctrl-1 = <&state_dpaux2_i2c>; 2340 pinctrl-2 = <&state_dpaux2_off>; 2341 pinctrl-names = "aux", "i2c", "off"; 2342 status = "disabled"; 2343 2344 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2345 nvidia,interface = <2>; 2346 }; 2347 2348 sor3: sor@15bc0000 { 2349 compatible = "nvidia,tegra194-sor"; 2350 reg = <0x0 0x15bc0000 0x0 0x40000>; 2351 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2352 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2353 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2354 <&bpmp TEGRA194_CLK_PLLD4>, 2355 <&bpmp TEGRA194_CLK_PLLDP>, 2356 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2357 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2358 clock-names = "sor", "out", "parent", "dp", "safe", 2359 "pad"; 2360 resets = <&bpmp TEGRA194_RESET_SOR3>; 2361 reset-names = "sor"; 2362 pinctrl-0 = <&state_dpaux3_aux>; 2363 pinctrl-1 = <&state_dpaux3_i2c>; 2364 pinctrl-2 = <&state_dpaux3_off>; 2365 pinctrl-names = "aux", "i2c", "off"; 2366 status = "disabled"; 2367 2368 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2369 nvidia,interface = <3>; 2370 }; 2371 }; 2372 2373 pcie@14100000 { 2374 compatible = "nvidia,tegra194-pcie"; 2375 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2376 reg = <0x0 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2377 <0x0 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2378 <0x0 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2379 <0x0 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2380 reg-names = "appl", "config", "atu_dma", "dbi"; 2381 2382 status = "disabled"; 2383 2384 #address-cells = <3>; 2385 #size-cells = <2>; 2386 device_type = "pci"; 2387 num-lanes = <1>; 2388 linux,pci-domain = <1>; 2389 2390 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2391 clock-names = "core"; 2392 2393 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2394 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2395 reset-names = "apb", "core"; 2396 2397 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2398 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2399 interrupt-names = "intr", "msi"; 2400 2401 #interrupt-cells = <1>; 2402 interrupt-map-mask = <0 0 0 0>; 2403 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2404 2405 nvidia,bpmp = <&bpmp 1>; 2406 2407 nvidia,aspm-cmrt-us = <60>; 2408 nvidia,aspm-pwr-on-t-us = <20>; 2409 nvidia,aspm-l0s-entrance-latency-us = <3>; 2410 2411 bus-range = <0x0 0xff>; 2412 2413 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2414 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2415 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2416 2417 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2418 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2419 interconnect-names = "dma-mem", "write"; 2420 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2421 iommu-map-mask = <0x0>; 2422 dma-coherent; 2423 }; 2424 2425 pcie@14120000 { 2426 compatible = "nvidia,tegra194-pcie"; 2427 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2428 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2429 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2430 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2431 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2432 reg-names = "appl", "config", "atu_dma", "dbi"; 2433 2434 status = "disabled"; 2435 2436 #address-cells = <3>; 2437 #size-cells = <2>; 2438 device_type = "pci"; 2439 num-lanes = <1>; 2440 linux,pci-domain = <2>; 2441 2442 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2443 clock-names = "core"; 2444 2445 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2446 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2447 reset-names = "apb", "core"; 2448 2449 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2450 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2451 interrupt-names = "intr", "msi"; 2452 2453 #interrupt-cells = <1>; 2454 interrupt-map-mask = <0 0 0 0>; 2455 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2456 2457 nvidia,bpmp = <&bpmp 2>; 2458 2459 nvidia,aspm-cmrt-us = <60>; 2460 nvidia,aspm-pwr-on-t-us = <20>; 2461 nvidia,aspm-l0s-entrance-latency-us = <3>; 2462 2463 bus-range = <0x0 0xff>; 2464 2465 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2466 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2467 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2468 2469 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2470 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2471 interconnect-names = "dma-mem", "write"; 2472 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2473 iommu-map-mask = <0x0>; 2474 dma-coherent; 2475 }; 2476 2477 pcie@14140000 { 2478 compatible = "nvidia,tegra194-pcie"; 2479 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2480 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2481 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2482 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2483 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2484 reg-names = "appl", "config", "atu_dma", "dbi"; 2485 2486 status = "disabled"; 2487 2488 #address-cells = <3>; 2489 #size-cells = <2>; 2490 device_type = "pci"; 2491 num-lanes = <1>; 2492 linux,pci-domain = <3>; 2493 2494 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2495 clock-names = "core"; 2496 2497 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2498 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2499 reset-names = "apb", "core"; 2500 2501 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2502 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2503 interrupt-names = "intr", "msi"; 2504 2505 #interrupt-cells = <1>; 2506 interrupt-map-mask = <0 0 0 0>; 2507 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2508 2509 nvidia,bpmp = <&bpmp 3>; 2510 2511 nvidia,aspm-cmrt-us = <60>; 2512 nvidia,aspm-pwr-on-t-us = <20>; 2513 nvidia,aspm-l0s-entrance-latency-us = <3>; 2514 2515 bus-range = <0x0 0xff>; 2516 2517 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2518 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2519 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2520 2521 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2522 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2523 interconnect-names = "dma-mem", "write"; 2524 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2525 iommu-map-mask = <0x0>; 2526 dma-coherent; 2527 }; 2528 2529 pcie@14160000 { 2530 compatible = "nvidia,tegra194-pcie"; 2531 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2532 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2533 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2534 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2535 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2536 reg-names = "appl", "config", "atu_dma", "dbi"; 2537 2538 status = "disabled"; 2539 2540 #address-cells = <3>; 2541 #size-cells = <2>; 2542 device_type = "pci"; 2543 num-lanes = <4>; 2544 linux,pci-domain = <4>; 2545 2546 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2547 clock-names = "core"; 2548 2549 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2550 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2551 reset-names = "apb", "core"; 2552 2553 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2554 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2555 interrupt-names = "intr", "msi"; 2556 2557 #interrupt-cells = <1>; 2558 interrupt-map-mask = <0 0 0 0>; 2559 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2560 2561 nvidia,bpmp = <&bpmp 4>; 2562 2563 nvidia,aspm-cmrt-us = <60>; 2564 nvidia,aspm-pwr-on-t-us = <20>; 2565 nvidia,aspm-l0s-entrance-latency-us = <3>; 2566 2567 bus-range = <0x0 0xff>; 2568 2569 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2570 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2571 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2572 2573 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2574 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2575 interconnect-names = "dma-mem", "write"; 2576 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2577 iommu-map-mask = <0x0>; 2578 dma-coherent; 2579 }; 2580 2581 pcie-ep@14160000 { 2582 compatible = "nvidia,tegra194-pcie-ep"; 2583 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2584 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2585 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2586 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2587 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2588 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2589 2590 status = "disabled"; 2591 2592 num-lanes = <4>; 2593 num-ib-windows = <2>; 2594 num-ob-windows = <8>; 2595 2596 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2597 clock-names = "core"; 2598 2599 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2600 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2601 reset-names = "apb", "core"; 2602 2603 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2604 interrupt-names = "intr"; 2605 2606 nvidia,bpmp = <&bpmp 4>; 2607 2608 nvidia,aspm-cmrt-us = <60>; 2609 nvidia,aspm-pwr-on-t-us = <20>; 2610 nvidia,aspm-l0s-entrance-latency-us = <3>; 2611 2612 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2613 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2614 interconnect-names = "dma-mem", "write"; 2615 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2616 iommu-map-mask = <0x0>; 2617 dma-coherent; 2618 }; 2619 2620 pcie@14180000 { 2621 compatible = "nvidia,tegra194-pcie"; 2622 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2623 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2624 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2625 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2626 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2627 reg-names = "appl", "config", "atu_dma", "dbi"; 2628 2629 status = "disabled"; 2630 2631 #address-cells = <3>; 2632 #size-cells = <2>; 2633 device_type = "pci"; 2634 num-lanes = <8>; 2635 linux,pci-domain = <0>; 2636 2637 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2638 clock-names = "core"; 2639 2640 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2641 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2642 reset-names = "apb", "core"; 2643 2644 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2645 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2646 interrupt-names = "intr", "msi"; 2647 2648 #interrupt-cells = <1>; 2649 interrupt-map-mask = <0 0 0 0>; 2650 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2651 2652 nvidia,bpmp = <&bpmp 0>; 2653 2654 nvidia,aspm-cmrt-us = <60>; 2655 nvidia,aspm-pwr-on-t-us = <20>; 2656 nvidia,aspm-l0s-entrance-latency-us = <3>; 2657 2658 bus-range = <0x0 0xff>; 2659 2660 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2661 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2662 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2663 2664 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2665 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2666 interconnect-names = "dma-mem", "write"; 2667 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2668 iommu-map-mask = <0x0>; 2669 dma-coherent; 2670 }; 2671 2672 pcie-ep@14180000 { 2673 compatible = "nvidia,tegra194-pcie-ep"; 2674 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2675 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2676 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2677 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2678 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2679 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2680 2681 status = "disabled"; 2682 2683 num-lanes = <8>; 2684 num-ib-windows = <2>; 2685 num-ob-windows = <8>; 2686 2687 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2688 clock-names = "core"; 2689 2690 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2691 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2692 reset-names = "apb", "core"; 2693 2694 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2695 interrupt-names = "intr"; 2696 2697 nvidia,bpmp = <&bpmp 0>; 2698 2699 nvidia,aspm-cmrt-us = <60>; 2700 nvidia,aspm-pwr-on-t-us = <20>; 2701 nvidia,aspm-l0s-entrance-latency-us = <3>; 2702 2703 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2704 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2705 interconnect-names = "dma-mem", "write"; 2706 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2707 iommu-map-mask = <0x0>; 2708 dma-coherent; 2709 }; 2710 2711 pcie@141a0000 { 2712 compatible = "nvidia,tegra194-pcie"; 2713 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2714 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2715 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2716 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2717 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2718 reg-names = "appl", "config", "atu_dma", "dbi"; 2719 2720 status = "disabled"; 2721 2722 #address-cells = <3>; 2723 #size-cells = <2>; 2724 device_type = "pci"; 2725 num-lanes = <8>; 2726 linux,pci-domain = <5>; 2727 2728 pinctrl-names = "default"; 2729 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2730 2731 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2732 clock-names = "core"; 2733 2734 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2735 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2736 reset-names = "apb", "core"; 2737 2738 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2739 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2740 interrupt-names = "intr", "msi"; 2741 2742 nvidia,bpmp = <&bpmp 5>; 2743 2744 #interrupt-cells = <1>; 2745 interrupt-map-mask = <0 0 0 0>; 2746 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2747 2748 nvidia,aspm-cmrt-us = <60>; 2749 nvidia,aspm-pwr-on-t-us = <20>; 2750 nvidia,aspm-l0s-entrance-latency-us = <3>; 2751 2752 bus-range = <0x0 0xff>; 2753 2754 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2755 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2756 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2757 2758 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2759 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2760 interconnect-names = "dma-mem", "write"; 2761 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2762 iommu-map-mask = <0x0>; 2763 dma-coherent; 2764 }; 2765 2766 pcie-ep@141a0000 { 2767 compatible = "nvidia,tegra194-pcie-ep"; 2768 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2769 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2770 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2771 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2772 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2773 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2774 2775 status = "disabled"; 2776 2777 num-lanes = <8>; 2778 num-ib-windows = <2>; 2779 num-ob-windows = <8>; 2780 2781 pinctrl-names = "default"; 2782 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2783 2784 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2785 clock-names = "core"; 2786 2787 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2788 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2789 reset-names = "apb", "core"; 2790 2791 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2792 interrupt-names = "intr"; 2793 2794 nvidia,bpmp = <&bpmp 5>; 2795 2796 nvidia,aspm-cmrt-us = <60>; 2797 nvidia,aspm-pwr-on-t-us = <20>; 2798 nvidia,aspm-l0s-entrance-latency-us = <3>; 2799 2800 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2801 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2802 interconnect-names = "dma-mem", "write"; 2803 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2804 iommu-map-mask = <0x0>; 2805 dma-coherent; 2806 }; 2807 2808 gpu@17000000 { 2809 compatible = "nvidia,gv11b"; 2810 reg = <0x0 0x17000000 0x0 0x1000000>, 2811 <0x0 0x18000000 0x0 0x1000000>; 2812 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2813 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2814 interrupt-names = "stall", "nonstall"; 2815 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2816 <&bpmp TEGRA194_CLK_GPU_PWR>, 2817 <&bpmp TEGRA194_CLK_FUSE>; 2818 clock-names = "gpu", "pwr", "fuse"; 2819 resets = <&bpmp TEGRA194_RESET_GPU>; 2820 reset-names = "gpu"; 2821 dma-coherent; 2822 2823 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2824 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2825 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2826 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2827 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2828 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2829 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2830 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2831 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2832 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2833 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2834 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2835 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2836 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2837 "read-1", "read-1-hp", "write-1", 2838 "read-2", "read-2-hp", "write-2", 2839 "read-3", "read-3-hp", "write-3"; 2840 }; 2841 }; 2842 2843 sram@40000000 { 2844 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2845 reg = <0x0 0x40000000 0x0 0x50000>; 2846 2847 #address-cells = <1>; 2848 #size-cells = <1>; 2849 ranges = <0x0 0x0 0x40000000 0x50000>; 2850 2851 no-memory-wc; 2852 2853 cpu_bpmp_tx: sram@4e000 { 2854 reg = <0x4e000 0x1000>; 2855 label = "cpu-bpmp-tx"; 2856 pool; 2857 }; 2858 2859 cpu_bpmp_rx: sram@4f000 { 2860 reg = <0x4f000 0x1000>; 2861 label = "cpu-bpmp-rx"; 2862 pool; 2863 }; 2864 }; 2865 2866 bpmp: bpmp { 2867 compatible = "nvidia,tegra186-bpmp"; 2868 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2869 TEGRA_HSP_DB_MASTER_BPMP>; 2870 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2871 #clock-cells = <1>; 2872 #reset-cells = <1>; 2873 #power-domain-cells = <1>; 2874 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2875 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2876 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2877 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2878 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2879 iommus = <&smmu TEGRA194_SID_BPMP>; 2880 2881 bpmp_i2c: i2c { 2882 compatible = "nvidia,tegra186-bpmp-i2c"; 2883 nvidia,bpmp-bus-id = <5>; 2884 #address-cells = <1>; 2885 #size-cells = <0>; 2886 }; 2887 2888 bpmp_thermal: thermal { 2889 compatible = "nvidia,tegra186-bpmp-thermal"; 2890 #thermal-sensor-cells = <1>; 2891 }; 2892 }; 2893 2894 cpus { 2895 compatible = "nvidia,tegra194-ccplex"; 2896 nvidia,bpmp = <&bpmp>; 2897 #address-cells = <1>; 2898 #size-cells = <0>; 2899 2900 cpu0_0: cpu@0 { 2901 compatible = "nvidia,tegra194-carmel"; 2902 device_type = "cpu"; 2903 reg = <0x000>; 2904 enable-method = "psci"; 2905 i-cache-size = <131072>; 2906 i-cache-line-size = <64>; 2907 i-cache-sets = <512>; 2908 d-cache-size = <65536>; 2909 d-cache-line-size = <64>; 2910 d-cache-sets = <256>; 2911 next-level-cache = <&l2c_0>; 2912 }; 2913 2914 cpu0_1: cpu@1 { 2915 compatible = "nvidia,tegra194-carmel"; 2916 device_type = "cpu"; 2917 reg = <0x001>; 2918 enable-method = "psci"; 2919 i-cache-size = <131072>; 2920 i-cache-line-size = <64>; 2921 i-cache-sets = <512>; 2922 d-cache-size = <65536>; 2923 d-cache-line-size = <64>; 2924 d-cache-sets = <256>; 2925 next-level-cache = <&l2c_0>; 2926 }; 2927 2928 cpu1_0: cpu@100 { 2929 compatible = "nvidia,tegra194-carmel"; 2930 device_type = "cpu"; 2931 reg = <0x100>; 2932 enable-method = "psci"; 2933 i-cache-size = <131072>; 2934 i-cache-line-size = <64>; 2935 i-cache-sets = <512>; 2936 d-cache-size = <65536>; 2937 d-cache-line-size = <64>; 2938 d-cache-sets = <256>; 2939 next-level-cache = <&l2c_1>; 2940 }; 2941 2942 cpu1_1: cpu@101 { 2943 compatible = "nvidia,tegra194-carmel"; 2944 device_type = "cpu"; 2945 reg = <0x101>; 2946 enable-method = "psci"; 2947 i-cache-size = <131072>; 2948 i-cache-line-size = <64>; 2949 i-cache-sets = <512>; 2950 d-cache-size = <65536>; 2951 d-cache-line-size = <64>; 2952 d-cache-sets = <256>; 2953 next-level-cache = <&l2c_1>; 2954 }; 2955 2956 cpu2_0: cpu@200 { 2957 compatible = "nvidia,tegra194-carmel"; 2958 device_type = "cpu"; 2959 reg = <0x200>; 2960 enable-method = "psci"; 2961 i-cache-size = <131072>; 2962 i-cache-line-size = <64>; 2963 i-cache-sets = <512>; 2964 d-cache-size = <65536>; 2965 d-cache-line-size = <64>; 2966 d-cache-sets = <256>; 2967 next-level-cache = <&l2c_2>; 2968 }; 2969 2970 cpu2_1: cpu@201 { 2971 compatible = "nvidia,tegra194-carmel"; 2972 device_type = "cpu"; 2973 reg = <0x201>; 2974 enable-method = "psci"; 2975 i-cache-size = <131072>; 2976 i-cache-line-size = <64>; 2977 i-cache-sets = <512>; 2978 d-cache-size = <65536>; 2979 d-cache-line-size = <64>; 2980 d-cache-sets = <256>; 2981 next-level-cache = <&l2c_2>; 2982 }; 2983 2984 cpu3_0: cpu@300 { 2985 compatible = "nvidia,tegra194-carmel"; 2986 device_type = "cpu"; 2987 reg = <0x300>; 2988 enable-method = "psci"; 2989 i-cache-size = <131072>; 2990 i-cache-line-size = <64>; 2991 i-cache-sets = <512>; 2992 d-cache-size = <65536>; 2993 d-cache-line-size = <64>; 2994 d-cache-sets = <256>; 2995 next-level-cache = <&l2c_3>; 2996 }; 2997 2998 cpu3_1: cpu@301 { 2999 compatible = "nvidia,tegra194-carmel"; 3000 device_type = "cpu"; 3001 reg = <0x301>; 3002 enable-method = "psci"; 3003 i-cache-size = <131072>; 3004 i-cache-line-size = <64>; 3005 i-cache-sets = <512>; 3006 d-cache-size = <65536>; 3007 d-cache-line-size = <64>; 3008 d-cache-sets = <256>; 3009 next-level-cache = <&l2c_3>; 3010 }; 3011 3012 cpu-map { 3013 cluster0 { 3014 core0 { 3015 cpu = <&cpu0_0>; 3016 }; 3017 3018 core1 { 3019 cpu = <&cpu0_1>; 3020 }; 3021 }; 3022 3023 cluster1 { 3024 core0 { 3025 cpu = <&cpu1_0>; 3026 }; 3027 3028 core1 { 3029 cpu = <&cpu1_1>; 3030 }; 3031 }; 3032 3033 cluster2 { 3034 core0 { 3035 cpu = <&cpu2_0>; 3036 }; 3037 3038 core1 { 3039 cpu = <&cpu2_1>; 3040 }; 3041 }; 3042 3043 cluster3 { 3044 core0 { 3045 cpu = <&cpu3_0>; 3046 }; 3047 3048 core1 { 3049 cpu = <&cpu3_1>; 3050 }; 3051 }; 3052 }; 3053 3054 l2c_0: l2-cache0 { 3055 compatible = "cache"; 3056 cache-unified; 3057 cache-size = <2097152>; 3058 cache-line-size = <64>; 3059 cache-sets = <2048>; 3060 cache-level = <2>; 3061 next-level-cache = <&l3c>; 3062 }; 3063 3064 l2c_1: l2-cache1 { 3065 compatible = "cache"; 3066 cache-unified; 3067 cache-size = <2097152>; 3068 cache-line-size = <64>; 3069 cache-sets = <2048>; 3070 cache-level = <2>; 3071 next-level-cache = <&l3c>; 3072 }; 3073 3074 l2c_2: l2-cache2 { 3075 compatible = "cache"; 3076 cache-unified; 3077 cache-size = <2097152>; 3078 cache-line-size = <64>; 3079 cache-sets = <2048>; 3080 cache-level = <2>; 3081 next-level-cache = <&l3c>; 3082 }; 3083 3084 l2c_3: l2-cache3 { 3085 compatible = "cache"; 3086 cache-unified; 3087 cache-size = <2097152>; 3088 cache-line-size = <64>; 3089 cache-sets = <2048>; 3090 cache-level = <2>; 3091 next-level-cache = <&l3c>; 3092 }; 3093 3094 l3c: l3-cache { 3095 compatible = "cache"; 3096 cache-unified; 3097 cache-size = <4194304>; 3098 cache-line-size = <64>; 3099 cache-level = <3>; 3100 cache-sets = <4096>; 3101 }; 3102 }; 3103 3104 pmu { 3105 compatible = "nvidia,carmel-pmu"; 3106 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 3114 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 3115 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 3116 }; 3117 3118 psci { 3119 compatible = "arm,psci-1.0"; 3120 status = "okay"; 3121 method = "smc"; 3122 }; 3123 3124 sound { 3125 status = "disabled"; 3126 3127 clocks = <&bpmp TEGRA194_CLK_PLLA>, 3128 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3129 clock-names = "pll_a", "plla_out0"; 3130 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 3131 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 3132 <&bpmp TEGRA194_CLK_AUD_MCLK>; 3133 assigned-clock-parents = <0>, 3134 <&bpmp TEGRA194_CLK_PLLA>, 3135 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3136 /* 3137 * PLLA supports dynamic ramp. Below initial rate is chosen 3138 * for this to work and oscillate between base rates required 3139 * for 8x and 11.025x sample rate streams. 3140 */ 3141 assigned-clock-rates = <258000000>; 3142 }; 3143 3144 tcu: serial { 3145 compatible = "nvidia,tegra194-tcu"; 3146 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3147 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3148 mbox-names = "rx", "tx"; 3149 }; 3150 3151 thermal-zones { 3152 cpu-thermal { 3153 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3154 status = "disabled"; 3155 }; 3156 3157 gpu-thermal { 3158 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3159 status = "disabled"; 3160 }; 3161 3162 aux-thermal { 3163 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3164 status = "disabled"; 3165 }; 3166 3167 pllx-thermal { 3168 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3169 status = "disabled"; 3170 }; 3171 3172 ao-thermal { 3173 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3174 status = "disabled"; 3175 }; 3176 3177 tj-thermal { 3178 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3179 status = "disabled"; 3180 }; 3181 }; 3182 3183 timer { 3184 compatible = "arm,armv8-timer"; 3185 interrupts = <GIC_PPI 13 3186 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3187 <GIC_PPI 14 3188 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3189 <GIC_PPI 11 3190 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3191 <GIC_PPI 10 3192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3193 interrupt-parent = <&gic>; 3194 always-on; 3195 }; 3196}; 3197