1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra194-clock.h> 3#include <dt-bindings/gpio/tegra194-gpio.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mailbox/tegra186-hsp.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/pinctrl/pinctrl-tegra.h> 8#include <dt-bindings/power/tegra194-powergate.h> 9#include <dt-bindings/reset/tegra194-reset.h> 10#include <dt-bindings/thermal/tegra194-bpmp-thermal.h> 11#include <dt-bindings/memory/tegra194-mc.h> 12 13/ { 14 compatible = "nvidia,tegra194"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* control backbone */ 20 bus@0 { 21 compatible = "simple-bus"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges = <0x0 0x0 0x0 0x40000000>; 25 26 apbmisc: misc@100000 { 27 compatible = "nvidia,tegra194-misc"; 28 reg = <0x00100000 0xf000>, 29 <0x0010f000 0x1000>; 30 }; 31 32 gpio: gpio@2200000 { 33 compatible = "nvidia,tegra194-gpio"; 34 reg-names = "security", "gpio"; 35 reg = <0x2200000 0x10000>, 36 <0x2210000 0x10000>; 37 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 85 #interrupt-cells = <2>; 86 interrupt-controller; 87 #gpio-cells = <2>; 88 gpio-controller; 89 }; 90 91 cbb-noc@2300000 { 92 compatible = "nvidia,tegra194-cbb-noc"; 93 reg = <0x02300000 0x1000>; 94 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 96 nvidia,axi2apb = <&axi2apb>; 97 nvidia,apbmisc = <&apbmisc>; 98 status = "okay"; 99 }; 100 101 axi2apb: axi2apb@2390000 { 102 compatible = "nvidia,tegra194-axi2apb"; 103 reg = <0x2390000 0x1000>, 104 <0x23a0000 0x1000>, 105 <0x23b0000 0x1000>, 106 <0x23c0000 0x1000>, 107 <0x23d0000 0x1000>, 108 <0x23e0000 0x1000>; 109 status = "okay"; 110 }; 111 112 ethernet@2490000 { 113 compatible = "nvidia,tegra194-eqos", 114 "nvidia,tegra186-eqos", 115 "snps,dwc-qos-ethernet-4.10"; 116 reg = <0x02490000 0x10000>; 117 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 118 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>, 119 <&bpmp TEGRA194_CLK_EQOS_AXI>, 120 <&bpmp TEGRA194_CLK_EQOS_RX>, 121 <&bpmp TEGRA194_CLK_EQOS_TX>, 122 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>; 123 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; 124 resets = <&bpmp TEGRA194_RESET_EQOS>; 125 reset-names = "eqos"; 126 interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>, 127 <&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>; 128 interconnect-names = "dma-mem", "write"; 129 iommus = <&smmu TEGRA194_SID_EQOS>; 130 status = "disabled"; 131 132 snps,write-requests = <1>; 133 snps,read-requests = <3>; 134 snps,burst-map = <0x7>; 135 snps,txpbl = <16>; 136 snps,rxpbl = <8>; 137 }; 138 139 gpcdma: dma-controller@2600000 { 140 compatible = "nvidia,tegra194-gpcdma", 141 "nvidia,tegra186-gpcdma"; 142 reg = <0x2600000 0x210000>; 143 resets = <&bpmp TEGRA194_RESET_GPCDMA>; 144 reset-names = "gpcdma"; 145 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 176 #dma-cells = <1>; 177 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 178 dma-coherent; 179 status = "okay"; 180 }; 181 182 aconnect@2900000 { 183 compatible = "nvidia,tegra194-aconnect", 184 "nvidia,tegra210-aconnect"; 185 clocks = <&bpmp TEGRA194_CLK_APE>, 186 <&bpmp TEGRA194_CLK_APB2APE>; 187 clock-names = "ape", "apb2ape"; 188 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 ranges = <0x02900000 0x02900000 0x200000>; 192 status = "disabled"; 193 194 adma: dma-controller@2930000 { 195 compatible = "nvidia,tegra194-adma", 196 "nvidia,tegra186-adma"; 197 reg = <0x02930000 0x20000>; 198 interrupt-parent = <&agic>; 199 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 231 #dma-cells = <1>; 232 clocks = <&bpmp TEGRA194_CLK_AHUB>; 233 clock-names = "d_audio"; 234 status = "disabled"; 235 }; 236 237 agic: interrupt-controller@2a40000 { 238 compatible = "nvidia,tegra194-agic", 239 "nvidia,tegra210-agic"; 240 #interrupt-cells = <3>; 241 interrupt-controller; 242 reg = <0x02a41000 0x1000>, 243 <0x02a42000 0x2000>; 244 interrupts = <GIC_SPI 145 245 (GIC_CPU_MASK_SIMPLE(4) | 246 IRQ_TYPE_LEVEL_HIGH)>; 247 clocks = <&bpmp TEGRA194_CLK_APE>; 248 clock-names = "clk"; 249 status = "disabled"; 250 }; 251 252 tegra_ahub: ahub@2900800 { 253 compatible = "nvidia,tegra194-ahub", 254 "nvidia,tegra186-ahub"; 255 reg = <0x02900800 0x800>; 256 clocks = <&bpmp TEGRA194_CLK_AHUB>; 257 clock-names = "ahub"; 258 assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; 259 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 260 #address-cells = <1>; 261 #size-cells = <1>; 262 ranges = <0x02900800 0x02900800 0x11800>; 263 status = "disabled"; 264 265 tegra_admaif: admaif@290f000 { 266 compatible = "nvidia,tegra194-admaif", 267 "nvidia,tegra186-admaif"; 268 reg = <0x0290f000 0x1000>; 269 dmas = <&adma 1>, <&adma 1>, 270 <&adma 2>, <&adma 2>, 271 <&adma 3>, <&adma 3>, 272 <&adma 4>, <&adma 4>, 273 <&adma 5>, <&adma 5>, 274 <&adma 6>, <&adma 6>, 275 <&adma 7>, <&adma 7>, 276 <&adma 8>, <&adma 8>, 277 <&adma 9>, <&adma 9>, 278 <&adma 10>, <&adma 10>, 279 <&adma 11>, <&adma 11>, 280 <&adma 12>, <&adma 12>, 281 <&adma 13>, <&adma 13>, 282 <&adma 14>, <&adma 14>, 283 <&adma 15>, <&adma 15>, 284 <&adma 16>, <&adma 16>, 285 <&adma 17>, <&adma 17>, 286 <&adma 18>, <&adma 18>, 287 <&adma 19>, <&adma 19>, 288 <&adma 20>, <&adma 20>; 289 dma-names = "rx1", "tx1", 290 "rx2", "tx2", 291 "rx3", "tx3", 292 "rx4", "tx4", 293 "rx5", "tx5", 294 "rx6", "tx6", 295 "rx7", "tx7", 296 "rx8", "tx8", 297 "rx9", "tx9", 298 "rx10", "tx10", 299 "rx11", "tx11", 300 "rx12", "tx12", 301 "rx13", "tx13", 302 "rx14", "tx14", 303 "rx15", "tx15", 304 "rx16", "tx16", 305 "rx17", "tx17", 306 "rx18", "tx18", 307 "rx19", "tx19", 308 "rx20", "tx20"; 309 status = "disabled"; 310 interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, 311 <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; 312 interconnect-names = "dma-mem", "write"; 313 iommus = <&smmu TEGRA194_SID_APE>; 314 }; 315 316 tegra_i2s1: i2s@2901000 { 317 compatible = "nvidia,tegra194-i2s", 318 "nvidia,tegra210-i2s"; 319 reg = <0x2901000 0x100>; 320 clocks = <&bpmp TEGRA194_CLK_I2S1>, 321 <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; 322 clock-names = "i2s", "sync_input"; 323 assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; 324 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 325 assigned-clock-rates = <1536000>; 326 sound-name-prefix = "I2S1"; 327 status = "disabled"; 328 }; 329 330 tegra_i2s2: i2s@2901100 { 331 compatible = "nvidia,tegra194-i2s", 332 "nvidia,tegra210-i2s"; 333 reg = <0x2901100 0x100>; 334 clocks = <&bpmp TEGRA194_CLK_I2S2>, 335 <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; 336 clock-names = "i2s", "sync_input"; 337 assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; 338 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 339 assigned-clock-rates = <1536000>; 340 sound-name-prefix = "I2S2"; 341 status = "disabled"; 342 }; 343 344 tegra_i2s3: i2s@2901200 { 345 compatible = "nvidia,tegra194-i2s", 346 "nvidia,tegra210-i2s"; 347 reg = <0x2901200 0x100>; 348 clocks = <&bpmp TEGRA194_CLK_I2S3>, 349 <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; 350 clock-names = "i2s", "sync_input"; 351 assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; 352 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 353 assigned-clock-rates = <1536000>; 354 sound-name-prefix = "I2S3"; 355 status = "disabled"; 356 }; 357 358 tegra_i2s4: i2s@2901300 { 359 compatible = "nvidia,tegra194-i2s", 360 "nvidia,tegra210-i2s"; 361 reg = <0x2901300 0x100>; 362 clocks = <&bpmp TEGRA194_CLK_I2S4>, 363 <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; 364 clock-names = "i2s", "sync_input"; 365 assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; 366 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 367 assigned-clock-rates = <1536000>; 368 sound-name-prefix = "I2S4"; 369 status = "disabled"; 370 }; 371 372 tegra_i2s5: i2s@2901400 { 373 compatible = "nvidia,tegra194-i2s", 374 "nvidia,tegra210-i2s"; 375 reg = <0x2901400 0x100>; 376 clocks = <&bpmp TEGRA194_CLK_I2S5>, 377 <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; 378 clock-names = "i2s", "sync_input"; 379 assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; 380 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 381 assigned-clock-rates = <1536000>; 382 sound-name-prefix = "I2S5"; 383 status = "disabled"; 384 }; 385 386 tegra_i2s6: i2s@2901500 { 387 compatible = "nvidia,tegra194-i2s", 388 "nvidia,tegra210-i2s"; 389 reg = <0x2901500 0x100>; 390 clocks = <&bpmp TEGRA194_CLK_I2S6>, 391 <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; 392 clock-names = "i2s", "sync_input"; 393 assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; 394 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 395 assigned-clock-rates = <1536000>; 396 sound-name-prefix = "I2S6"; 397 status = "disabled"; 398 }; 399 400 tegra_dmic1: dmic@2904000 { 401 compatible = "nvidia,tegra194-dmic", 402 "nvidia,tegra210-dmic"; 403 reg = <0x2904000 0x100>; 404 clocks = <&bpmp TEGRA194_CLK_DMIC1>; 405 clock-names = "dmic"; 406 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; 407 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 408 assigned-clock-rates = <3072000>; 409 sound-name-prefix = "DMIC1"; 410 status = "disabled"; 411 }; 412 413 tegra_dmic2: dmic@2904100 { 414 compatible = "nvidia,tegra194-dmic", 415 "nvidia,tegra210-dmic"; 416 reg = <0x2904100 0x100>; 417 clocks = <&bpmp TEGRA194_CLK_DMIC2>; 418 clock-names = "dmic"; 419 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; 420 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 421 assigned-clock-rates = <3072000>; 422 sound-name-prefix = "DMIC2"; 423 status = "disabled"; 424 }; 425 426 tegra_dmic3: dmic@2904200 { 427 compatible = "nvidia,tegra194-dmic", 428 "nvidia,tegra210-dmic"; 429 reg = <0x2904200 0x100>; 430 clocks = <&bpmp TEGRA194_CLK_DMIC3>; 431 clock-names = "dmic"; 432 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; 433 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 434 assigned-clock-rates = <3072000>; 435 sound-name-prefix = "DMIC3"; 436 status = "disabled"; 437 }; 438 439 tegra_dmic4: dmic@2904300 { 440 compatible = "nvidia,tegra194-dmic", 441 "nvidia,tegra210-dmic"; 442 reg = <0x2904300 0x100>; 443 clocks = <&bpmp TEGRA194_CLK_DMIC4>; 444 clock-names = "dmic"; 445 assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; 446 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 447 assigned-clock-rates = <3072000>; 448 sound-name-prefix = "DMIC4"; 449 status = "disabled"; 450 }; 451 452 tegra_dspk1: dspk@2905000 { 453 compatible = "nvidia,tegra194-dspk", 454 "nvidia,tegra186-dspk"; 455 reg = <0x2905000 0x100>; 456 clocks = <&bpmp TEGRA194_CLK_DSPK1>; 457 clock-names = "dspk"; 458 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; 459 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 460 assigned-clock-rates = <12288000>; 461 sound-name-prefix = "DSPK1"; 462 status = "disabled"; 463 }; 464 465 tegra_dspk2: dspk@2905100 { 466 compatible = "nvidia,tegra194-dspk", 467 "nvidia,tegra186-dspk"; 468 reg = <0x2905100 0x100>; 469 clocks = <&bpmp TEGRA194_CLK_DSPK2>; 470 clock-names = "dspk"; 471 assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; 472 assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; 473 assigned-clock-rates = <12288000>; 474 sound-name-prefix = "DSPK2"; 475 status = "disabled"; 476 }; 477 478 tegra_sfc1: sfc@2902000 { 479 compatible = "nvidia,tegra194-sfc", 480 "nvidia,tegra210-sfc"; 481 reg = <0x2902000 0x200>; 482 sound-name-prefix = "SFC1"; 483 status = "disabled"; 484 }; 485 486 tegra_sfc2: sfc@2902200 { 487 compatible = "nvidia,tegra194-sfc", 488 "nvidia,tegra210-sfc"; 489 reg = <0x2902200 0x200>; 490 sound-name-prefix = "SFC2"; 491 status = "disabled"; 492 }; 493 494 tegra_sfc3: sfc@2902400 { 495 compatible = "nvidia,tegra194-sfc", 496 "nvidia,tegra210-sfc"; 497 reg = <0x2902400 0x200>; 498 sound-name-prefix = "SFC3"; 499 status = "disabled"; 500 }; 501 502 tegra_sfc4: sfc@2902600 { 503 compatible = "nvidia,tegra194-sfc", 504 "nvidia,tegra210-sfc"; 505 reg = <0x2902600 0x200>; 506 sound-name-prefix = "SFC4"; 507 status = "disabled"; 508 }; 509 510 tegra_mvc1: mvc@290a000 { 511 compatible = "nvidia,tegra194-mvc", 512 "nvidia,tegra210-mvc"; 513 reg = <0x290a000 0x200>; 514 sound-name-prefix = "MVC1"; 515 status = "disabled"; 516 }; 517 518 tegra_mvc2: mvc@290a200 { 519 compatible = "nvidia,tegra194-mvc", 520 "nvidia,tegra210-mvc"; 521 reg = <0x290a200 0x200>; 522 sound-name-prefix = "MVC2"; 523 status = "disabled"; 524 }; 525 526 tegra_amx1: amx@2903000 { 527 compatible = "nvidia,tegra194-amx"; 528 reg = <0x2903000 0x100>; 529 sound-name-prefix = "AMX1"; 530 status = "disabled"; 531 }; 532 533 tegra_amx2: amx@2903100 { 534 compatible = "nvidia,tegra194-amx"; 535 reg = <0x2903100 0x100>; 536 sound-name-prefix = "AMX2"; 537 status = "disabled"; 538 }; 539 540 tegra_amx3: amx@2903200 { 541 compatible = "nvidia,tegra194-amx"; 542 reg = <0x2903200 0x100>; 543 sound-name-prefix = "AMX3"; 544 status = "disabled"; 545 }; 546 547 tegra_amx4: amx@2903300 { 548 compatible = "nvidia,tegra194-amx"; 549 reg = <0x2903300 0x100>; 550 sound-name-prefix = "AMX4"; 551 status = "disabled"; 552 }; 553 554 tegra_adx1: adx@2903800 { 555 compatible = "nvidia,tegra194-adx", 556 "nvidia,tegra210-adx"; 557 reg = <0x2903800 0x100>; 558 sound-name-prefix = "ADX1"; 559 status = "disabled"; 560 }; 561 562 tegra_adx2: adx@2903900 { 563 compatible = "nvidia,tegra194-adx", 564 "nvidia,tegra210-adx"; 565 reg = <0x2903900 0x100>; 566 sound-name-prefix = "ADX2"; 567 status = "disabled"; 568 }; 569 570 tegra_adx3: adx@2903a00 { 571 compatible = "nvidia,tegra194-adx", 572 "nvidia,tegra210-adx"; 573 reg = <0x2903a00 0x100>; 574 sound-name-prefix = "ADX3"; 575 status = "disabled"; 576 }; 577 578 tegra_adx4: adx@2903b00 { 579 compatible = "nvidia,tegra194-adx", 580 "nvidia,tegra210-adx"; 581 reg = <0x2903b00 0x100>; 582 sound-name-prefix = "ADX4"; 583 status = "disabled"; 584 }; 585 586 tegra_ope1: processing-engine@2908000 { 587 compatible = "nvidia,tegra194-ope", 588 "nvidia,tegra210-ope"; 589 reg = <0x2908000 0x100>; 590 #address-cells = <1>; 591 #size-cells = <1>; 592 ranges; 593 sound-name-prefix = "OPE1"; 594 status = "disabled"; 595 596 equalizer@2908100 { 597 compatible = "nvidia,tegra194-peq", 598 "nvidia,tegra210-peq"; 599 reg = <0x2908100 0x100>; 600 }; 601 602 dynamic-range-compressor@2908200 { 603 compatible = "nvidia,tegra194-mbdrc", 604 "nvidia,tegra210-mbdrc"; 605 reg = <0x2908200 0x200>; 606 }; 607 }; 608 609 tegra_amixer: amixer@290bb00 { 610 compatible = "nvidia,tegra194-amixer", 611 "nvidia,tegra210-amixer"; 612 reg = <0x290bb00 0x800>; 613 sound-name-prefix = "MIXER1"; 614 status = "disabled"; 615 }; 616 617 tegra_asrc: asrc@2910000 { 618 compatible = "nvidia,tegra194-asrc", 619 "nvidia,tegra186-asrc"; 620 reg = <0x2910000 0x2000>; 621 sound-name-prefix = "ASRC1"; 622 status = "disabled"; 623 }; 624 }; 625 }; 626 627 pinmux: pinmux@2430000 { 628 compatible = "nvidia,tegra194-pinmux"; 629 reg = <0x2430000 0x17000>, 630 <0xc300000 0x4000>; 631 632 status = "okay"; 633 634 pex_rst_c5_out_state: pex_rst_c5_out { 635 pex_rst { 636 nvidia,pins = "pex_l5_rst_n_pgg1"; 637 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 638 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 639 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 640 nvidia,tristate = <TEGRA_PIN_DISABLE>; 641 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 642 }; 643 }; 644 645 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir { 646 clkreq { 647 nvidia,pins = "pex_l5_clkreq_n_pgg0"; 648 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 649 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 650 nvidia,io-hv = <TEGRA_PIN_ENABLE>; 651 nvidia,tristate = <TEGRA_PIN_DISABLE>; 652 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 653 }; 654 }; 655 }; 656 657 mc: memory-controller@2c00000 { 658 compatible = "nvidia,tegra194-mc"; 659 reg = <0x02c00000 0x10000>, /* MC-SID */ 660 <0x02c10000 0x10000>, /* MC Broadcast*/ 661 <0x02c20000 0x10000>, /* MC0 */ 662 <0x02c30000 0x10000>, /* MC1 */ 663 <0x02c40000 0x10000>, /* MC2 */ 664 <0x02c50000 0x10000>, /* MC3 */ 665 <0x02b80000 0x10000>, /* MC4 */ 666 <0x02b90000 0x10000>, /* MC5 */ 667 <0x02ba0000 0x10000>, /* MC6 */ 668 <0x02bb0000 0x10000>, /* MC7 */ 669 <0x01700000 0x10000>, /* MC8 */ 670 <0x01710000 0x10000>, /* MC9 */ 671 <0x01720000 0x10000>, /* MC10 */ 672 <0x01730000 0x10000>, /* MC11 */ 673 <0x01740000 0x10000>, /* MC12 */ 674 <0x01750000 0x10000>, /* MC13 */ 675 <0x01760000 0x10000>, /* MC14 */ 676 <0x01770000 0x10000>; /* MC15 */ 677 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 678 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 679 "ch11", "ch12", "ch13", "ch14", "ch15"; 680 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 681 #interconnect-cells = <1>; 682 status = "disabled"; 683 684 #address-cells = <2>; 685 #size-cells = <2>; 686 687 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 688 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 689 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 690 691 /* 692 * Bit 39 of addresses passing through the memory 693 * controller selects the XBAR format used when memory 694 * is accessed. This is used to transparently access 695 * memory in the XBAR format used by the discrete GPU 696 * (bit 39 set) or Tegra (bit 39 clear). 697 * 698 * As a consequence, the operating system must ensure 699 * that bit 39 is never used implicitly, for example 700 * via an I/O virtual address mapping of an IOMMU. If 701 * devices require access to the XBAR switch, their 702 * drivers must set this bit explicitly. 703 * 704 * Limit the DMA range for memory clients to [38:0]. 705 */ 706 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 707 708 emc: external-memory-controller@2c60000 { 709 compatible = "nvidia,tegra194-emc"; 710 reg = <0x0 0x02c60000 0x0 0x90000>, 711 <0x0 0x01780000 0x0 0x80000>; 712 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&bpmp TEGRA194_CLK_EMC>; 714 clock-names = "emc"; 715 716 #interconnect-cells = <0>; 717 718 nvidia,bpmp = <&bpmp>; 719 }; 720 }; 721 722 timer@3010000 { 723 compatible = "nvidia,tegra186-timer"; 724 reg = <0x03010000 0x000e0000>; 725 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 735 status = "okay"; 736 }; 737 738 uarta: serial@3100000 { 739 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 740 reg = <0x03100000 0x40>; 741 reg-shift = <2>; 742 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&bpmp TEGRA194_CLK_UARTA>; 744 clock-names = "serial"; 745 resets = <&bpmp TEGRA194_RESET_UARTA>; 746 reset-names = "serial"; 747 status = "disabled"; 748 }; 749 750 uartb: serial@3110000 { 751 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 752 reg = <0x03110000 0x40>; 753 reg-shift = <2>; 754 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 755 clocks = <&bpmp TEGRA194_CLK_UARTB>; 756 clock-names = "serial"; 757 resets = <&bpmp TEGRA194_RESET_UARTB>; 758 reset-names = "serial"; 759 status = "disabled"; 760 }; 761 762 uartd: serial@3130000 { 763 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 764 reg = <0x03130000 0x40>; 765 reg-shift = <2>; 766 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&bpmp TEGRA194_CLK_UARTD>; 768 clock-names = "serial"; 769 resets = <&bpmp TEGRA194_RESET_UARTD>; 770 reset-names = "serial"; 771 status = "disabled"; 772 }; 773 774 uarte: serial@3140000 { 775 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 776 reg = <0x03140000 0x40>; 777 reg-shift = <2>; 778 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&bpmp TEGRA194_CLK_UARTE>; 780 clock-names = "serial"; 781 resets = <&bpmp TEGRA194_RESET_UARTE>; 782 reset-names = "serial"; 783 status = "disabled"; 784 }; 785 786 uartf: serial@3150000 { 787 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 788 reg = <0x03150000 0x40>; 789 reg-shift = <2>; 790 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&bpmp TEGRA194_CLK_UARTF>; 792 clock-names = "serial"; 793 resets = <&bpmp TEGRA194_RESET_UARTF>; 794 reset-names = "serial"; 795 status = "disabled"; 796 }; 797 798 gen1_i2c: i2c@3160000 { 799 compatible = "nvidia,tegra194-i2c"; 800 reg = <0x03160000 0x10000>; 801 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 clocks = <&bpmp TEGRA194_CLK_I2C1>; 805 clock-names = "div-clk"; 806 resets = <&bpmp TEGRA194_RESET_I2C1>; 807 reset-names = "i2c"; 808 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 809 dma-coherent; 810 dmas = <&gpcdma 21>, <&gpcdma 21>; 811 dma-names = "rx", "tx"; 812 status = "disabled"; 813 }; 814 815 uarth: serial@3170000 { 816 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 817 reg = <0x03170000 0x40>; 818 reg-shift = <2>; 819 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&bpmp TEGRA194_CLK_UARTH>; 821 clock-names = "serial"; 822 resets = <&bpmp TEGRA194_RESET_UARTH>; 823 reset-names = "serial"; 824 status = "disabled"; 825 }; 826 827 cam_i2c: i2c@3180000 { 828 compatible = "nvidia,tegra194-i2c"; 829 reg = <0x03180000 0x10000>; 830 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 clocks = <&bpmp TEGRA194_CLK_I2C3>; 834 clock-names = "div-clk"; 835 resets = <&bpmp TEGRA194_RESET_I2C3>; 836 reset-names = "i2c"; 837 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 838 dma-coherent; 839 dmas = <&gpcdma 23>, <&gpcdma 23>; 840 dma-names = "rx", "tx"; 841 status = "disabled"; 842 }; 843 844 /* shares pads with dpaux1 */ 845 dp_aux_ch1_i2c: i2c@3190000 { 846 compatible = "nvidia,tegra194-i2c"; 847 reg = <0x03190000 0x10000>; 848 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 clocks = <&bpmp TEGRA194_CLK_I2C4>; 852 clock-names = "div-clk"; 853 resets = <&bpmp TEGRA194_RESET_I2C4>; 854 reset-names = "i2c"; 855 pinctrl-0 = <&state_dpaux1_i2c>; 856 pinctrl-1 = <&state_dpaux1_off>; 857 pinctrl-names = "default", "idle"; 858 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 859 dma-coherent; 860 dmas = <&gpcdma 26>, <&gpcdma 26>; 861 dma-names = "rx", "tx"; 862 status = "disabled"; 863 }; 864 865 /* shares pads with dpaux0 */ 866 dp_aux_ch0_i2c: i2c@31b0000 { 867 compatible = "nvidia,tegra194-i2c"; 868 reg = <0x031b0000 0x10000>; 869 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 clocks = <&bpmp TEGRA194_CLK_I2C6>; 873 clock-names = "div-clk"; 874 resets = <&bpmp TEGRA194_RESET_I2C6>; 875 reset-names = "i2c"; 876 pinctrl-0 = <&state_dpaux0_i2c>; 877 pinctrl-1 = <&state_dpaux0_off>; 878 pinctrl-names = "default", "idle"; 879 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 880 dma-coherent; 881 dmas = <&gpcdma 30>, <&gpcdma 30>; 882 dma-names = "rx", "tx"; 883 status = "disabled"; 884 }; 885 886 /* shares pads with dpaux2 */ 887 dp_aux_ch2_i2c: i2c@31c0000 { 888 compatible = "nvidia,tegra194-i2c"; 889 reg = <0x031c0000 0x10000>; 890 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 clocks = <&bpmp TEGRA194_CLK_I2C7>; 894 clock-names = "div-clk"; 895 resets = <&bpmp TEGRA194_RESET_I2C7>; 896 reset-names = "i2c"; 897 pinctrl-0 = <&state_dpaux2_i2c>; 898 pinctrl-1 = <&state_dpaux2_off>; 899 pinctrl-names = "default", "idle"; 900 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 901 dma-coherent; 902 dmas = <&gpcdma 27>, <&gpcdma 27>; 903 dma-names = "rx", "tx"; 904 status = "disabled"; 905 }; 906 907 /* shares pads with dpaux3 */ 908 dp_aux_ch3_i2c: i2c@31e0000 { 909 compatible = "nvidia,tegra194-i2c"; 910 reg = <0x031e0000 0x10000>; 911 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 clocks = <&bpmp TEGRA194_CLK_I2C9>; 915 clock-names = "div-clk"; 916 resets = <&bpmp TEGRA194_RESET_I2C9>; 917 reset-names = "i2c"; 918 pinctrl-0 = <&state_dpaux3_i2c>; 919 pinctrl-1 = <&state_dpaux3_off>; 920 pinctrl-names = "default", "idle"; 921 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 922 dma-coherent; 923 dmas = <&gpcdma 31>, <&gpcdma 31>; 924 dma-names = "rx", "tx"; 925 status = "disabled"; 926 }; 927 928 spi@3270000 { 929 compatible = "nvidia,tegra194-qspi"; 930 reg = <0x3270000 0x1000>; 931 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 clocks = <&bpmp TEGRA194_CLK_QSPI0>, 935 <&bpmp TEGRA194_CLK_QSPI0_PM>; 936 clock-names = "qspi", "qspi_out"; 937 resets = <&bpmp TEGRA194_RESET_QSPI0>; 938 reset-names = "qspi"; 939 status = "disabled"; 940 }; 941 942 spi@3300000 { 943 compatible = "nvidia,tegra194-qspi"; 944 reg = <0x3300000 0x1000>; 945 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 clocks = <&bpmp TEGRA194_CLK_QSPI1>, 949 <&bpmp TEGRA194_CLK_QSPI1_PM>; 950 clock-names = "qspi", "qspi_out"; 951 resets = <&bpmp TEGRA194_RESET_QSPI1>; 952 reset-names = "qspi"; 953 status = "disabled"; 954 }; 955 956 pwm1: pwm@3280000 { 957 compatible = "nvidia,tegra194-pwm", 958 "nvidia,tegra186-pwm"; 959 reg = <0x3280000 0x10000>; 960 clocks = <&bpmp TEGRA194_CLK_PWM1>; 961 clock-names = "pwm"; 962 resets = <&bpmp TEGRA194_RESET_PWM1>; 963 reset-names = "pwm"; 964 status = "disabled"; 965 #pwm-cells = <2>; 966 }; 967 968 pwm2: pwm@3290000 { 969 compatible = "nvidia,tegra194-pwm", 970 "nvidia,tegra186-pwm"; 971 reg = <0x3290000 0x10000>; 972 clocks = <&bpmp TEGRA194_CLK_PWM2>; 973 clock-names = "pwm"; 974 resets = <&bpmp TEGRA194_RESET_PWM2>; 975 reset-names = "pwm"; 976 status = "disabled"; 977 #pwm-cells = <2>; 978 }; 979 980 pwm3: pwm@32a0000 { 981 compatible = "nvidia,tegra194-pwm", 982 "nvidia,tegra186-pwm"; 983 reg = <0x32a0000 0x10000>; 984 clocks = <&bpmp TEGRA194_CLK_PWM3>; 985 clock-names = "pwm"; 986 resets = <&bpmp TEGRA194_RESET_PWM3>; 987 reset-names = "pwm"; 988 status = "disabled"; 989 #pwm-cells = <2>; 990 }; 991 992 pwm5: pwm@32c0000 { 993 compatible = "nvidia,tegra194-pwm", 994 "nvidia,tegra186-pwm"; 995 reg = <0x32c0000 0x10000>; 996 clocks = <&bpmp TEGRA194_CLK_PWM5>; 997 clock-names = "pwm"; 998 resets = <&bpmp TEGRA194_RESET_PWM5>; 999 reset-names = "pwm"; 1000 status = "disabled"; 1001 #pwm-cells = <2>; 1002 }; 1003 1004 pwm6: pwm@32d0000 { 1005 compatible = "nvidia,tegra194-pwm", 1006 "nvidia,tegra186-pwm"; 1007 reg = <0x32d0000 0x10000>; 1008 clocks = <&bpmp TEGRA194_CLK_PWM6>; 1009 clock-names = "pwm"; 1010 resets = <&bpmp TEGRA194_RESET_PWM6>; 1011 reset-names = "pwm"; 1012 status = "disabled"; 1013 #pwm-cells = <2>; 1014 }; 1015 1016 pwm7: pwm@32e0000 { 1017 compatible = "nvidia,tegra194-pwm", 1018 "nvidia,tegra186-pwm"; 1019 reg = <0x32e0000 0x10000>; 1020 clocks = <&bpmp TEGRA194_CLK_PWM7>; 1021 clock-names = "pwm"; 1022 resets = <&bpmp TEGRA194_RESET_PWM7>; 1023 reset-names = "pwm"; 1024 status = "disabled"; 1025 #pwm-cells = <2>; 1026 }; 1027 1028 pwm8: pwm@32f0000 { 1029 compatible = "nvidia,tegra194-pwm", 1030 "nvidia,tegra186-pwm"; 1031 reg = <0x32f0000 0x10000>; 1032 clocks = <&bpmp TEGRA194_CLK_PWM8>; 1033 clock-names = "pwm"; 1034 resets = <&bpmp TEGRA194_RESET_PWM8>; 1035 reset-names = "pwm"; 1036 status = "disabled"; 1037 #pwm-cells = <2>; 1038 }; 1039 1040 sdmmc1: mmc@3400000 { 1041 compatible = "nvidia,tegra194-sdhci"; 1042 reg = <0x03400000 0x10000>; 1043 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1045 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1046 clock-names = "sdhci", "tmclk"; 1047 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, 1048 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1049 assigned-clock-parents = 1050 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1051 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1052 resets = <&bpmp TEGRA194_RESET_SDMMC1>; 1053 reset-names = "sdhci"; 1054 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, 1055 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>; 1056 interconnect-names = "dma-mem", "write"; 1057 iommus = <&smmu TEGRA194_SID_SDMMC1>; 1058 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1059 pinctrl-0 = <&sdmmc1_3v3>; 1060 pinctrl-1 = <&sdmmc1_1v8>; 1061 nvidia,pad-autocal-pull-up-offset-3v3-timeout = 1062 <0x07>; 1063 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1064 <0x07>; 1065 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1066 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1067 <0x07>; 1068 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1069 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1070 nvidia,default-tap = <0x9>; 1071 nvidia,default-trim = <0x5>; 1072 sd-uhs-sdr25; 1073 sd-uhs-sdr50; 1074 sd-uhs-ddr50; 1075 sd-uhs-sdr104; 1076 status = "disabled"; 1077 }; 1078 1079 sdmmc3: mmc@3440000 { 1080 compatible = "nvidia,tegra194-sdhci"; 1081 reg = <0x03440000 0x10000>; 1082 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1084 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1085 clock-names = "sdhci", "tmclk"; 1086 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, 1087 <&bpmp TEGRA194_CLK_PLLC4_MUXED>; 1088 assigned-clock-parents = 1089 <&bpmp TEGRA194_CLK_PLLC4_MUXED>, 1090 <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; 1091 resets = <&bpmp TEGRA194_RESET_SDMMC3>; 1092 reset-names = "sdhci"; 1093 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, 1094 <&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>; 1095 interconnect-names = "dma-mem", "write"; 1096 iommus = <&smmu TEGRA194_SID_SDMMC3>; 1097 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 1098 pinctrl-0 = <&sdmmc3_3v3>; 1099 pinctrl-1 = <&sdmmc3_1v8>; 1100 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>; 1101 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>; 1102 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 1103 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1104 <0x07>; 1105 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 1106 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1107 <0x07>; 1108 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 1109 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 1110 nvidia,default-tap = <0x9>; 1111 nvidia,default-trim = <0x5>; 1112 sd-uhs-sdr25; 1113 sd-uhs-sdr50; 1114 sd-uhs-ddr50; 1115 sd-uhs-sdr104; 1116 status = "disabled"; 1117 }; 1118 1119 sdmmc4: mmc@3460000 { 1120 compatible = "nvidia,tegra194-sdhci"; 1121 reg = <0x03460000 0x10000>; 1122 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1124 <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; 1125 clock-names = "sdhci", "tmclk"; 1126 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>, 1127 <&bpmp TEGRA194_CLK_PLLC4>; 1128 assigned-clock-parents = 1129 <&bpmp TEGRA194_CLK_PLLC4>; 1130 resets = <&bpmp TEGRA194_RESET_SDMMC4>; 1131 reset-names = "sdhci"; 1132 interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>, 1133 <&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>; 1134 interconnect-names = "dma-mem", "write"; 1135 iommus = <&smmu TEGRA194_SID_SDMMC4>; 1136 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 1137 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 1138 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 1139 nvidia,pad-autocal-pull-down-offset-1v8-timeout = 1140 <0x0a>; 1141 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 1142 nvidia,pad-autocal-pull-down-offset-3v3-timeout = 1143 <0x0a>; 1144 nvidia,default-tap = <0x8>; 1145 nvidia,default-trim = <0x14>; 1146 nvidia,dqs-trim = <40>; 1147 cap-mmc-highspeed; 1148 mmc-ddr-1_8v; 1149 mmc-hs200-1_8v; 1150 mmc-hs400-1_8v; 1151 mmc-hs400-enhanced-strobe; 1152 supports-cqe; 1153 status = "disabled"; 1154 }; 1155 1156 hda@3510000 { 1157 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda"; 1158 reg = <0x3510000 0x10000>; 1159 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1160 clocks = <&bpmp TEGRA194_CLK_HDA>, 1161 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>, 1162 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>; 1163 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1164 resets = <&bpmp TEGRA194_RESET_HDA>, 1165 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>; 1166 reset-names = "hda", "hda2hdmi"; 1167 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1168 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>, 1169 <&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>; 1170 interconnect-names = "dma-mem", "write"; 1171 iommus = <&smmu TEGRA194_SID_HDA>; 1172 status = "disabled"; 1173 }; 1174 1175 xusb_padctl: padctl@3520000 { 1176 compatible = "nvidia,tegra194-xusb-padctl"; 1177 reg = <0x03520000 0x1000>, 1178 <0x03540000 0x1000>; 1179 reg-names = "padctl", "ao"; 1180 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1181 1182 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>; 1183 reset-names = "padctl"; 1184 1185 status = "disabled"; 1186 1187 pads { 1188 usb2 { 1189 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>; 1190 clock-names = "trk"; 1191 1192 lanes { 1193 usb2-0 { 1194 nvidia,function = "xusb"; 1195 status = "disabled"; 1196 #phy-cells = <0>; 1197 }; 1198 1199 usb2-1 { 1200 nvidia,function = "xusb"; 1201 status = "disabled"; 1202 #phy-cells = <0>; 1203 }; 1204 1205 usb2-2 { 1206 nvidia,function = "xusb"; 1207 status = "disabled"; 1208 #phy-cells = <0>; 1209 }; 1210 1211 usb2-3 { 1212 nvidia,function = "xusb"; 1213 status = "disabled"; 1214 #phy-cells = <0>; 1215 }; 1216 }; 1217 }; 1218 1219 usb3 { 1220 lanes { 1221 usb3-0 { 1222 nvidia,function = "xusb"; 1223 status = "disabled"; 1224 #phy-cells = <0>; 1225 }; 1226 1227 usb3-1 { 1228 nvidia,function = "xusb"; 1229 status = "disabled"; 1230 #phy-cells = <0>; 1231 }; 1232 1233 usb3-2 { 1234 nvidia,function = "xusb"; 1235 status = "disabled"; 1236 #phy-cells = <0>; 1237 }; 1238 1239 usb3-3 { 1240 nvidia,function = "xusb"; 1241 status = "disabled"; 1242 #phy-cells = <0>; 1243 }; 1244 }; 1245 }; 1246 }; 1247 1248 ports { 1249 usb2-0 { 1250 status = "disabled"; 1251 }; 1252 1253 usb2-1 { 1254 status = "disabled"; 1255 }; 1256 1257 usb2-2 { 1258 status = "disabled"; 1259 }; 1260 1261 usb2-3 { 1262 status = "disabled"; 1263 }; 1264 1265 usb3-0 { 1266 status = "disabled"; 1267 }; 1268 1269 usb3-1 { 1270 status = "disabled"; 1271 }; 1272 1273 usb3-2 { 1274 status = "disabled"; 1275 }; 1276 1277 usb3-3 { 1278 status = "disabled"; 1279 }; 1280 }; 1281 }; 1282 1283 usb@3550000 { 1284 compatible = "nvidia,tegra194-xudc"; 1285 reg = <0x03550000 0x8000>, 1286 <0x03558000 0x1000>; 1287 reg-names = "base", "fpci"; 1288 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1289 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>, 1290 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1291 <&bpmp TEGRA194_CLK_XUSB_SS>, 1292 <&bpmp TEGRA194_CLK_XUSB_FS>; 1293 clock-names = "dev", "ss", "ss_src", "fs_src"; 1294 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVR &emc>, 1295 <&mc TEGRA194_MEMORY_CLIENT_XUSB_DEVW &emc>; 1296 interconnect-names = "dma-mem", "write"; 1297 iommus = <&smmu TEGRA194_SID_XUSB_DEV>; 1298 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>, 1299 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1300 power-domain-names = "dev", "ss"; 1301 nvidia,xusb-padctl = <&xusb_padctl>; 1302 status = "disabled"; 1303 }; 1304 1305 usb@3610000 { 1306 compatible = "nvidia,tegra194-xusb"; 1307 reg = <0x03610000 0x40000>, 1308 <0x03600000 0x10000>; 1309 reg-names = "hcd", "fpci"; 1310 1311 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1313 1314 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>, 1315 <&bpmp TEGRA194_CLK_XUSB_FALCON>, 1316 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>, 1317 <&bpmp TEGRA194_CLK_XUSB_SS>, 1318 <&bpmp TEGRA194_CLK_CLK_M>, 1319 <&bpmp TEGRA194_CLK_XUSB_FS>, 1320 <&bpmp TEGRA194_CLK_UTMIPLL>, 1321 <&bpmp TEGRA194_CLK_CLK_M>, 1322 <&bpmp TEGRA194_CLK_PLLE>; 1323 clock-names = "xusb_host", "xusb_falcon_src", 1324 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 1325 "xusb_fs_src", "pll_u_480m", "clk_m", 1326 "pll_e"; 1327 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>, 1328 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>; 1329 interconnect-names = "dma-mem", "write"; 1330 iommus = <&smmu TEGRA194_SID_XUSB_HOST>; 1331 1332 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>, 1333 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>; 1334 power-domain-names = "xusb_host", "xusb_ss"; 1335 1336 nvidia,xusb-padctl = <&xusb_padctl>; 1337 status = "disabled"; 1338 }; 1339 1340 fuse@3820000 { 1341 compatible = "nvidia,tegra194-efuse"; 1342 reg = <0x03820000 0x10000>; 1343 clocks = <&bpmp TEGRA194_CLK_FUSE>; 1344 clock-names = "fuse"; 1345 }; 1346 1347 gic: interrupt-controller@3881000 { 1348 compatible = "arm,gic-400"; 1349 #interrupt-cells = <3>; 1350 interrupt-controller; 1351 reg = <0x03881000 0x1000>, 1352 <0x03882000 0x2000>, 1353 <0x03884000 0x2000>, 1354 <0x03886000 0x2000>; 1355 interrupts = <GIC_PPI 9 1356 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1357 interrupt-parent = <&gic>; 1358 }; 1359 1360 cec@3960000 { 1361 compatible = "nvidia,tegra194-cec"; 1362 reg = <0x03960000 0x10000>; 1363 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1364 clocks = <&bpmp TEGRA194_CLK_CEC>; 1365 clock-names = "cec"; 1366 status = "disabled"; 1367 }; 1368 1369 hte_lic: hardware-timestamp@3aa0000 { 1370 compatible = "nvidia,tegra194-gte-lic"; 1371 reg = <0x3aa0000 0x10000>; 1372 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1373 nvidia,int-threshold = <1>; 1374 nvidia,slices = <11>; 1375 #timestamp-cells = <1>; 1376 status = "okay"; 1377 }; 1378 1379 hsp_top0: hsp@3c00000 { 1380 compatible = "nvidia,tegra194-hsp"; 1381 reg = <0x03c00000 0xa0000>; 1382 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1391 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 1392 "shared3", "shared4", "shared5", "shared6", 1393 "shared7"; 1394 #mbox-cells = <2>; 1395 }; 1396 1397 p2u_hsio_0: phy@3e10000 { 1398 compatible = "nvidia,tegra194-p2u"; 1399 reg = <0x03e10000 0x10000>; 1400 reg-names = "ctl"; 1401 1402 #phy-cells = <0>; 1403 }; 1404 1405 p2u_hsio_1: phy@3e20000 { 1406 compatible = "nvidia,tegra194-p2u"; 1407 reg = <0x03e20000 0x10000>; 1408 reg-names = "ctl"; 1409 1410 #phy-cells = <0>; 1411 }; 1412 1413 p2u_hsio_2: phy@3e30000 { 1414 compatible = "nvidia,tegra194-p2u"; 1415 reg = <0x03e30000 0x10000>; 1416 reg-names = "ctl"; 1417 1418 #phy-cells = <0>; 1419 }; 1420 1421 p2u_hsio_3: phy@3e40000 { 1422 compatible = "nvidia,tegra194-p2u"; 1423 reg = <0x03e40000 0x10000>; 1424 reg-names = "ctl"; 1425 1426 #phy-cells = <0>; 1427 }; 1428 1429 p2u_hsio_4: phy@3e50000 { 1430 compatible = "nvidia,tegra194-p2u"; 1431 reg = <0x03e50000 0x10000>; 1432 reg-names = "ctl"; 1433 1434 #phy-cells = <0>; 1435 }; 1436 1437 p2u_hsio_5: phy@3e60000 { 1438 compatible = "nvidia,tegra194-p2u"; 1439 reg = <0x03e60000 0x10000>; 1440 reg-names = "ctl"; 1441 1442 #phy-cells = <0>; 1443 }; 1444 1445 p2u_hsio_6: phy@3e70000 { 1446 compatible = "nvidia,tegra194-p2u"; 1447 reg = <0x03e70000 0x10000>; 1448 reg-names = "ctl"; 1449 1450 #phy-cells = <0>; 1451 }; 1452 1453 p2u_hsio_7: phy@3e80000 { 1454 compatible = "nvidia,tegra194-p2u"; 1455 reg = <0x03e80000 0x10000>; 1456 reg-names = "ctl"; 1457 1458 #phy-cells = <0>; 1459 }; 1460 1461 p2u_hsio_8: phy@3e90000 { 1462 compatible = "nvidia,tegra194-p2u"; 1463 reg = <0x03e90000 0x10000>; 1464 reg-names = "ctl"; 1465 1466 #phy-cells = <0>; 1467 }; 1468 1469 p2u_hsio_9: phy@3ea0000 { 1470 compatible = "nvidia,tegra194-p2u"; 1471 reg = <0x03ea0000 0x10000>; 1472 reg-names = "ctl"; 1473 1474 #phy-cells = <0>; 1475 }; 1476 1477 p2u_nvhs_0: phy@3eb0000 { 1478 compatible = "nvidia,tegra194-p2u"; 1479 reg = <0x03eb0000 0x10000>; 1480 reg-names = "ctl"; 1481 1482 #phy-cells = <0>; 1483 }; 1484 1485 p2u_nvhs_1: phy@3ec0000 { 1486 compatible = "nvidia,tegra194-p2u"; 1487 reg = <0x03ec0000 0x10000>; 1488 reg-names = "ctl"; 1489 1490 #phy-cells = <0>; 1491 }; 1492 1493 p2u_nvhs_2: phy@3ed0000 { 1494 compatible = "nvidia,tegra194-p2u"; 1495 reg = <0x03ed0000 0x10000>; 1496 reg-names = "ctl"; 1497 1498 #phy-cells = <0>; 1499 }; 1500 1501 p2u_nvhs_3: phy@3ee0000 { 1502 compatible = "nvidia,tegra194-p2u"; 1503 reg = <0x03ee0000 0x10000>; 1504 reg-names = "ctl"; 1505 1506 #phy-cells = <0>; 1507 }; 1508 1509 p2u_nvhs_4: phy@3ef0000 { 1510 compatible = "nvidia,tegra194-p2u"; 1511 reg = <0x03ef0000 0x10000>; 1512 reg-names = "ctl"; 1513 1514 #phy-cells = <0>; 1515 }; 1516 1517 p2u_nvhs_5: phy@3f00000 { 1518 compatible = "nvidia,tegra194-p2u"; 1519 reg = <0x03f00000 0x10000>; 1520 reg-names = "ctl"; 1521 1522 #phy-cells = <0>; 1523 }; 1524 1525 p2u_nvhs_6: phy@3f10000 { 1526 compatible = "nvidia,tegra194-p2u"; 1527 reg = <0x03f10000 0x10000>; 1528 reg-names = "ctl"; 1529 1530 #phy-cells = <0>; 1531 }; 1532 1533 p2u_nvhs_7: phy@3f20000 { 1534 compatible = "nvidia,tegra194-p2u"; 1535 reg = <0x03f20000 0x10000>; 1536 reg-names = "ctl"; 1537 1538 #phy-cells = <0>; 1539 }; 1540 1541 p2u_hsio_10: phy@3f30000 { 1542 compatible = "nvidia,tegra194-p2u"; 1543 reg = <0x03f30000 0x10000>; 1544 reg-names = "ctl"; 1545 1546 #phy-cells = <0>; 1547 }; 1548 1549 p2u_hsio_11: phy@3f40000 { 1550 compatible = "nvidia,tegra194-p2u"; 1551 reg = <0x03f40000 0x10000>; 1552 reg-names = "ctl"; 1553 1554 #phy-cells = <0>; 1555 }; 1556 1557 sce-noc@b600000 { 1558 compatible = "nvidia,tegra194-sce-noc"; 1559 reg = <0xb600000 0x1000>; 1560 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1561 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1562 nvidia,axi2apb = <&axi2apb>; 1563 nvidia,apbmisc = <&apbmisc>; 1564 status = "okay"; 1565 }; 1566 1567 rce-noc@be00000 { 1568 compatible = "nvidia,tegra194-rce-noc"; 1569 reg = <0xbe00000 0x1000>; 1570 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1572 nvidia,axi2apb = <&axi2apb>; 1573 nvidia,apbmisc = <&apbmisc>; 1574 status = "okay"; 1575 }; 1576 1577 hsp_aon: hsp@c150000 { 1578 compatible = "nvidia,tegra194-hsp"; 1579 reg = <0x0c150000 0x90000>; 1580 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1584 /* 1585 * Shared interrupt 0 is routed only to AON/SPE, so 1586 * we only have 4 shared interrupts for the CCPLEX. 1587 */ 1588 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1589 #mbox-cells = <2>; 1590 }; 1591 1592 hte_aon: hardware-timestamp@c1e0000 { 1593 compatible = "nvidia,tegra194-gte-aon"; 1594 reg = <0xc1e0000 0x10000>; 1595 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1596 nvidia,int-threshold = <1>; 1597 nvidia,slices = <3>; 1598 #timestamp-cells = <1>; 1599 status = "okay"; 1600 }; 1601 1602 gen2_i2c: i2c@c240000 { 1603 compatible = "nvidia,tegra194-i2c"; 1604 reg = <0x0c240000 0x10000>; 1605 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1606 #address-cells = <1>; 1607 #size-cells = <0>; 1608 clocks = <&bpmp TEGRA194_CLK_I2C2>; 1609 clock-names = "div-clk"; 1610 resets = <&bpmp TEGRA194_RESET_I2C2>; 1611 reset-names = "i2c"; 1612 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1613 dma-coherent; 1614 dmas = <&gpcdma 22>, <&gpcdma 22>; 1615 dma-names = "rx", "tx"; 1616 status = "disabled"; 1617 }; 1618 1619 gen8_i2c: i2c@c250000 { 1620 compatible = "nvidia,tegra194-i2c"; 1621 reg = <0x0c250000 0x10000>; 1622 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1623 #address-cells = <1>; 1624 #size-cells = <0>; 1625 clocks = <&bpmp TEGRA194_CLK_I2C8>; 1626 clock-names = "div-clk"; 1627 resets = <&bpmp TEGRA194_RESET_I2C8>; 1628 reset-names = "i2c"; 1629 iommus = <&smmu TEGRA194_SID_GPCDMA_0>; 1630 dma-coherent; 1631 dmas = <&gpcdma 0>, <&gpcdma 0>; 1632 dma-names = "rx", "tx"; 1633 status = "disabled"; 1634 }; 1635 1636 uartc: serial@c280000 { 1637 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1638 reg = <0x0c280000 0x40>; 1639 reg-shift = <2>; 1640 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1641 clocks = <&bpmp TEGRA194_CLK_UARTC>; 1642 clock-names = "serial"; 1643 resets = <&bpmp TEGRA194_RESET_UARTC>; 1644 reset-names = "serial"; 1645 status = "disabled"; 1646 }; 1647 1648 uartg: serial@c290000 { 1649 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; 1650 reg = <0x0c290000 0x40>; 1651 reg-shift = <2>; 1652 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1653 clocks = <&bpmp TEGRA194_CLK_UARTG>; 1654 clock-names = "serial"; 1655 resets = <&bpmp TEGRA194_RESET_UARTG>; 1656 reset-names = "serial"; 1657 status = "disabled"; 1658 }; 1659 1660 rtc: rtc@c2a0000 { 1661 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc"; 1662 reg = <0x0c2a0000 0x10000>; 1663 interrupt-parent = <&pmc>; 1664 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1665 clocks = <&bpmp TEGRA194_CLK_CLK_32K>; 1666 clock-names = "rtc"; 1667 status = "disabled"; 1668 }; 1669 1670 gpio_aon: gpio@c2f0000 { 1671 compatible = "nvidia,tegra194-gpio-aon"; 1672 reg-names = "security", "gpio"; 1673 reg = <0xc2f0000 0x1000>, 1674 <0xc2f1000 0x1000>; 1675 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1676 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1677 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1679 gpio-controller; 1680 #gpio-cells = <2>; 1681 interrupt-controller; 1682 #interrupt-cells = <2>; 1683 }; 1684 1685 pwm4: pwm@c340000 { 1686 compatible = "nvidia,tegra194-pwm", 1687 "nvidia,tegra186-pwm"; 1688 reg = <0xc340000 0x10000>; 1689 clocks = <&bpmp TEGRA194_CLK_PWM4>; 1690 clock-names = "pwm"; 1691 resets = <&bpmp TEGRA194_RESET_PWM4>; 1692 reset-names = "pwm"; 1693 status = "disabled"; 1694 #pwm-cells = <2>; 1695 }; 1696 1697 pmc: pmc@c360000 { 1698 compatible = "nvidia,tegra194-pmc"; 1699 reg = <0x0c360000 0x10000>, 1700 <0x0c370000 0x10000>, 1701 <0x0c380000 0x10000>, 1702 <0x0c390000 0x10000>, 1703 <0x0c3a0000 0x10000>; 1704 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1705 1706 #interrupt-cells = <2>; 1707 interrupt-controller; 1708 sdmmc1_3v3: sdmmc1-3v3 { 1709 pins = "sdmmc1-hv"; 1710 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1711 }; 1712 1713 sdmmc1_1v8: sdmmc1-1v8 { 1714 pins = "sdmmc1-hv"; 1715 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1716 }; 1717 sdmmc3_3v3: sdmmc3-3v3 { 1718 pins = "sdmmc3-hv"; 1719 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 1720 }; 1721 1722 sdmmc3_1v8: sdmmc3-1v8 { 1723 pins = "sdmmc3-hv"; 1724 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 1725 }; 1726 1727 }; 1728 1729 aon-noc@c600000 { 1730 compatible = "nvidia,tegra194-aon-noc"; 1731 reg = <0xc600000 0x1000>; 1732 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1734 nvidia,apbmisc = <&apbmisc>; 1735 status = "okay"; 1736 }; 1737 1738 bpmp-noc@d600000 { 1739 compatible = "nvidia,tegra194-bpmp-noc"; 1740 reg = <0xd600000 0x1000>; 1741 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1743 nvidia,axi2apb = <&axi2apb>; 1744 nvidia,apbmisc = <&apbmisc>; 1745 status = "okay"; 1746 }; 1747 1748 iommu@10000000 { 1749 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1750 reg = <0x10000000 0x800000>; 1751 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1812 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1813 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1814 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1815 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1816 stream-match-mask = <0x7f80>; 1817 #global-interrupts = <1>; 1818 #iommu-cells = <1>; 1819 1820 nvidia,memory-controller = <&mc>; 1821 status = "disabled"; 1822 }; 1823 1824 smmu: iommu@12000000 { 1825 compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; 1826 reg = <0x12000000 0x800000>, 1827 <0x11000000 0x800000>; 1828 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1894 stream-match-mask = <0x7f80>; 1895 #global-interrupts = <2>; 1896 #iommu-cells = <1>; 1897 1898 nvidia,memory-controller = <&mc>; 1899 status = "okay"; 1900 }; 1901 1902 host1x@13e00000 { 1903 compatible = "nvidia,tegra194-host1x"; 1904 reg = <0x13e00000 0x10000>, 1905 <0x13e10000 0x10000>; 1906 reg-names = "hypervisor", "vm"; 1907 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1909 interrupt-names = "syncpt", "host1x"; 1910 clocks = <&bpmp TEGRA194_CLK_HOST1X>; 1911 clock-names = "host1x"; 1912 resets = <&bpmp TEGRA194_RESET_HOST1X>; 1913 reset-names = "host1x"; 1914 1915 #address-cells = <1>; 1916 #size-cells = <1>; 1917 1918 ranges = <0x14800000 0x14800000 0x02800000>; 1919 interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>; 1920 interconnect-names = "dma-mem"; 1921 iommus = <&smmu TEGRA194_SID_HOST1X>; 1922 1923 /* Context isolation domains */ 1924 iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>, 1925 <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>, 1926 <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>, 1927 <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>, 1928 <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>, 1929 <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>, 1930 <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>, 1931 <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>; 1932 1933 nvdec@15140000 { 1934 compatible = "nvidia,tegra194-nvdec"; 1935 reg = <0x15140000 0x00040000>; 1936 clocks = <&bpmp TEGRA194_CLK_NVDEC1>; 1937 clock-names = "nvdec"; 1938 resets = <&bpmp TEGRA194_RESET_NVDEC1>; 1939 reset-names = "nvdec"; 1940 1941 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>; 1942 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>, 1943 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>, 1944 <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>; 1945 interconnect-names = "dma-mem", "read-1", "write"; 1946 iommus = <&smmu TEGRA194_SID_NVDEC1>; 1947 dma-coherent; 1948 1949 nvidia,host1x-class = <0xf5>; 1950 }; 1951 1952 display-hub@15200000 { 1953 compatible = "nvidia,tegra194-display"; 1954 reg = <0x15200000 0x00040000>; 1955 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>, 1956 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>, 1957 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>, 1958 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>, 1959 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>, 1960 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>, 1961 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>; 1962 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", 1963 "wgrp3", "wgrp4", "wgrp5"; 1964 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>, 1965 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>; 1966 clock-names = "disp", "hub"; 1967 status = "disabled"; 1968 1969 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1970 1971 #address-cells = <1>; 1972 #size-cells = <1>; 1973 1974 ranges = <0x15200000 0x15200000 0x40000>; 1975 1976 display@15200000 { 1977 compatible = "nvidia,tegra194-dc"; 1978 reg = <0x15200000 0x10000>; 1979 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1980 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>; 1981 clock-names = "dc"; 1982 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>; 1983 reset-names = "dc"; 1984 1985 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 1986 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 1987 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 1988 interconnect-names = "dma-mem", "read-1"; 1989 1990 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 1991 nvidia,head = <0>; 1992 }; 1993 1994 display@15210000 { 1995 compatible = "nvidia,tegra194-dc"; 1996 reg = <0x15210000 0x10000>; 1997 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1998 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>; 1999 clock-names = "dc"; 2000 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>; 2001 reset-names = "dc"; 2002 2003 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>; 2004 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2005 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2006 interconnect-names = "dma-mem", "read-1"; 2007 2008 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2009 nvidia,head = <1>; 2010 }; 2011 2012 display@15220000 { 2013 compatible = "nvidia,tegra194-dc"; 2014 reg = <0x15220000 0x10000>; 2015 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2016 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>; 2017 clock-names = "dc"; 2018 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>; 2019 reset-names = "dc"; 2020 2021 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2022 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2023 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2024 interconnect-names = "dma-mem", "read-1"; 2025 2026 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2027 nvidia,head = <2>; 2028 }; 2029 2030 display@15230000 { 2031 compatible = "nvidia,tegra194-dc"; 2032 reg = <0x15230000 0x10000>; 2033 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 2034 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>; 2035 clock-names = "dc"; 2036 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>; 2037 reset-names = "dc"; 2038 2039 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>; 2040 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, 2041 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; 2042 interconnect-names = "dma-mem", "read-1"; 2043 2044 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; 2045 nvidia,head = <3>; 2046 }; 2047 }; 2048 2049 vic@15340000 { 2050 compatible = "nvidia,tegra194-vic"; 2051 reg = <0x15340000 0x00040000>; 2052 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 2053 clocks = <&bpmp TEGRA194_CLK_VIC>; 2054 clock-names = "vic"; 2055 resets = <&bpmp TEGRA194_RESET_VIC>; 2056 reset-names = "vic"; 2057 2058 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>; 2059 interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>, 2060 <&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>; 2061 interconnect-names = "dma-mem", "write"; 2062 iommus = <&smmu TEGRA194_SID_VIC>; 2063 dma-coherent; 2064 }; 2065 2066 nvjpg@15380000 { 2067 compatible = "nvidia,tegra194-nvjpg"; 2068 reg = <0x15380000 0x40000>; 2069 clocks = <&bpmp TEGRA194_CLK_NVJPG>; 2070 clock-names = "nvjpg"; 2071 resets = <&bpmp TEGRA194_RESET_NVJPG>; 2072 reset-names = "nvjpg"; 2073 2074 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>; 2075 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>, 2076 <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>; 2077 interconnect-names = "dma-mem", "write"; 2078 iommus = <&smmu TEGRA194_SID_NVJPG>; 2079 dma-coherent; 2080 }; 2081 2082 nvdec@15480000 { 2083 compatible = "nvidia,tegra194-nvdec"; 2084 reg = <0x15480000 0x00040000>; 2085 clocks = <&bpmp TEGRA194_CLK_NVDEC>; 2086 clock-names = "nvdec"; 2087 resets = <&bpmp TEGRA194_RESET_NVDEC>; 2088 reset-names = "nvdec"; 2089 2090 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>; 2091 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>, 2092 <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>, 2093 <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>; 2094 interconnect-names = "dma-mem", "read-1", "write"; 2095 iommus = <&smmu TEGRA194_SID_NVDEC>; 2096 dma-coherent; 2097 2098 nvidia,host1x-class = <0xf0>; 2099 }; 2100 2101 nvenc@154c0000 { 2102 compatible = "nvidia,tegra194-nvenc"; 2103 reg = <0x154c0000 0x40000>; 2104 clocks = <&bpmp TEGRA194_CLK_NVENC>; 2105 clock-names = "nvenc"; 2106 resets = <&bpmp TEGRA194_RESET_NVENC>; 2107 reset-names = "nvenc"; 2108 2109 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>; 2110 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>, 2111 <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>, 2112 <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>; 2113 interconnect-names = "dma-mem", "read-1", "write"; 2114 iommus = <&smmu TEGRA194_SID_NVENC>; 2115 dma-coherent; 2116 2117 nvidia,host1x-class = <0x21>; 2118 }; 2119 2120 dpaux0: dpaux@155c0000 { 2121 compatible = "nvidia,tegra194-dpaux"; 2122 reg = <0x155c0000 0x10000>; 2123 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 2124 clocks = <&bpmp TEGRA194_CLK_DPAUX>, 2125 <&bpmp TEGRA194_CLK_PLLDP>; 2126 clock-names = "dpaux", "parent"; 2127 resets = <&bpmp TEGRA194_RESET_DPAUX>; 2128 reset-names = "dpaux"; 2129 status = "disabled"; 2130 2131 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2132 2133 state_dpaux0_aux: pinmux-aux { 2134 groups = "dpaux-io"; 2135 function = "aux"; 2136 }; 2137 2138 state_dpaux0_i2c: pinmux-i2c { 2139 groups = "dpaux-io"; 2140 function = "i2c"; 2141 }; 2142 2143 state_dpaux0_off: pinmux-off { 2144 groups = "dpaux-io"; 2145 function = "off"; 2146 }; 2147 2148 i2c-bus { 2149 #address-cells = <1>; 2150 #size-cells = <0>; 2151 }; 2152 }; 2153 2154 dpaux1: dpaux@155d0000 { 2155 compatible = "nvidia,tegra194-dpaux"; 2156 reg = <0x155d0000 0x10000>; 2157 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2158 clocks = <&bpmp TEGRA194_CLK_DPAUX1>, 2159 <&bpmp TEGRA194_CLK_PLLDP>; 2160 clock-names = "dpaux", "parent"; 2161 resets = <&bpmp TEGRA194_RESET_DPAUX1>; 2162 reset-names = "dpaux"; 2163 status = "disabled"; 2164 2165 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2166 2167 state_dpaux1_aux: pinmux-aux { 2168 groups = "dpaux-io"; 2169 function = "aux"; 2170 }; 2171 2172 state_dpaux1_i2c: pinmux-i2c { 2173 groups = "dpaux-io"; 2174 function = "i2c"; 2175 }; 2176 2177 state_dpaux1_off: pinmux-off { 2178 groups = "dpaux-io"; 2179 function = "off"; 2180 }; 2181 2182 i2c-bus { 2183 #address-cells = <1>; 2184 #size-cells = <0>; 2185 }; 2186 }; 2187 2188 dpaux2: dpaux@155e0000 { 2189 compatible = "nvidia,tegra194-dpaux"; 2190 reg = <0x155e0000 0x10000>; 2191 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 2192 clocks = <&bpmp TEGRA194_CLK_DPAUX2>, 2193 <&bpmp TEGRA194_CLK_PLLDP>; 2194 clock-names = "dpaux", "parent"; 2195 resets = <&bpmp TEGRA194_RESET_DPAUX2>; 2196 reset-names = "dpaux"; 2197 status = "disabled"; 2198 2199 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2200 2201 state_dpaux2_aux: pinmux-aux { 2202 groups = "dpaux-io"; 2203 function = "aux"; 2204 }; 2205 2206 state_dpaux2_i2c: pinmux-i2c { 2207 groups = "dpaux-io"; 2208 function = "i2c"; 2209 }; 2210 2211 state_dpaux2_off: pinmux-off { 2212 groups = "dpaux-io"; 2213 function = "off"; 2214 }; 2215 2216 i2c-bus { 2217 #address-cells = <1>; 2218 #size-cells = <0>; 2219 }; 2220 }; 2221 2222 dpaux3: dpaux@155f0000 { 2223 compatible = "nvidia,tegra194-dpaux"; 2224 reg = <0x155f0000 0x10000>; 2225 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 2226 clocks = <&bpmp TEGRA194_CLK_DPAUX3>, 2227 <&bpmp TEGRA194_CLK_PLLDP>; 2228 clock-names = "dpaux", "parent"; 2229 resets = <&bpmp TEGRA194_RESET_DPAUX3>; 2230 reset-names = "dpaux"; 2231 status = "disabled"; 2232 2233 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2234 2235 state_dpaux3_aux: pinmux-aux { 2236 groups = "dpaux-io"; 2237 function = "aux"; 2238 }; 2239 2240 state_dpaux3_i2c: pinmux-i2c { 2241 groups = "dpaux-io"; 2242 function = "i2c"; 2243 }; 2244 2245 state_dpaux3_off: pinmux-off { 2246 groups = "dpaux-io"; 2247 function = "off"; 2248 }; 2249 2250 i2c-bus { 2251 #address-cells = <1>; 2252 #size-cells = <0>; 2253 }; 2254 }; 2255 2256 nvenc@15a80000 { 2257 compatible = "nvidia,tegra194-nvenc"; 2258 reg = <0x15a80000 0x00040000>; 2259 clocks = <&bpmp TEGRA194_CLK_NVENC1>; 2260 clock-names = "nvenc"; 2261 resets = <&bpmp TEGRA194_RESET_NVENC1>; 2262 reset-names = "nvenc"; 2263 2264 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>; 2265 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>, 2266 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>, 2267 <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>; 2268 interconnect-names = "dma-mem", "read-1", "write"; 2269 iommus = <&smmu TEGRA194_SID_NVENC1>; 2270 dma-coherent; 2271 2272 nvidia,host1x-class = <0x22>; 2273 }; 2274 2275 sor0: sor@15b00000 { 2276 compatible = "nvidia,tegra194-sor"; 2277 reg = <0x15b00000 0x40000>; 2278 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 2279 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>, 2280 <&bpmp TEGRA194_CLK_SOR0_OUT>, 2281 <&bpmp TEGRA194_CLK_PLLD>, 2282 <&bpmp TEGRA194_CLK_PLLDP>, 2283 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2284 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>; 2285 clock-names = "sor", "out", "parent", "dp", "safe", 2286 "pad"; 2287 resets = <&bpmp TEGRA194_RESET_SOR0>; 2288 reset-names = "sor"; 2289 pinctrl-0 = <&state_dpaux0_aux>; 2290 pinctrl-1 = <&state_dpaux0_i2c>; 2291 pinctrl-2 = <&state_dpaux0_off>; 2292 pinctrl-names = "aux", "i2c", "off"; 2293 status = "disabled"; 2294 2295 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2296 nvidia,interface = <0>; 2297 }; 2298 2299 sor1: sor@15b40000 { 2300 compatible = "nvidia,tegra194-sor"; 2301 reg = <0x15b40000 0x40000>; 2302 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 2303 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, 2304 <&bpmp TEGRA194_CLK_SOR1_OUT>, 2305 <&bpmp TEGRA194_CLK_PLLD2>, 2306 <&bpmp TEGRA194_CLK_PLLDP>, 2307 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2308 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>; 2309 clock-names = "sor", "out", "parent", "dp", "safe", 2310 "pad"; 2311 resets = <&bpmp TEGRA194_RESET_SOR1>; 2312 reset-names = "sor"; 2313 pinctrl-0 = <&state_dpaux1_aux>; 2314 pinctrl-1 = <&state_dpaux1_i2c>; 2315 pinctrl-2 = <&state_dpaux1_off>; 2316 pinctrl-names = "aux", "i2c", "off"; 2317 status = "disabled"; 2318 2319 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2320 nvidia,interface = <1>; 2321 }; 2322 2323 sor2: sor@15b80000 { 2324 compatible = "nvidia,tegra194-sor"; 2325 reg = <0x15b80000 0x40000>; 2326 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2327 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>, 2328 <&bpmp TEGRA194_CLK_SOR2_OUT>, 2329 <&bpmp TEGRA194_CLK_PLLD3>, 2330 <&bpmp TEGRA194_CLK_PLLDP>, 2331 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2332 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>; 2333 clock-names = "sor", "out", "parent", "dp", "safe", 2334 "pad"; 2335 resets = <&bpmp TEGRA194_RESET_SOR2>; 2336 reset-names = "sor"; 2337 pinctrl-0 = <&state_dpaux2_aux>; 2338 pinctrl-1 = <&state_dpaux2_i2c>; 2339 pinctrl-2 = <&state_dpaux2_off>; 2340 pinctrl-names = "aux", "i2c", "off"; 2341 status = "disabled"; 2342 2343 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2344 nvidia,interface = <2>; 2345 }; 2346 2347 sor3: sor@15bc0000 { 2348 compatible = "nvidia,tegra194-sor"; 2349 reg = <0x15bc0000 0x40000>; 2350 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 2351 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>, 2352 <&bpmp TEGRA194_CLK_SOR3_OUT>, 2353 <&bpmp TEGRA194_CLK_PLLD4>, 2354 <&bpmp TEGRA194_CLK_PLLDP>, 2355 <&bpmp TEGRA194_CLK_SOR_SAFE>, 2356 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>; 2357 clock-names = "sor", "out", "parent", "dp", "safe", 2358 "pad"; 2359 resets = <&bpmp TEGRA194_RESET_SOR3>; 2360 reset-names = "sor"; 2361 pinctrl-0 = <&state_dpaux3_aux>; 2362 pinctrl-1 = <&state_dpaux3_i2c>; 2363 pinctrl-2 = <&state_dpaux3_off>; 2364 pinctrl-names = "aux", "i2c", "off"; 2365 status = "disabled"; 2366 2367 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>; 2368 nvidia,interface = <3>; 2369 }; 2370 }; 2371 2372 gpu@17000000 { 2373 compatible = "nvidia,gv11b"; 2374 reg = <0x17000000 0x1000000>, 2375 <0x18000000 0x1000000>; 2376 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2377 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2378 interrupt-names = "stall", "nonstall"; 2379 clocks = <&bpmp TEGRA194_CLK_GPCCLK>, 2380 <&bpmp TEGRA194_CLK_GPU_PWR>, 2381 <&bpmp TEGRA194_CLK_FUSE>; 2382 clock-names = "gpu", "pwr", "fuse"; 2383 resets = <&bpmp TEGRA194_RESET_GPU>; 2384 reset-names = "gpu"; 2385 dma-coherent; 2386 2387 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; 2388 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVL1R &emc>, 2389 <&mc TEGRA194_MEMORY_CLIENT_NVL1RHP &emc>, 2390 <&mc TEGRA194_MEMORY_CLIENT_NVL1W &emc>, 2391 <&mc TEGRA194_MEMORY_CLIENT_NVL2R &emc>, 2392 <&mc TEGRA194_MEMORY_CLIENT_NVL2RHP &emc>, 2393 <&mc TEGRA194_MEMORY_CLIENT_NVL2W &emc>, 2394 <&mc TEGRA194_MEMORY_CLIENT_NVL3R &emc>, 2395 <&mc TEGRA194_MEMORY_CLIENT_NVL3RHP &emc>, 2396 <&mc TEGRA194_MEMORY_CLIENT_NVL3W &emc>, 2397 <&mc TEGRA194_MEMORY_CLIENT_NVL4R &emc>, 2398 <&mc TEGRA194_MEMORY_CLIENT_NVL4RHP &emc>, 2399 <&mc TEGRA194_MEMORY_CLIENT_NVL4W &emc>; 2400 interconnect-names = "dma-mem", "read-0-hp", "write-0", 2401 "read-1", "read-1-hp", "write-1", 2402 "read-2", "read-2-hp", "write-2", 2403 "read-3", "read-3-hp", "write-3"; 2404 }; 2405 }; 2406 2407 pcie@14100000 { 2408 compatible = "nvidia,tegra194-pcie"; 2409 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2410 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 2411 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 2412 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2413 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2414 reg-names = "appl", "config", "atu_dma", "dbi"; 2415 2416 status = "disabled"; 2417 2418 #address-cells = <3>; 2419 #size-cells = <2>; 2420 device_type = "pci"; 2421 num-lanes = <1>; 2422 linux,pci-domain = <1>; 2423 2424 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>; 2425 clock-names = "core"; 2426 2427 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>, 2428 <&bpmp TEGRA194_RESET_PEX0_CORE_1>; 2429 reset-names = "apb", "core"; 2430 2431 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2432 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2433 interrupt-names = "intr", "msi"; 2434 2435 #interrupt-cells = <1>; 2436 interrupt-map-mask = <0 0 0 0>; 2437 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 2438 2439 nvidia,bpmp = <&bpmp 1>; 2440 2441 nvidia,aspm-cmrt-us = <60>; 2442 nvidia,aspm-pwr-on-t-us = <20>; 2443 nvidia,aspm-l0s-entrance-latency-us = <3>; 2444 2445 bus-range = <0x0 0xff>; 2446 2447 ranges = <0x43000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2448 <0x02000000 0x0 0x40000000 0x12 0x30000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2449 <0x01000000 0x0 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2450 2451 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE1R &emc>, 2452 <&mc TEGRA194_MEMORY_CLIENT_PCIE1W &emc>; 2453 interconnect-names = "dma-mem", "write"; 2454 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE1 0x1000>; 2455 iommu-map-mask = <0x0>; 2456 dma-coherent; 2457 }; 2458 2459 pcie@14120000 { 2460 compatible = "nvidia,tegra194-pcie"; 2461 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2462 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 2463 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 2464 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2465 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2466 reg-names = "appl", "config", "atu_dma", "dbi"; 2467 2468 status = "disabled"; 2469 2470 #address-cells = <3>; 2471 #size-cells = <2>; 2472 device_type = "pci"; 2473 num-lanes = <1>; 2474 linux,pci-domain = <2>; 2475 2476 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>; 2477 clock-names = "core"; 2478 2479 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>, 2480 <&bpmp TEGRA194_RESET_PEX0_CORE_2>; 2481 reset-names = "apb", "core"; 2482 2483 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2484 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2485 interrupt-names = "intr", "msi"; 2486 2487 #interrupt-cells = <1>; 2488 interrupt-map-mask = <0 0 0 0>; 2489 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2490 2491 nvidia,bpmp = <&bpmp 2>; 2492 2493 nvidia,aspm-cmrt-us = <60>; 2494 nvidia,aspm-pwr-on-t-us = <20>; 2495 nvidia,aspm-l0s-entrance-latency-us = <3>; 2496 2497 bus-range = <0x0 0xff>; 2498 2499 ranges = <0x43000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2500 <0x02000000 0x0 0x40000000 0x12 0x70000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB - 64 KiB) */ 2501 <0x01000000 0x0 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2502 2503 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE2AR &emc>, 2504 <&mc TEGRA194_MEMORY_CLIENT_PCIE2AW &emc>; 2505 interconnect-names = "dma-mem", "write"; 2506 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE2 0x1000>; 2507 iommu-map-mask = <0x0>; 2508 dma-coherent; 2509 }; 2510 2511 pcie@14140000 { 2512 compatible = "nvidia,tegra194-pcie"; 2513 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>; 2514 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 2515 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 2516 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2517 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2518 reg-names = "appl", "config", "atu_dma", "dbi"; 2519 2520 status = "disabled"; 2521 2522 #address-cells = <3>; 2523 #size-cells = <2>; 2524 device_type = "pci"; 2525 num-lanes = <1>; 2526 linux,pci-domain = <3>; 2527 2528 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>; 2529 clock-names = "core"; 2530 2531 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>, 2532 <&bpmp TEGRA194_RESET_PEX0_CORE_3>; 2533 reset-names = "apb", "core"; 2534 2535 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2536 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2537 interrupt-names = "intr", "msi"; 2538 2539 #interrupt-cells = <1>; 2540 interrupt-map-mask = <0 0 0 0>; 2541 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 2542 2543 nvidia,bpmp = <&bpmp 3>; 2544 2545 nvidia,aspm-cmrt-us = <60>; 2546 nvidia,aspm-pwr-on-t-us = <20>; 2547 nvidia,aspm-l0s-entrance-latency-us = <3>; 2548 2549 bus-range = <0x0 0xff>; 2550 2551 ranges = <0x43000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000>, /* prefetchable memory (768 MiB) */ 2552 <0x02000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x0fff0000>, /* non-prefetchable memory (256 MiB + 64 KiB) */ 2553 <0x01000000 0x0 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2554 2555 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE3R &emc>, 2556 <&mc TEGRA194_MEMORY_CLIENT_PCIE3W &emc>; 2557 interconnect-names = "dma-mem", "write"; 2558 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE3 0x1000>; 2559 iommu-map-mask = <0x0>; 2560 dma-coherent; 2561 }; 2562 2563 pcie@14160000 { 2564 compatible = "nvidia,tegra194-pcie"; 2565 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2566 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2567 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 2568 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2569 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2570 reg-names = "appl", "config", "atu_dma", "dbi"; 2571 2572 status = "disabled"; 2573 2574 #address-cells = <3>; 2575 #size-cells = <2>; 2576 device_type = "pci"; 2577 num-lanes = <4>; 2578 linux,pci-domain = <4>; 2579 2580 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2581 clock-names = "core"; 2582 2583 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2584 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2585 reset-names = "apb", "core"; 2586 2587 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2588 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2589 interrupt-names = "intr", "msi"; 2590 2591 #interrupt-cells = <1>; 2592 interrupt-map-mask = <0 0 0 0>; 2593 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 2594 2595 nvidia,bpmp = <&bpmp 4>; 2596 2597 nvidia,aspm-cmrt-us = <60>; 2598 nvidia,aspm-pwr-on-t-us = <20>; 2599 nvidia,aspm-l0s-entrance-latency-us = <3>; 2600 2601 bus-range = <0x0 0xff>; 2602 2603 ranges = <0x43000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2604 <0x02000000 0x0 0x40000000 0x17 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2605 <0x01000000 0x0 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2606 2607 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2608 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2609 interconnect-names = "dma-mem", "write"; 2610 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2611 iommu-map-mask = <0x0>; 2612 dma-coherent; 2613 }; 2614 2615 pcie@14180000 { 2616 compatible = "nvidia,tegra194-pcie"; 2617 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2618 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2619 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 2620 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2621 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2622 reg-names = "appl", "config", "atu_dma", "dbi"; 2623 2624 status = "disabled"; 2625 2626 #address-cells = <3>; 2627 #size-cells = <2>; 2628 device_type = "pci"; 2629 num-lanes = <8>; 2630 linux,pci-domain = <0>; 2631 2632 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2633 clock-names = "core"; 2634 2635 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2636 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2637 reset-names = "apb", "core"; 2638 2639 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2640 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2641 interrupt-names = "intr", "msi"; 2642 2643 #interrupt-cells = <1>; 2644 interrupt-map-mask = <0 0 0 0>; 2645 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 2646 2647 nvidia,bpmp = <&bpmp 0>; 2648 2649 nvidia,aspm-cmrt-us = <60>; 2650 nvidia,aspm-pwr-on-t-us = <20>; 2651 nvidia,aspm-l0s-entrance-latency-us = <3>; 2652 2653 bus-range = <0x0 0xff>; 2654 2655 ranges = <0x43000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2656 <0x02000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2657 <0x01000000 0x0 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2658 2659 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2660 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2661 interconnect-names = "dma-mem", "write"; 2662 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2663 iommu-map-mask = <0x0>; 2664 dma-coherent; 2665 }; 2666 2667 pcie@141a0000 { 2668 compatible = "nvidia,tegra194-pcie"; 2669 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2670 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2671 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 2672 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2673 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */ 2674 reg-names = "appl", "config", "atu_dma", "dbi"; 2675 2676 status = "disabled"; 2677 2678 #address-cells = <3>; 2679 #size-cells = <2>; 2680 device_type = "pci"; 2681 num-lanes = <8>; 2682 linux,pci-domain = <5>; 2683 2684 pinctrl-names = "default"; 2685 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 2686 2687 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2688 clock-names = "core"; 2689 2690 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2691 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2692 reset-names = "apb", "core"; 2693 2694 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 2695 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 2696 interrupt-names = "intr", "msi"; 2697 2698 nvidia,bpmp = <&bpmp 5>; 2699 2700 #interrupt-cells = <1>; 2701 interrupt-map-mask = <0 0 0 0>; 2702 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 2703 2704 nvidia,aspm-cmrt-us = <60>; 2705 nvidia,aspm-pwr-on-t-us = <20>; 2706 nvidia,aspm-l0s-entrance-latency-us = <3>; 2707 2708 bus-range = <0x0 0xff>; 2709 2710 ranges = <0x43000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000>, /* prefetchable memory (13 GiB) */ 2711 <0x02000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xbfff0000>, /* non-prefetchable memory (3 GiB - 64 KiB) */ 2712 <0x01000000 0x0 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64 KiB) */ 2713 2714 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2715 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2716 interconnect-names = "dma-mem", "write"; 2717 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2718 iommu-map-mask = <0x0>; 2719 dma-coherent; 2720 }; 2721 2722 pcie-ep@14160000 { 2723 compatible = "nvidia,tegra194-pcie-ep"; 2724 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; 2725 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 2726 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2727 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2728 <0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2729 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2730 2731 status = "disabled"; 2732 2733 num-lanes = <4>; 2734 num-ib-windows = <2>; 2735 num-ob-windows = <8>; 2736 2737 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>; 2738 clock-names = "core"; 2739 2740 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>, 2741 <&bpmp TEGRA194_RESET_PEX0_CORE_4>; 2742 reset-names = "apb", "core"; 2743 2744 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2745 interrupt-names = "intr"; 2746 2747 nvidia,bpmp = <&bpmp 4>; 2748 2749 nvidia,aspm-cmrt-us = <60>; 2750 nvidia,aspm-pwr-on-t-us = <20>; 2751 nvidia,aspm-l0s-entrance-latency-us = <3>; 2752 2753 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, 2754 <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; 2755 interconnect-names = "dma-mem", "write"; 2756 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE4 0x1000>; 2757 iommu-map-mask = <0x0>; 2758 dma-coherent; 2759 }; 2760 2761 pcie-ep@14180000 { 2762 compatible = "nvidia,tegra194-pcie-ep"; 2763 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 2764 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 2765 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2766 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2767 <0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2768 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2769 2770 status = "disabled"; 2771 2772 num-lanes = <8>; 2773 num-ib-windows = <2>; 2774 num-ob-windows = <8>; 2775 2776 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 2777 clock-names = "core"; 2778 2779 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 2780 <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 2781 reset-names = "apb", "core"; 2782 2783 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2784 interrupt-names = "intr"; 2785 2786 nvidia,bpmp = <&bpmp 0>; 2787 2788 nvidia,aspm-cmrt-us = <60>; 2789 nvidia,aspm-pwr-on-t-us = <20>; 2790 nvidia,aspm-l0s-entrance-latency-us = <3>; 2791 2792 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, 2793 <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; 2794 interconnect-names = "dma-mem", "write"; 2795 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE0 0x1000>; 2796 iommu-map-mask = <0x0>; 2797 dma-coherent; 2798 }; 2799 2800 pcie-ep@141a0000 { 2801 compatible = "nvidia,tegra194-pcie-ep"; 2802 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 2803 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 2804 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 2805 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 2806 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 2807 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 2808 2809 status = "disabled"; 2810 2811 num-lanes = <8>; 2812 num-ib-windows = <2>; 2813 num-ob-windows = <8>; 2814 2815 pinctrl-names = "default"; 2816 pinctrl-0 = <&clkreq_c5_bi_dir_state>; 2817 2818 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 2819 clock-names = "core"; 2820 2821 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 2822 <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 2823 reset-names = "apb", "core"; 2824 2825 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 2826 interrupt-names = "intr"; 2827 2828 nvidia,bpmp = <&bpmp 5>; 2829 2830 nvidia,aspm-cmrt-us = <60>; 2831 nvidia,aspm-pwr-on-t-us = <20>; 2832 nvidia,aspm-l0s-entrance-latency-us = <3>; 2833 2834 interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, 2835 <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; 2836 interconnect-names = "dma-mem", "write"; 2837 iommu-map = <0x0 &smmu TEGRA194_SID_PCIE5 0x1000>; 2838 iommu-map-mask = <0x0>; 2839 dma-coherent; 2840 }; 2841 2842 sram@40000000 { 2843 compatible = "nvidia,tegra194-sysram", "mmio-sram"; 2844 reg = <0x0 0x40000000 0x0 0x50000>; 2845 #address-cells = <1>; 2846 #size-cells = <1>; 2847 ranges = <0x0 0x0 0x40000000 0x50000>; 2848 no-memory-wc; 2849 2850 cpu_bpmp_tx: sram@4e000 { 2851 reg = <0x4e000 0x1000>; 2852 label = "cpu-bpmp-tx"; 2853 pool; 2854 }; 2855 2856 cpu_bpmp_rx: sram@4f000 { 2857 reg = <0x4f000 0x1000>; 2858 label = "cpu-bpmp-rx"; 2859 pool; 2860 }; 2861 }; 2862 2863 bpmp: bpmp { 2864 compatible = "nvidia,tegra186-bpmp"; 2865 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 2866 TEGRA_HSP_DB_MASTER_BPMP>; 2867 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 2868 #clock-cells = <1>; 2869 #reset-cells = <1>; 2870 #power-domain-cells = <1>; 2871 interconnects = <&mc TEGRA194_MEMORY_CLIENT_BPMPR &emc>, 2872 <&mc TEGRA194_MEMORY_CLIENT_BPMPW &emc>, 2873 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>, 2874 <&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>; 2875 interconnect-names = "read", "write", "dma-mem", "dma-write"; 2876 iommus = <&smmu TEGRA194_SID_BPMP>; 2877 2878 bpmp_i2c: i2c { 2879 compatible = "nvidia,tegra186-bpmp-i2c"; 2880 nvidia,bpmp-bus-id = <5>; 2881 #address-cells = <1>; 2882 #size-cells = <0>; 2883 }; 2884 2885 bpmp_thermal: thermal { 2886 compatible = "nvidia,tegra186-bpmp-thermal"; 2887 #thermal-sensor-cells = <1>; 2888 }; 2889 }; 2890 2891 cpus { 2892 compatible = "nvidia,tegra194-ccplex"; 2893 nvidia,bpmp = <&bpmp>; 2894 #address-cells = <1>; 2895 #size-cells = <0>; 2896 2897 cpu0_0: cpu@0 { 2898 compatible = "nvidia,tegra194-carmel"; 2899 device_type = "cpu"; 2900 reg = <0x000>; 2901 enable-method = "psci"; 2902 i-cache-size = <131072>; 2903 i-cache-line-size = <64>; 2904 i-cache-sets = <512>; 2905 d-cache-size = <65536>; 2906 d-cache-line-size = <64>; 2907 d-cache-sets = <256>; 2908 next-level-cache = <&l2c_0>; 2909 }; 2910 2911 cpu0_1: cpu@1 { 2912 compatible = "nvidia,tegra194-carmel"; 2913 device_type = "cpu"; 2914 reg = <0x001>; 2915 enable-method = "psci"; 2916 i-cache-size = <131072>; 2917 i-cache-line-size = <64>; 2918 i-cache-sets = <512>; 2919 d-cache-size = <65536>; 2920 d-cache-line-size = <64>; 2921 d-cache-sets = <256>; 2922 next-level-cache = <&l2c_0>; 2923 }; 2924 2925 cpu1_0: cpu@100 { 2926 compatible = "nvidia,tegra194-carmel"; 2927 device_type = "cpu"; 2928 reg = <0x100>; 2929 enable-method = "psci"; 2930 i-cache-size = <131072>; 2931 i-cache-line-size = <64>; 2932 i-cache-sets = <512>; 2933 d-cache-size = <65536>; 2934 d-cache-line-size = <64>; 2935 d-cache-sets = <256>; 2936 next-level-cache = <&l2c_1>; 2937 }; 2938 2939 cpu1_1: cpu@101 { 2940 compatible = "nvidia,tegra194-carmel"; 2941 device_type = "cpu"; 2942 reg = <0x101>; 2943 enable-method = "psci"; 2944 i-cache-size = <131072>; 2945 i-cache-line-size = <64>; 2946 i-cache-sets = <512>; 2947 d-cache-size = <65536>; 2948 d-cache-line-size = <64>; 2949 d-cache-sets = <256>; 2950 next-level-cache = <&l2c_1>; 2951 }; 2952 2953 cpu2_0: cpu@200 { 2954 compatible = "nvidia,tegra194-carmel"; 2955 device_type = "cpu"; 2956 reg = <0x200>; 2957 enable-method = "psci"; 2958 i-cache-size = <131072>; 2959 i-cache-line-size = <64>; 2960 i-cache-sets = <512>; 2961 d-cache-size = <65536>; 2962 d-cache-line-size = <64>; 2963 d-cache-sets = <256>; 2964 next-level-cache = <&l2c_2>; 2965 }; 2966 2967 cpu2_1: cpu@201 { 2968 compatible = "nvidia,tegra194-carmel"; 2969 device_type = "cpu"; 2970 reg = <0x201>; 2971 enable-method = "psci"; 2972 i-cache-size = <131072>; 2973 i-cache-line-size = <64>; 2974 i-cache-sets = <512>; 2975 d-cache-size = <65536>; 2976 d-cache-line-size = <64>; 2977 d-cache-sets = <256>; 2978 next-level-cache = <&l2c_2>; 2979 }; 2980 2981 cpu3_0: cpu@300 { 2982 compatible = "nvidia,tegra194-carmel"; 2983 device_type = "cpu"; 2984 reg = <0x300>; 2985 enable-method = "psci"; 2986 i-cache-size = <131072>; 2987 i-cache-line-size = <64>; 2988 i-cache-sets = <512>; 2989 d-cache-size = <65536>; 2990 d-cache-line-size = <64>; 2991 d-cache-sets = <256>; 2992 next-level-cache = <&l2c_3>; 2993 }; 2994 2995 cpu3_1: cpu@301 { 2996 compatible = "nvidia,tegra194-carmel"; 2997 device_type = "cpu"; 2998 reg = <0x301>; 2999 enable-method = "psci"; 3000 i-cache-size = <131072>; 3001 i-cache-line-size = <64>; 3002 i-cache-sets = <512>; 3003 d-cache-size = <65536>; 3004 d-cache-line-size = <64>; 3005 d-cache-sets = <256>; 3006 next-level-cache = <&l2c_3>; 3007 }; 3008 3009 cpu-map { 3010 cluster0 { 3011 core0 { 3012 cpu = <&cpu0_0>; 3013 }; 3014 3015 core1 { 3016 cpu = <&cpu0_1>; 3017 }; 3018 }; 3019 3020 cluster1 { 3021 core0 { 3022 cpu = <&cpu1_0>; 3023 }; 3024 3025 core1 { 3026 cpu = <&cpu1_1>; 3027 }; 3028 }; 3029 3030 cluster2 { 3031 core0 { 3032 cpu = <&cpu2_0>; 3033 }; 3034 3035 core1 { 3036 cpu = <&cpu2_1>; 3037 }; 3038 }; 3039 3040 cluster3 { 3041 core0 { 3042 cpu = <&cpu3_0>; 3043 }; 3044 3045 core1 { 3046 cpu = <&cpu3_1>; 3047 }; 3048 }; 3049 }; 3050 3051 l2c_0: l2-cache0 { 3052 cache-size = <2097152>; 3053 cache-line-size = <64>; 3054 cache-sets = <2048>; 3055 next-level-cache = <&l3c>; 3056 }; 3057 3058 l2c_1: l2-cache1 { 3059 cache-size = <2097152>; 3060 cache-line-size = <64>; 3061 cache-sets = <2048>; 3062 next-level-cache = <&l3c>; 3063 }; 3064 3065 l2c_2: l2-cache2 { 3066 cache-size = <2097152>; 3067 cache-line-size = <64>; 3068 cache-sets = <2048>; 3069 next-level-cache = <&l3c>; 3070 }; 3071 3072 l2c_3: l2-cache3 { 3073 cache-size = <2097152>; 3074 cache-line-size = <64>; 3075 cache-sets = <2048>; 3076 next-level-cache = <&l3c>; 3077 }; 3078 3079 l3c: l3-cache { 3080 cache-size = <4194304>; 3081 cache-line-size = <64>; 3082 cache-sets = <4096>; 3083 }; 3084 }; 3085 3086 pmu { 3087 compatible = "nvidia,carmel-pmu"; 3088 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 3089 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 3090 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 3091 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 3092 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 3095 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 3096 interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1 3097 &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>; 3098 }; 3099 3100 psci { 3101 compatible = "arm,psci-1.0"; 3102 status = "okay"; 3103 method = "smc"; 3104 }; 3105 3106 sound { 3107 status = "disabled"; 3108 3109 clocks = <&bpmp TEGRA194_CLK_PLLA>, 3110 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3111 clock-names = "pll_a", "plla_out0"; 3112 assigned-clocks = <&bpmp TEGRA194_CLK_PLLA>, 3113 <&bpmp TEGRA194_CLK_PLLA_OUT0>, 3114 <&bpmp TEGRA194_CLK_AUD_MCLK>; 3115 assigned-clock-parents = <0>, 3116 <&bpmp TEGRA194_CLK_PLLA>, 3117 <&bpmp TEGRA194_CLK_PLLA_OUT0>; 3118 /* 3119 * PLLA supports dynamic ramp. Below initial rate is chosen 3120 * for this to work and oscillate between base rates required 3121 * for 8x and 11.025x sample rate streams. 3122 */ 3123 assigned-clock-rates = <258000000>; 3124 }; 3125 3126 tcu: serial { 3127 compatible = "nvidia,tegra194-tcu"; 3128 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 3129 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 3130 mbox-names = "rx", "tx"; 3131 }; 3132 3133 thermal-zones { 3134 cpu-thermal { 3135 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_CPU>; 3136 status = "disabled"; 3137 }; 3138 3139 gpu-thermal { 3140 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_GPU>; 3141 status = "disabled"; 3142 }; 3143 3144 aux-thermal { 3145 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AUX>; 3146 status = "disabled"; 3147 }; 3148 3149 pllx-thermal { 3150 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_PLLX>; 3151 status = "disabled"; 3152 }; 3153 3154 ao-thermal { 3155 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_AO>; 3156 status = "disabled"; 3157 }; 3158 3159 tj-thermal { 3160 thermal-sensors = <&{/bpmp/thermal} TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>; 3161 status = "disabled"; 3162 }; 3163 }; 3164 3165 timer { 3166 compatible = "arm,armv8-timer"; 3167 interrupts = <GIC_PPI 13 3168 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3169 <GIC_PPI 14 3170 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3171 <GIC_PPI 11 3172 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3173 <GIC_PPI 10 3174 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3175 interrupt-parent = <&gic>; 3176 always-on; 3177 }; 3178}; 3179