Revision tags: v6.6.25, v6.6.24, v6.6.23 |
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#
cfdca115 |
| 13-Feb-2024 |
Nícolas F. R. A. Prado <nfraprado@collabora.com> |
arm64: dts: mediatek: mt8186: Add missing xhci clock to usb controllers
[ Upstream commit 1af98c3e53da5a8f627855cecd68b017e753ffd3 ]
The mtu3 usb controllers don't list the xhci clock, though they
arm64: dts: mediatek: mt8186: Add missing xhci clock to usb controllers
[ Upstream commit 1af98c3e53da5a8f627855cecd68b017e753ffd3 ]
The mtu3 usb controllers don't list the xhci clock, though they require it, and thus rely on the bootloader leaving it on in order to work.
When booting with the upstream arm64 defconfig, the usb controllers will defer probe until modules have loaded since they have an indirect dependency on CONFIG_MTK_CMDQ, which is configured as a module. However at the point where modules are loaded, unused clocks are also disabled, causing the usb controllers to probe without the xhci clock enabled and fail to probe:
mtu3 11201000.usb: clks of sts1 are not stable! mtu3 11201000.usb: device enable failed -110 mtu3 11201000.usb: mtu3 hw init failed:-110 mtu3 11201000.usb: failed to initialize gadget mtu3: probe of 11201000.usb failed with error -110
(and same for the one at 11281000)
Add the missing clock for the usb controllers so that they can successfully probe without relying on the bootloader state.
Fixes: f6c3e61c5486 ("arm64: dts: mediatek: mt8186: Add MTU3 nodes") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20240213-mt8186-ssusb-domain-clk-fix-v2-2-1f981d35f3fd@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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#
8781c3f4 |
| 13-Feb-2024 |
Nícolas F. R. A. Prado <nfraprado@collabora.com> |
arm64: dts: mediatek: mt8186: Add missing clocks to ssusb power domains
[ Upstream commit a00d4a98af44e025891e97c490b2545368a25e08 ]
The ssusb power domains currently don't list any clocks, despite
arm64: dts: mediatek: mt8186: Add missing clocks to ssusb power domains
[ Upstream commit a00d4a98af44e025891e97c490b2545368a25e08 ]
The ssusb power domains currently don't list any clocks, despite depending on some, and thus rely on the bootloader leaving the required clocks on in order to work.
When booting with the upstream arm64 defconfig, the power domain controller will defer probe until modules have loaded since it has an indirect dependency on CONFIG_MTK_CMDQ, which is configured as a module. However at the point where modules are loaded, unused clocks are also disabled, causing the ssusb domains to fail to be enabled and consequently the controller to fail probe:
mtk-power-controller 10006000.syscon:power-controller: /soc/syscon@10006000/power-controller/power-domain@4: failed to power on domain: -110 mtk-power-controller: probe of 10006000.syscon:power-controller failed with error -110
Add the missing clocks for the ssusb power domains so that they can successfully probe without relying on the bootloader state.
Fixes: d9e43c1e7a38 ("arm64: dts: mt8186: Add power domains controller") Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20240213-mt8186-ssusb-domain-clk-fix-v2-1-1f981d35f3fd@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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Revision tags: v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9 |
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#
b5d11a01 |
| 28-Dec-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
arm64: dts: mediatek: mt8186: fix VENC power domain clocks
[ Upstream commit 09860910c589a3bb3b5268ff6f704cf6b18ada73 ]
The larb clock is in fact a subsys clock, so it must be prefixed by 'subsys-'
arm64: dts: mediatek: mt8186: fix VENC power domain clocks
[ Upstream commit 09860910c589a3bb3b5268ff6f704cf6b18ada73 ]
The larb clock is in fact a subsys clock, so it must be prefixed by 'subsys-' to be correctly identified in the driver.
Fixes: d9e43c1e7a38 ("arm64: dts: mt8186: Add power domains controller") Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20231228113245.174706-6-eugen.hristev@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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Revision tags: v6.6.8, v6.6.7, v6.6.6, v6.6.5 |
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#
f8fa25bf |
| 04-Dec-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
arm64: dts: mediatek: mt8186: fix address warning for ADSP mailboxes
[ Upstream commit 840e341bed3c4331061031dc9db0aff04abafb4b ]
Fix warnings reported by dtbs_check :
arch/arm64/boot/dts/mediatek
arm64: dts: mediatek: mt8186: fix address warning for ADSP mailboxes
[ Upstream commit 840e341bed3c4331061031dc9db0aff04abafb4b ]
Fix warnings reported by dtbs_check :
arch/arm64/boot/dts/mediatek/mt8186.dtsi:1163.35-1168.5: Warning (simple_bus_reg): /soc/mailbox@10686000: simple-bus unit address format error, expected "10686100" arch/arm64/boot/dts/mediatek/mt8186.dtsi:1170.35-1175.5: Warning (simple_bus_reg): /soc/mailbox@10687000: simple-bus unit address format error, expected "10687100"
by having the right bus address as node name.
Fixes: 379cf0e639ae ("arm64: dts: mediatek: mt8186: Add ADSP mailbox nodes") Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Link: https://lore.kernel.org/r/20231204135533.21327-1-eugen.hristev@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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Revision tags: v6.6.4 |
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#
9bd3a188 |
| 30-Nov-2023 |
Chen-Yu Tsai <wenst@chromium.org> |
arm64: dts: mediatek: mt8186: Fix alias prefix for ovl_2l0
[ Upstream commit 6ed159e499bc2ebedf94c9086244220824e71672 ]
The alias prefix for ovl_2l (2 layer overlay) is "ovl-2l", not "ovl_2l".
Fix
arm64: dts: mediatek: mt8186: Fix alias prefix for ovl_2l0
[ Upstream commit 6ed159e499bc2ebedf94c9086244220824e71672 ]
The alias prefix for ovl_2l (2 layer overlay) is "ovl-2l", not "ovl_2l".
Fix this.
Fixes: 7e07d3322de2 ("arm64: dts: mediatek: mt8186: Add display nodes") Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20231130074032.913511-4-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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Revision tags: v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6 |
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#
b9cc1708 |
| 05-Oct-2023 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt8186: Change gpu speedbin nvmem cell name
commit 59fa1e51ba54e1f513985a8177969b62973f7fd5 upstream.
MT8186's GPU speedbin value must be interpreted, or the value will not be
arm64: dts: mediatek: mt8186: Change gpu speedbin nvmem cell name
commit 59fa1e51ba54e1f513985a8177969b62973f7fd5 upstream.
MT8186's GPU speedbin value must be interpreted, or the value will not be meaningful. Use the correct "gpu-speedbin" nvmem cell name for the GPU speedbin to allow triggering the cell info fixup handler, hence feeding the right speedbin number to the users.
Cc: stable@vger.kernel.org Fixes: 263d2fd02afc ("arm64: dts: mediatek: mt8186: Add GPU speed bin NVMEM cells") Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20231005151150.355536-1-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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#
b6eccbcb |
| 05-Oct-2023 |
Eugen Hristev <eugen.hristev@collabora.com> |
arm64: dts: mediatek: mt8186: fix clock names for power domains
commit 9adf7580f6d498a5839e02fa1d1535e934364602 upstream.
Clocks for each power domain are split into big categories: pd clocks and s
arm64: dts: mediatek: mt8186: fix clock names for power domains
commit 9adf7580f6d498a5839e02fa1d1535e934364602 upstream.
Clocks for each power domain are split into big categories: pd clocks and subsys clocks. According to the binding, all clocks which have a dash '-' in their name are treated as subsys clocks, and must be placed at the end of the list. The other clocks which are pd clocks must come first. Fixed the naming and the placing of all clocks in the power domains. For the avoidance of doubt, prefixed all subsys clocks with the 'subsys' prefix. The binding does not enforce strict clock names, the driver uses them in bulk, only making a difference for pd clocks vs subsys clocks.
The above problem appears to be trivial, however, it leads to incorrect power up and power down sequence of the power domains, because some clocks will be mistakenly taken for subsys clocks and viceversa. One consequence is the fact that if the DIS power domain goes power down and power back up during the boot process, when it comes back up, there are still transactions left on the bus which makes the display inoperable.
Some of the clocks for the DIS power domain were wrongly using '_' instead of '-', which again made these clocks being treated as pd clocks instead of subsys clocks.
Cc: stable@vger.kernel.org Fixes: d9e43c1e7a38 ("arm64: dts: mt8186: Add power domains controller") Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20231005103041.352478-1-eugen.hristev@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33 |
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#
f38ea593 |
| 09-Jun-2023 |
Chen-Yu Tsai <wenst@chromium.org> |
arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scaling
Add the GPU's OPP table. This is from the downstream ChromeOS kernel, adapted to the new upstream opp-supported-hw binning format.
arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scaling
Add the GPU's OPP table. This is from the downstream ChromeOS kernel, adapted to the new upstream opp-supported-hw binning format. Also add dynamic-power-coefficient for the GPU.
Also add label for mfg1 power domain. This is to be used at the board level to add a regulator supply for the power domain.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230609072906.2784594-5-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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#
263d2fd0 |
| 09-Jun-2023 |
Chen-Yu Tsai <wenst@chromium.org> |
arm64: dts: mediatek: mt8186: Add GPU speed bin NVMEM cells
On the MT8186, the chip is binned for different GPU voltages at the highest OPPs. The binning value is stored in the efuse.
Add the NVMEM
arm64: dts: mediatek: mt8186: Add GPU speed bin NVMEM cells
On the MT8186, the chip is binned for different GPU voltages at the highest OPPs. The binning value is stored in the efuse.
Add the NVMEM cell, and tie it to the GPU.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230609072906.2784594-4-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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#
8f4ed8fc |
| 09-Jun-2023 |
Chen-Yu Tsai <wenst@chromium.org> |
arm64: dts: mediatek: mt8186: Wire up CPU frequency/voltage scaling
This adds clocks, dynamic power coefficients, and OPP tables for the CPU cores, so that everything required at the SoC level for C
arm64: dts: mediatek: mt8186: Wire up CPU frequency/voltage scaling
This adds clocks, dynamic power coefficients, and OPP tables for the CPU cores, so that everything required at the SoC level for CPU freqency and voltage scaling is available.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230609072906.2784594-3-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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#
32dfbc03 |
| 09-Jun-2023 |
Chen-Yu Tsai <wenst@chromium.org> |
arm64: dts: mediatek: mt8186: Add CCI node and CCI OPP table
Add a device node for the CCI (cache coherent interconnect) and an OPP table for it. The OPP table was taken from the downstream ChromeOS
arm64: dts: mediatek: mt8186: Add CCI node and CCI OPP table
Add a device node for the CCI (cache coherent interconnect) and an OPP table for it. The OPP table was taken from the downstream ChromeOS kernel.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230609072906.2784594-2-wenst@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Revision tags: v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3 |
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#
492061bf |
| 21-Apr-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: mediatek: add missing cache properties
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like:
mt7622-rfb1.dtb: l2-cache: 'cache-uni
arm64: dts: mediatek: add missing cache properties
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like:
mt7622-rfb1.dtb: l2-cache: 'cache-unified' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230421223157.115367-1-krzysztof.kozlowski@linaro.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Revision tags: v6.1.25, v6.1.24, v6.1.23, v6.1.22 |
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#
7e07d332 |
| 23-Mar-2023 |
Allen-KH Cheng <allen-kh.cheng@mediatek.com> |
arm64: dts: mediatek: mt8186: Add display nodes
Add display nodes and the GCE (Global Command Engine) properties to the display nodes in order to enable the usage of the CMDQ (Command Queue), which
arm64: dts: mediatek: mt8186: Add display nodes
Add display nodes and the GCE (Global Command Engine) properties to the display nodes in order to enable the usage of the CMDQ (Command Queue), which is required for operating the display.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230324021258.15863-7-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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#
41218847 |
| 23-Mar-2023 |
Allen-KH Cheng <allen-kh.cheng@mediatek.com> |
arm64: dts: mediatek: mt8186: Add GCE node
Add the Global Command Engine (GCE) node for MT8186 SoC
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regn
arm64: dts: mediatek: mt8186: Add GCE node
Add the Global Command Engine (GCE) node for MT8186 SoC
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230324021258.15863-6-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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#
4dad4f32 |
| 23-Mar-2023 |
Allen-KH Cheng <allen-kh.cheng@mediatek.com> |
arm64: dts: mediatek: mt8186: Add ADSP node
Add ADSP node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delre
arm64: dts: mediatek: mt8186: Add ADSP node
Add ADSP node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230324021258.15863-5-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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#
36cfc08f |
| 23-Mar-2023 |
Allen-KH Cheng <allen-kh.cheng@mediatek.com> |
arm64: dts: mediatek: mt8186: Add SPMI node
Add SPMI node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delre
arm64: dts: mediatek: mt8186: Add SPMI node
Add SPMI node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230324021258.15863-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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#
f6c3e61c |
| 23-Mar-2023 |
Allen-KH Cheng <allen-kh.cheng@mediatek.com> |
arm64: dts: mediatek: mt8186: Add MTU3 nodes
Add MTU3 nodes for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Ang
arm64: dts: mediatek: mt8186: Add MTU3 nodes
Add MTU3 nodes for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230324021258.15863-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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#
f5430284 |
| 11-Apr-2023 |
Yong Wu <yong.wu@mediatek.com> |
arm64: dts: mt8186: Add dma-ranges for the parent "soc" node
Prepare for the MM nodes whose dma-ranges(iova range) is 16GB.
Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: AngeloGioacchi
arm64: dts: mt8186: Add dma-ranges for the parent "soc" node
Prepare for the MM nodes whose dma-ranges(iova range) is 16GB.
Signed-off-by: Yong Wu <yong.wu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230411093144.2690-15-yong.wu@mediatek.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
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Revision tags: v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15 |
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#
ee63f414 |
| 01-Mar-2023 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt8186: Add GPU node
Add a GPU node for MT8186 SoC but keep it disabled.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-
arm64: dts: mediatek: mt8186: Add GPU node
Add a GPU node for MT8186 SoC but keep it disabled.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230301095523.428461-18-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Revision tags: v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78 |
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#
e5e96162 |
| 07-Nov-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mediatek: mt8186: Fix watchdog compatible
MT8186's watchdog embeds a reset controller and needs only the mediatek,mt8186-wdt compatible string as the MT6589 one is there for watchdogs th
arm64: dts: mediatek: mt8186: Fix watchdog compatible
MT8186's watchdog embeds a reset controller and needs only the mediatek,mt8186-wdt compatible string as the MT6589 one is there for watchdogs that don't have any reset controller capability.
Fixes: 2e78620b1350 ("arm64: dts: Add MediaTek MT8186 dts and evaluation board and Makefile") Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Co-developed-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20221108033209.22751-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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f3ca1580 |
| 26-Jan-2023 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mt8186: Change idle states names to reflect actual function
The names of the idle states are misleading being this a single cluster SoC, a cluster-off idle state is impossible!
After so
arm64: dts: mt8186: Change idle states names to reflect actual function
The names of the idle states are misleading being this a single cluster SoC, a cluster-off idle state is impossible!
After some research in ATF, it emerged that the cpu-off state is in reality putting CPUs in retention state, while the cluster-off one is turning off the CPUs.
Summarizing renaming: - cpu-off -> cpu-retention - cluster-off -> cpu-off
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230126103526.417039-6-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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1c473804 |
| 26-Jan-2023 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
arm64: dts: mt8186: Fix CPU map for single-cluster SoC
MT8186 features the ARM DynamIQ technology and combines both two Cortex-A76 (big) and six Cortex-A55 (LITTLE) CPUs in one cluster: fix the CPU
arm64: dts: mt8186: Fix CPU map for single-cluster SoC
MT8186 features the ARM DynamIQ technology and combines both two Cortex-A76 (big) and six Cortex-A55 (LITTLE) CPUs in one cluster: fix the CPU map to reflect that.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Fixes: 2e78620b1350 ("arm64: dts: Add MediaTek MT8186 dts and evaluation board and Makefile") Link: https://lore.kernel.org/r/20230126103526.417039-4-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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90e75e82 |
| 18-Jan-2023 |
Allen-KH Cheng <allen-kh.cheng@mediatek.com> |
arm64: dts: mediatek: mt8186: Add DPI node
Add DPI node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloG
arm64: dts: mediatek: mt8186: Add DPI node
Add DPI node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230118091829.755-8-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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18942d29 |
| 18-Jan-2023 |
Allen-KH Cheng <allen-kh.cheng@mediatek.com> |
arm64: dts: mediatek: mt8186: Add audio controller node
Add audio controller node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno
arm64: dts: mediatek: mt8186: Add audio controller node
Add audio controller node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230118091829.755-7-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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379cf0e6 |
| 18-Jan-2023 |
Allen-KH Cheng <allen-kh.cheng@mediatek.com> |
arm64: dts: mediatek: mt8186: Add ADSP mailbox nodes
Add ADSP mailbox node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angel
arm64: dts: mediatek: mt8186: Add ADSP mailbox nodes
Add ADSP mailbox node for MT8186 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230118091829.755-5-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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