1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/gce/mt8186-gce.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/memory/mt8186-memory-port.h> 12#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 13#include <dt-bindings/power/mt8186-power.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/reset/mt8186-resets.h> 16 17/ { 18 compatible = "mediatek,mt8186"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 ovl0 = &ovl0; 25 ovl_2l0 = &ovl_2l0; 26 rdma0 = &rdma0; 27 rdma1 = &rdma1; 28 }; 29 30 cci: cci { 31 compatible = "mediatek,mt8186-cci"; 32 clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>, 33 <&apmixedsys CLK_APMIXED_MAINPLL>; 34 clock-names = "cci", "intermediate"; 35 operating-points-v2 = <&cci_opp>; 36 }; 37 38 cci_opp: opp-table-cci { 39 compatible = "operating-points-v2"; 40 opp-shared; 41 42 cci_opp_0: opp-500000000 { 43 opp-hz = /bits/ 64 <500000000>; 44 opp-microvolt = <600000>; 45 }; 46 47 cci_opp_1: opp-560000000 { 48 opp-hz = /bits/ 64 <560000000>; 49 opp-microvolt = <675000>; 50 }; 51 52 cci_opp_2: opp-612000000 { 53 opp-hz = /bits/ 64 <612000000>; 54 opp-microvolt = <693750>; 55 }; 56 57 cci_opp_3: opp-682000000 { 58 opp-hz = /bits/ 64 <682000000>; 59 opp-microvolt = <718750>; 60 }; 61 62 cci_opp_4: opp-752000000 { 63 opp-hz = /bits/ 64 <752000000>; 64 opp-microvolt = <743750>; 65 }; 66 67 cci_opp_5: opp-822000000 { 68 opp-hz = /bits/ 64 <822000000>; 69 opp-microvolt = <768750>; 70 }; 71 72 cci_opp_6: opp-875000000 { 73 opp-hz = /bits/ 64 <875000000>; 74 opp-microvolt = <781250>; 75 }; 76 77 cci_opp_7: opp-927000000 { 78 opp-hz = /bits/ 64 <927000000>; 79 opp-microvolt = <800000>; 80 }; 81 82 cci_opp_8: opp-980000000 { 83 opp-hz = /bits/ 64 <980000000>; 84 opp-microvolt = <818750>; 85 }; 86 87 cci_opp_9: opp-1050000000 { 88 opp-hz = /bits/ 64 <1050000000>; 89 opp-microvolt = <843750>; 90 }; 91 92 cci_opp_10: opp-1120000000 { 93 opp-hz = /bits/ 64 <1120000000>; 94 opp-microvolt = <862500>; 95 }; 96 97 cci_opp_11: opp-1155000000 { 98 opp-hz = /bits/ 64 <1155000000>; 99 opp-microvolt = <887500>; 100 }; 101 102 cci_opp_12: opp-1190000000 { 103 opp-hz = /bits/ 64 <1190000000>; 104 opp-microvolt = <906250>; 105 }; 106 107 cci_opp_13: opp-1260000000 { 108 opp-hz = /bits/ 64 <1260000000>; 109 opp-microvolt = <950000>; 110 }; 111 112 cci_opp_14: opp-1330000000 { 113 opp-hz = /bits/ 64 <1330000000>; 114 opp-microvolt = <993750>; 115 }; 116 117 cci_opp_15: opp-1400000000 { 118 opp-hz = /bits/ 64 <1400000000>; 119 opp-microvolt = <1031250>; 120 }; 121 }; 122 123 cluster0_opp: opp-table-cluster0 { 124 compatible = "operating-points-v2"; 125 opp-shared; 126 127 opp-500000000 { 128 opp-hz = /bits/ 64 <500000000>; 129 opp-microvolt = <600000>; 130 required-opps = <&cci_opp_0>; 131 }; 132 133 opp-774000000 { 134 opp-hz = /bits/ 64 <774000000>; 135 opp-microvolt = <675000>; 136 required-opps = <&cci_opp_1>; 137 }; 138 139 opp-875000000 { 140 opp-hz = /bits/ 64 <875000000>; 141 opp-microvolt = <700000>; 142 required-opps = <&cci_opp_2>; 143 }; 144 145 opp-975000000 { 146 opp-hz = /bits/ 64 <975000000>; 147 opp-microvolt = <725000>; 148 required-opps = <&cci_opp_3>; 149 }; 150 151 opp-1075000000 { 152 opp-hz = /bits/ 64 <1075000000>; 153 opp-microvolt = <750000>; 154 required-opps = <&cci_opp_4>; 155 }; 156 157 opp-1175000000 { 158 opp-hz = /bits/ 64 <1175000000>; 159 opp-microvolt = <775000>; 160 required-opps = <&cci_opp_5>; 161 }; 162 163 opp-1275000000 { 164 opp-hz = /bits/ 64 <1275000000>; 165 opp-microvolt = <800000>; 166 required-opps = <&cci_opp_6>; 167 }; 168 169 opp-1375000000 { 170 opp-hz = /bits/ 64 <1375000000>; 171 opp-microvolt = <825000>; 172 required-opps = <&cci_opp_7>; 173 }; 174 175 opp-1500000000 { 176 opp-hz = /bits/ 64 <1500000000>; 177 opp-microvolt = <856250>; 178 required-opps = <&cci_opp_8>; 179 }; 180 181 opp-1618000000 { 182 opp-hz = /bits/ 64 <1618000000>; 183 opp-microvolt = <875000>; 184 required-opps = <&cci_opp_9>; 185 }; 186 187 opp-1666000000 { 188 opp-hz = /bits/ 64 <1666000000>; 189 opp-microvolt = <900000>; 190 required-opps = <&cci_opp_10>; 191 }; 192 193 opp-1733000000 { 194 opp-hz = /bits/ 64 <1733000000>; 195 opp-microvolt = <925000>; 196 required-opps = <&cci_opp_11>; 197 }; 198 199 opp-1800000000 { 200 opp-hz = /bits/ 64 <1800000000>; 201 opp-microvolt = <950000>; 202 required-opps = <&cci_opp_12>; 203 }; 204 205 opp-1866000000 { 206 opp-hz = /bits/ 64 <1866000000>; 207 opp-microvolt = <981250>; 208 required-opps = <&cci_opp_13>; 209 }; 210 211 opp-1933000000 { 212 opp-hz = /bits/ 64 <1933000000>; 213 opp-microvolt = <1006250>; 214 required-opps = <&cci_opp_14>; 215 }; 216 217 opp-2000000000 { 218 opp-hz = /bits/ 64 <2000000000>; 219 opp-microvolt = <1031250>; 220 required-opps = <&cci_opp_15>; 221 }; 222 }; 223 224 cluster1_opp: opp-table-cluster1 { 225 compatible = "operating-points-v2"; 226 opp-shared; 227 228 opp-774000000 { 229 opp-hz = /bits/ 64 <774000000>; 230 opp-microvolt = <675000>; 231 required-opps = <&cci_opp_0>; 232 }; 233 234 opp-835000000 { 235 opp-hz = /bits/ 64 <835000000>; 236 opp-microvolt = <693750>; 237 required-opps = <&cci_opp_1>; 238 }; 239 240 opp-919000000 { 241 opp-hz = /bits/ 64 <919000000>; 242 opp-microvolt = <718750>; 243 required-opps = <&cci_opp_2>; 244 }; 245 246 opp-1002000000 { 247 opp-hz = /bits/ 64 <1002000000>; 248 opp-microvolt = <743750>; 249 required-opps = <&cci_opp_3>; 250 }; 251 252 opp-1085000000 { 253 opp-hz = /bits/ 64 <1085000000>; 254 opp-microvolt = <775000>; 255 required-opps = <&cci_opp_4>; 256 }; 257 258 opp-1169000000 { 259 opp-hz = /bits/ 64 <1169000000>; 260 opp-microvolt = <800000>; 261 required-opps = <&cci_opp_5>; 262 }; 263 264 opp-1308000000 { 265 opp-hz = /bits/ 64 <1308000000>; 266 opp-microvolt = <843750>; 267 required-opps = <&cci_opp_6>; 268 }; 269 270 opp-1419000000 { 271 opp-hz = /bits/ 64 <1419000000>; 272 opp-microvolt = <875000>; 273 required-opps = <&cci_opp_7>; 274 }; 275 276 opp-1530000000 { 277 opp-hz = /bits/ 64 <1530000000>; 278 opp-microvolt = <912500>; 279 required-opps = <&cci_opp_8>; 280 }; 281 282 opp-1670000000 { 283 opp-hz = /bits/ 64 <1670000000>; 284 opp-microvolt = <956250>; 285 required-opps = <&cci_opp_9>; 286 }; 287 288 opp-1733000000 { 289 opp-hz = /bits/ 64 <1733000000>; 290 opp-microvolt = <981250>; 291 required-opps = <&cci_opp_10>; 292 }; 293 294 opp-1796000000 { 295 opp-hz = /bits/ 64 <1796000000>; 296 opp-microvolt = <1012500>; 297 required-opps = <&cci_opp_11>; 298 }; 299 300 opp-1860000000 { 301 opp-hz = /bits/ 64 <1860000000>; 302 opp-microvolt = <1037500>; 303 required-opps = <&cci_opp_12>; 304 }; 305 306 opp-1923000000 { 307 opp-hz = /bits/ 64 <1923000000>; 308 opp-microvolt = <1062500>; 309 required-opps = <&cci_opp_13>; 310 }; 311 312 cluster1_opp_14: opp-1986000000 { 313 opp-hz = /bits/ 64 <1986000000>; 314 opp-microvolt = <1093750>; 315 required-opps = <&cci_opp_14>; 316 }; 317 318 cluster1_opp_15: opp-2050000000 { 319 opp-hz = /bits/ 64 <2050000000>; 320 opp-microvolt = <1118750>; 321 required-opps = <&cci_opp_15>; 322 }; 323 }; 324 325 cpus { 326 #address-cells = <1>; 327 #size-cells = <0>; 328 329 cpu-map { 330 cluster0 { 331 core0 { 332 cpu = <&cpu0>; 333 }; 334 335 core1 { 336 cpu = <&cpu1>; 337 }; 338 339 core2 { 340 cpu = <&cpu2>; 341 }; 342 343 core3 { 344 cpu = <&cpu3>; 345 }; 346 347 core4 { 348 cpu = <&cpu4>; 349 }; 350 351 core5 { 352 cpu = <&cpu5>; 353 }; 354 355 core6 { 356 cpu = <&cpu6>; 357 }; 358 359 core7 { 360 cpu = <&cpu7>; 361 }; 362 }; 363 }; 364 365 cpu0: cpu@0 { 366 device_type = "cpu"; 367 compatible = "arm,cortex-a55"; 368 reg = <0x000>; 369 enable-method = "psci"; 370 clock-frequency = <2000000000>; 371 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 372 <&apmixedsys CLK_APMIXED_MAINPLL>; 373 clock-names = "cpu", "intermediate"; 374 operating-points-v2 = <&cluster0_opp>; 375 dynamic-power-coefficient = <84>; 376 capacity-dmips-mhz = <382>; 377 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 378 i-cache-size = <32768>; 379 i-cache-line-size = <64>; 380 i-cache-sets = <128>; 381 d-cache-size = <32768>; 382 d-cache-line-size = <64>; 383 d-cache-sets = <128>; 384 next-level-cache = <&l2_0>; 385 #cooling-cells = <2>; 386 mediatek,cci = <&cci>; 387 }; 388 389 cpu1: cpu@100 { 390 device_type = "cpu"; 391 compatible = "arm,cortex-a55"; 392 reg = <0x100>; 393 enable-method = "psci"; 394 clock-frequency = <2000000000>; 395 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 396 <&apmixedsys CLK_APMIXED_MAINPLL>; 397 clock-names = "cpu", "intermediate"; 398 operating-points-v2 = <&cluster0_opp>; 399 dynamic-power-coefficient = <84>; 400 capacity-dmips-mhz = <382>; 401 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 402 i-cache-size = <32768>; 403 i-cache-line-size = <64>; 404 i-cache-sets = <128>; 405 d-cache-size = <32768>; 406 d-cache-line-size = <64>; 407 d-cache-sets = <128>; 408 next-level-cache = <&l2_0>; 409 #cooling-cells = <2>; 410 mediatek,cci = <&cci>; 411 }; 412 413 cpu2: cpu@200 { 414 device_type = "cpu"; 415 compatible = "arm,cortex-a55"; 416 reg = <0x200>; 417 enable-method = "psci"; 418 clock-frequency = <2000000000>; 419 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 420 <&apmixedsys CLK_APMIXED_MAINPLL>; 421 clock-names = "cpu", "intermediate"; 422 operating-points-v2 = <&cluster0_opp>; 423 dynamic-power-coefficient = <84>; 424 capacity-dmips-mhz = <382>; 425 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 426 i-cache-size = <32768>; 427 i-cache-line-size = <64>; 428 i-cache-sets = <128>; 429 d-cache-size = <32768>; 430 d-cache-line-size = <64>; 431 d-cache-sets = <128>; 432 next-level-cache = <&l2_0>; 433 #cooling-cells = <2>; 434 mediatek,cci = <&cci>; 435 }; 436 437 cpu3: cpu@300 { 438 device_type = "cpu"; 439 compatible = "arm,cortex-a55"; 440 reg = <0x300>; 441 enable-method = "psci"; 442 clock-frequency = <2000000000>; 443 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 444 <&apmixedsys CLK_APMIXED_MAINPLL>; 445 clock-names = "cpu", "intermediate"; 446 operating-points-v2 = <&cluster0_opp>; 447 dynamic-power-coefficient = <84>; 448 capacity-dmips-mhz = <382>; 449 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 450 i-cache-size = <32768>; 451 i-cache-line-size = <64>; 452 i-cache-sets = <128>; 453 d-cache-size = <32768>; 454 d-cache-line-size = <64>; 455 d-cache-sets = <128>; 456 next-level-cache = <&l2_0>; 457 #cooling-cells = <2>; 458 mediatek,cci = <&cci>; 459 }; 460 461 cpu4: cpu@400 { 462 device_type = "cpu"; 463 compatible = "arm,cortex-a55"; 464 reg = <0x400>; 465 enable-method = "psci"; 466 clock-frequency = <2000000000>; 467 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 468 <&apmixedsys CLK_APMIXED_MAINPLL>; 469 clock-names = "cpu", "intermediate"; 470 operating-points-v2 = <&cluster0_opp>; 471 dynamic-power-coefficient = <84>; 472 capacity-dmips-mhz = <382>; 473 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 474 i-cache-size = <32768>; 475 i-cache-line-size = <64>; 476 i-cache-sets = <128>; 477 d-cache-size = <32768>; 478 d-cache-line-size = <64>; 479 d-cache-sets = <128>; 480 next-level-cache = <&l2_0>; 481 #cooling-cells = <2>; 482 mediatek,cci = <&cci>; 483 }; 484 485 cpu5: cpu@500 { 486 device_type = "cpu"; 487 compatible = "arm,cortex-a55"; 488 reg = <0x500>; 489 enable-method = "psci"; 490 clock-frequency = <2000000000>; 491 clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>, 492 <&apmixedsys CLK_APMIXED_MAINPLL>; 493 clock-names = "cpu", "intermediate"; 494 operating-points-v2 = <&cluster0_opp>; 495 dynamic-power-coefficient = <84>; 496 capacity-dmips-mhz = <382>; 497 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 498 i-cache-size = <32768>; 499 i-cache-line-size = <64>; 500 i-cache-sets = <128>; 501 d-cache-size = <32768>; 502 d-cache-line-size = <64>; 503 d-cache-sets = <128>; 504 next-level-cache = <&l2_0>; 505 #cooling-cells = <2>; 506 mediatek,cci = <&cci>; 507 }; 508 509 cpu6: cpu@600 { 510 device_type = "cpu"; 511 compatible = "arm,cortex-a76"; 512 reg = <0x600>; 513 enable-method = "psci"; 514 clock-frequency = <2050000000>; 515 clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>, 516 <&apmixedsys CLK_APMIXED_MAINPLL>; 517 clock-names = "cpu", "intermediate"; 518 operating-points-v2 = <&cluster1_opp>; 519 dynamic-power-coefficient = <335>; 520 capacity-dmips-mhz = <1024>; 521 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 522 i-cache-size = <65536>; 523 i-cache-line-size = <64>; 524 i-cache-sets = <256>; 525 d-cache-size = <65536>; 526 d-cache-line-size = <64>; 527 d-cache-sets = <256>; 528 next-level-cache = <&l2_1>; 529 #cooling-cells = <2>; 530 mediatek,cci = <&cci>; 531 }; 532 533 cpu7: cpu@700 { 534 device_type = "cpu"; 535 compatible = "arm,cortex-a76"; 536 reg = <0x700>; 537 enable-method = "psci"; 538 clock-frequency = <2050000000>; 539 clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>, 540 <&apmixedsys CLK_APMIXED_MAINPLL>; 541 clock-names = "cpu", "intermediate"; 542 operating-points-v2 = <&cluster1_opp>; 543 dynamic-power-coefficient = <335>; 544 capacity-dmips-mhz = <1024>; 545 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 546 i-cache-size = <65536>; 547 i-cache-line-size = <64>; 548 i-cache-sets = <256>; 549 d-cache-size = <65536>; 550 d-cache-line-size = <64>; 551 d-cache-sets = <256>; 552 next-level-cache = <&l2_1>; 553 #cooling-cells = <2>; 554 mediatek,cci = <&cci>; 555 }; 556 557 idle-states { 558 entry-method = "psci"; 559 560 cpu_ret_l: cpu-retention-l { 561 compatible = "arm,idle-state"; 562 arm,psci-suspend-param = <0x00010001>; 563 local-timer-stop; 564 entry-latency-us = <50>; 565 exit-latency-us = <100>; 566 min-residency-us = <1600>; 567 }; 568 569 cpu_ret_b: cpu-retention-b { 570 compatible = "arm,idle-state"; 571 arm,psci-suspend-param = <0x00010001>; 572 local-timer-stop; 573 entry-latency-us = <50>; 574 exit-latency-us = <100>; 575 min-residency-us = <1400>; 576 }; 577 578 cpu_off_l: cpu-off-l { 579 compatible = "arm,idle-state"; 580 arm,psci-suspend-param = <0x01010001>; 581 local-timer-stop; 582 entry-latency-us = <100>; 583 exit-latency-us = <250>; 584 min-residency-us = <2100>; 585 }; 586 587 cpu_off_b: cpu-off-b { 588 compatible = "arm,idle-state"; 589 arm,psci-suspend-param = <0x01010001>; 590 local-timer-stop; 591 entry-latency-us = <100>; 592 exit-latency-us = <250>; 593 min-residency-us = <1900>; 594 }; 595 }; 596 597 l2_0: l2-cache0 { 598 compatible = "cache"; 599 cache-level = <2>; 600 cache-size = <131072>; 601 cache-line-size = <64>; 602 cache-sets = <512>; 603 next-level-cache = <&l3_0>; 604 cache-unified; 605 }; 606 607 l2_1: l2-cache1 { 608 compatible = "cache"; 609 cache-level = <2>; 610 cache-size = <262144>; 611 cache-line-size = <64>; 612 cache-sets = <512>; 613 next-level-cache = <&l3_0>; 614 cache-unified; 615 }; 616 617 l3_0: l3-cache { 618 compatible = "cache"; 619 cache-level = <3>; 620 cache-size = <1048576>; 621 cache-line-size = <64>; 622 cache-sets = <1024>; 623 cache-unified; 624 }; 625 }; 626 627 clk13m: fixed-factor-clock-13m { 628 compatible = "fixed-factor-clock"; 629 #clock-cells = <0>; 630 clocks = <&clk26m>; 631 clock-div = <2>; 632 clock-mult = <1>; 633 clock-output-names = "clk13m"; 634 }; 635 636 clk26m: oscillator-26m { 637 compatible = "fixed-clock"; 638 #clock-cells = <0>; 639 clock-frequency = <26000000>; 640 clock-output-names = "clk26m"; 641 }; 642 643 clk32k: oscillator-32k { 644 compatible = "fixed-clock"; 645 #clock-cells = <0>; 646 clock-frequency = <32768>; 647 clock-output-names = "clk32k"; 648 }; 649 650 pmu-a55 { 651 compatible = "arm,cortex-a55-pmu"; 652 interrupt-parent = <&gic>; 653 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 654 }; 655 656 pmu-a76 { 657 compatible = "arm,cortex-a76-pmu"; 658 interrupt-parent = <&gic>; 659 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 660 }; 661 662 psci { 663 compatible = "arm,psci-1.0"; 664 method = "smc"; 665 }; 666 667 timer { 668 compatible = "arm,armv8-timer"; 669 interrupt-parent = <&gic>; 670 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 671 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 672 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 673 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 674 }; 675 676 soc { 677 #address-cells = <2>; 678 #size-cells = <2>; 679 compatible = "simple-bus"; 680 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 681 ranges; 682 683 gic: interrupt-controller@c000000 { 684 compatible = "arm,gic-v3"; 685 #interrupt-cells = <4>; 686 #redistributor-regions = <1>; 687 interrupt-parent = <&gic>; 688 interrupt-controller; 689 reg = <0 0x0c000000 0 0x40000>, 690 <0 0x0c040000 0 0x200000>; 691 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 692 693 ppi-partitions { 694 ppi_cluster0: interrupt-partition-0 { 695 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 696 }; 697 698 ppi_cluster1: interrupt-partition-1 { 699 affinity = <&cpu6 &cpu7>; 700 }; 701 }; 702 }; 703 704 mcusys: syscon@c53a000 { 705 compatible = "mediatek,mt8186-mcusys", "syscon"; 706 reg = <0 0xc53a000 0 0x1000>; 707 #clock-cells = <1>; 708 }; 709 710 topckgen: syscon@10000000 { 711 compatible = "mediatek,mt8186-topckgen", "syscon"; 712 reg = <0 0x10000000 0 0x1000>; 713 #clock-cells = <1>; 714 }; 715 716 infracfg_ao: syscon@10001000 { 717 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 718 reg = <0 0x10001000 0 0x1000>; 719 #clock-cells = <1>; 720 #reset-cells = <1>; 721 }; 722 723 pericfg: syscon@10003000 { 724 compatible = "mediatek,mt8186-pericfg", "syscon"; 725 reg = <0 0x10003000 0 0x1000>; 726 }; 727 728 pio: pinctrl@10005000 { 729 compatible = "mediatek,mt8186-pinctrl"; 730 reg = <0 0x10005000 0 0x1000>, 731 <0 0x10002000 0 0x0200>, 732 <0 0x10002200 0 0x0200>, 733 <0 0x10002400 0 0x0200>, 734 <0 0x10002600 0 0x0200>, 735 <0 0x10002a00 0 0x0200>, 736 <0 0x10002c00 0 0x0200>, 737 <0 0x1000b000 0 0x1000>; 738 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 739 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 740 gpio-controller; 741 #gpio-cells = <2>; 742 gpio-ranges = <&pio 0 0 185>; 743 interrupt-controller; 744 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 745 #interrupt-cells = <2>; 746 }; 747 748 scpsys: syscon@10006000 { 749 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 750 reg = <0 0x10006000 0 0x1000>; 751 752 /* System Power Manager */ 753 spm: power-controller { 754 compatible = "mediatek,mt8186-power-controller"; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 #power-domain-cells = <1>; 758 759 /* power domain of the SoC */ 760 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 761 reg = <MT8186_POWER_DOMAIN_MFG0>; 762 clocks = <&topckgen CLK_TOP_MFG>; 763 clock-names = "mfg00"; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 #power-domain-cells = <1>; 767 768 power-domain@MT8186_POWER_DOMAIN_MFG1 { 769 reg = <MT8186_POWER_DOMAIN_MFG1>; 770 mediatek,infracfg = <&infracfg_ao>; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 #power-domain-cells = <1>; 774 775 power-domain@MT8186_POWER_DOMAIN_MFG2 { 776 reg = <MT8186_POWER_DOMAIN_MFG2>; 777 #power-domain-cells = <0>; 778 }; 779 780 power-domain@MT8186_POWER_DOMAIN_MFG3 { 781 reg = <MT8186_POWER_DOMAIN_MFG3>; 782 #power-domain-cells = <0>; 783 }; 784 }; 785 }; 786 787 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 788 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 789 clocks = <&topckgen CLK_TOP_SENINF>, 790 <&topckgen CLK_TOP_SENINF1>; 791 clock-names = "csirx_top0", "csirx_top1"; 792 #power-domain-cells = <0>; 793 }; 794 795 power-domain@MT8186_POWER_DOMAIN_SSUSB { 796 reg = <MT8186_POWER_DOMAIN_SSUSB>; 797 #power-domain-cells = <0>; 798 }; 799 800 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 801 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 802 #power-domain-cells = <0>; 803 }; 804 805 power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 806 reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 807 clocks = <&topckgen CLK_TOP_AUDIODSP>, 808 <&topckgen CLK_TOP_ADSP_BUS>; 809 clock-names = "audioadsp", "adsp_bus"; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 #power-domain-cells = <1>; 813 814 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 815 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 #power-domain-cells = <1>; 819 820 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 821 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 822 mediatek,infracfg = <&infracfg_ao>; 823 #power-domain-cells = <0>; 824 }; 825 }; 826 }; 827 828 power-domain@MT8186_POWER_DOMAIN_CONN_ON { 829 reg = <MT8186_POWER_DOMAIN_CONN_ON>; 830 mediatek,infracfg = <&infracfg_ao>; 831 #power-domain-cells = <0>; 832 }; 833 834 power-domain@MT8186_POWER_DOMAIN_DIS { 835 reg = <MT8186_POWER_DOMAIN_DIS>; 836 clocks = <&topckgen CLK_TOP_DISP>, 837 <&topckgen CLK_TOP_MDP>, 838 <&mmsys CLK_MM_SMI_INFRA>, 839 <&mmsys CLK_MM_SMI_COMMON>, 840 <&mmsys CLK_MM_SMI_GALS>, 841 <&mmsys CLK_MM_SMI_IOMMU>; 842 clock-names = "disp", "mdp", "smi_infra", "smi_common", 843 "smi_gals", "smi_iommu"; 844 mediatek,infracfg = <&infracfg_ao>; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 #power-domain-cells = <1>; 848 849 power-domain@MT8186_POWER_DOMAIN_VDEC { 850 reg = <MT8186_POWER_DOMAIN_VDEC>; 851 clocks = <&topckgen CLK_TOP_VDEC>, 852 <&vdecsys CLK_VDEC_LARB1_CKEN>; 853 clock-names = "vdec0", "larb"; 854 mediatek,infracfg = <&infracfg_ao>; 855 #power-domain-cells = <0>; 856 }; 857 858 power-domain@MT8186_POWER_DOMAIN_CAM { 859 reg = <MT8186_POWER_DOMAIN_CAM>; 860 clocks = <&topckgen CLK_TOP_CAM>, 861 <&topckgen CLK_TOP_SENINF>, 862 <&topckgen CLK_TOP_SENINF1>, 863 <&topckgen CLK_TOP_SENINF2>, 864 <&topckgen CLK_TOP_SENINF3>, 865 <&topckgen CLK_TOP_CAMTM>, 866 <&camsys CLK_CAM2MM_GALS>; 867 clock-names = "cam-top", "cam0", "cam1", "cam2", 868 "cam3", "cam-tm", "gals"; 869 mediatek,infracfg = <&infracfg_ao>; 870 #address-cells = <1>; 871 #size-cells = <0>; 872 #power-domain-cells = <1>; 873 874 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 875 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 876 #power-domain-cells = <0>; 877 }; 878 879 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 880 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 881 #power-domain-cells = <0>; 882 }; 883 }; 884 885 power-domain@MT8186_POWER_DOMAIN_IMG { 886 reg = <MT8186_POWER_DOMAIN_IMG>; 887 clocks = <&topckgen CLK_TOP_IMG1>, 888 <&imgsys1 CLK_IMG1_GALS_IMG1>; 889 clock-names = "img-top", "gals"; 890 mediatek,infracfg = <&infracfg_ao>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 #power-domain-cells = <1>; 894 895 power-domain@MT8186_POWER_DOMAIN_IMG2 { 896 reg = <MT8186_POWER_DOMAIN_IMG2>; 897 #power-domain-cells = <0>; 898 }; 899 }; 900 901 power-domain@MT8186_POWER_DOMAIN_IPE { 902 reg = <MT8186_POWER_DOMAIN_IPE>; 903 clocks = <&topckgen CLK_TOP_IPE>, 904 <&ipesys CLK_IPE_LARB19>, 905 <&ipesys CLK_IPE_LARB20>, 906 <&ipesys CLK_IPE_SMI_SUBCOM>, 907 <&ipesys CLK_IPE_GALS_IPE>; 908 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", 909 "ipe-smi", "ipe-gals"; 910 mediatek,infracfg = <&infracfg_ao>; 911 #power-domain-cells = <0>; 912 }; 913 914 power-domain@MT8186_POWER_DOMAIN_VENC { 915 reg = <MT8186_POWER_DOMAIN_VENC>; 916 clocks = <&topckgen CLK_TOP_VENC>, 917 <&vencsys CLK_VENC_CKE1_VENC>; 918 clock-names = "venc0", "larb"; 919 mediatek,infracfg = <&infracfg_ao>; 920 #power-domain-cells = <0>; 921 }; 922 923 power-domain@MT8186_POWER_DOMAIN_WPE { 924 reg = <MT8186_POWER_DOMAIN_WPE>; 925 clocks = <&topckgen CLK_TOP_WPE>, 926 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 927 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 928 clock-names = "wpe0", "larb-ck", "larb-pclk"; 929 mediatek,infracfg = <&infracfg_ao>; 930 #power-domain-cells = <0>; 931 }; 932 }; 933 }; 934 }; 935 936 watchdog: watchdog@10007000 { 937 compatible = "mediatek,mt8186-wdt"; 938 mediatek,disable-extrst; 939 reg = <0 0x10007000 0 0x1000>; 940 #reset-cells = <1>; 941 }; 942 943 apmixedsys: syscon@1000c000 { 944 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 945 reg = <0 0x1000c000 0 0x1000>; 946 #clock-cells = <1>; 947 }; 948 949 pwrap: pwrap@1000d000 { 950 compatible = "mediatek,mt8186-pwrap", "syscon"; 951 reg = <0 0x1000d000 0 0x1000>; 952 reg-names = "pwrap"; 953 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 954 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 955 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 956 clock-names = "spi", "wrap"; 957 }; 958 959 spmi: spmi@10015000 { 960 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; 961 reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; 962 reg-names = "pmif", "spmimst"; 963 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 964 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 965 <&topckgen CLK_TOP_SPMI_MST>; 966 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 967 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; 968 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 969 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>, 970 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>; 971 status = "disabled"; 972 }; 973 974 systimer: timer@10017000 { 975 compatible = "mediatek,mt8186-timer", 976 "mediatek,mt6765-timer"; 977 reg = <0 0x10017000 0 0x1000>; 978 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 979 clocks = <&clk13m>; 980 }; 981 982 gce: mailbox@1022c000 { 983 compatible = "mediatek,mt8186-gce"; 984 reg = <0 0X1022c000 0 0x4000>; 985 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 986 clock-names = "gce"; 987 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 988 #mbox-cells = <2>; 989 }; 990 991 scp: scp@10500000 { 992 compatible = "mediatek,mt8186-scp"; 993 reg = <0 0x10500000 0 0x40000>, 994 <0 0x105c0000 0 0x19080>; 995 reg-names = "sram", "cfg"; 996 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 997 }; 998 999 adsp: adsp@10680000 { 1000 compatible = "mediatek,mt8186-dsp"; 1001 reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, 1002 <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; 1003 reg-names = "cfg", "sram", "sec", "bus"; 1004 clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; 1005 clock-names = "audiodsp", "adsp_bus"; 1006 assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, 1007 <&topckgen CLK_TOP_ADSP_BUS>; 1008 assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; 1009 mbox-names = "rx", "tx"; 1010 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 1011 power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; 1012 status = "disabled"; 1013 }; 1014 1015 adsp_mailbox0: mailbox@10686000 { 1016 compatible = "mediatek,mt8186-adsp-mbox"; 1017 #mbox-cells = <0>; 1018 reg = <0 0x10686100 0 0x1000>; 1019 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 1020 }; 1021 1022 adsp_mailbox1: mailbox@10687000 { 1023 compatible = "mediatek,mt8186-adsp-mbox"; 1024 #mbox-cells = <0>; 1025 reg = <0 0x10687100 0 0x1000>; 1026 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>; 1027 }; 1028 1029 nor_flash: spi@11000000 { 1030 compatible = "mediatek,mt8186-nor"; 1031 reg = <0 0x11000000 0 0x1000>; 1032 clocks = <&topckgen CLK_TOP_SPINOR>, 1033 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 1034 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 1035 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 1036 clock-names = "spi", "sf", "axi", "axi_s"; 1037 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 1038 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 1039 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 1040 status = "disabled"; 1041 }; 1042 1043 auxadc: adc@11001000 { 1044 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 1045 reg = <0 0x11001000 0 0x1000>; 1046 #io-channel-cells = <1>; 1047 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1048 clock-names = "main"; 1049 }; 1050 1051 uart0: serial@11002000 { 1052 compatible = "mediatek,mt8186-uart", 1053 "mediatek,mt6577-uart"; 1054 reg = <0 0x11002000 0 0x1000>; 1055 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 1056 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1057 clock-names = "baud", "bus"; 1058 status = "disabled"; 1059 }; 1060 1061 uart1: serial@11003000 { 1062 compatible = "mediatek,mt8186-uart", 1063 "mediatek,mt6577-uart"; 1064 reg = <0 0x11003000 0 0x1000>; 1065 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1066 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1067 clock-names = "baud", "bus"; 1068 status = "disabled"; 1069 }; 1070 1071 i2c0: i2c@11007000 { 1072 compatible = "mediatek,mt8186-i2c"; 1073 reg = <0 0x11007000 0 0x1000>, 1074 <0 0x10200100 0 0x100>; 1075 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 1076 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 1077 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1078 clock-names = "main", "dma"; 1079 clock-div = <1>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 status = "disabled"; 1083 }; 1084 1085 i2c1: i2c@11008000 { 1086 compatible = "mediatek,mt8186-i2c"; 1087 reg = <0 0x11008000 0 0x1000>, 1088 <0 0x10200200 0 0x100>; 1089 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1090 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 1091 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1092 clock-names = "main", "dma"; 1093 clock-div = <1>; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 status = "disabled"; 1097 }; 1098 1099 i2c2: i2c@11009000 { 1100 compatible = "mediatek,mt8186-i2c"; 1101 reg = <0 0x11009000 0 0x1000>, 1102 <0 0x10200300 0 0x180>; 1103 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 1104 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 1105 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1106 clock-names = "main", "dma"; 1107 clock-div = <1>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 1113 i2c3: i2c@1100f000 { 1114 compatible = "mediatek,mt8186-i2c"; 1115 reg = <0 0x1100f000 0 0x1000>, 1116 <0 0x10200480 0 0x100>; 1117 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 1118 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 1119 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1120 clock-names = "main", "dma"; 1121 clock-div = <1>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 i2c4: i2c@11011000 { 1128 compatible = "mediatek,mt8186-i2c"; 1129 reg = <0 0x11011000 0 0x1000>, 1130 <0 0x10200580 0 0x180>; 1131 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 1132 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 1133 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1134 clock-names = "main", "dma"; 1135 clock-div = <1>; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 status = "disabled"; 1139 }; 1140 1141 i2c5: i2c@11016000 { 1142 compatible = "mediatek,mt8186-i2c"; 1143 reg = <0 0x11016000 0 0x1000>, 1144 <0 0x10200700 0 0x100>; 1145 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 1146 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 1147 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1148 clock-names = "main", "dma"; 1149 clock-div = <1>; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 status = "disabled"; 1153 }; 1154 1155 i2c6: i2c@1100d000 { 1156 compatible = "mediatek,mt8186-i2c"; 1157 reg = <0 0x1100d000 0 0x1000>, 1158 <0 0x10200800 0 0x100>; 1159 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 1160 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 1161 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1162 clock-names = "main", "dma"; 1163 clock-div = <1>; 1164 #address-cells = <1>; 1165 #size-cells = <0>; 1166 status = "disabled"; 1167 }; 1168 1169 i2c7: i2c@11004000 { 1170 compatible = "mediatek,mt8186-i2c"; 1171 reg = <0 0x11004000 0 0x1000>, 1172 <0 0x10200900 0 0x180>; 1173 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 1174 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 1175 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1176 clock-names = "main", "dma"; 1177 clock-div = <1>; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 status = "disabled"; 1181 }; 1182 1183 i2c8: i2c@11005000 { 1184 compatible = "mediatek,mt8186-i2c"; 1185 reg = <0 0x11005000 0 0x1000>, 1186 <0 0x10200A80 0 0x180>; 1187 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1188 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 1189 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1190 clock-names = "main", "dma"; 1191 clock-div = <1>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 status = "disabled"; 1195 }; 1196 1197 spi0: spi@1100a000 { 1198 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 reg = <0 0x1100a000 0 0x1000>; 1202 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 1203 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1204 <&topckgen CLK_TOP_SPI>, 1205 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1206 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1207 status = "disabled"; 1208 }; 1209 1210 pwm0: pwm@1100e000 { 1211 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 1212 reg = <0 0x1100e000 0 0x1000>; 1213 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1214 #pwm-cells = <2>; 1215 clocks = <&topckgen CLK_TOP_DISP_PWM>, 1216 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1217 clock-names = "main", "mm"; 1218 status = "disabled"; 1219 }; 1220 1221 spi1: spi@11010000 { 1222 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 reg = <0 0x11010000 0 0x1000>; 1226 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 1227 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1228 <&topckgen CLK_TOP_SPI>, 1229 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1230 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1231 status = "disabled"; 1232 }; 1233 1234 spi2: spi@11012000 { 1235 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 reg = <0 0x11012000 0 0x1000>; 1239 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 1240 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1241 <&topckgen CLK_TOP_SPI>, 1242 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1243 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1244 status = "disabled"; 1245 }; 1246 1247 spi3: spi@11013000 { 1248 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 reg = <0 0x11013000 0 0x1000>; 1252 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 1253 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1254 <&topckgen CLK_TOP_SPI>, 1255 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1256 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1257 status = "disabled"; 1258 }; 1259 1260 spi4: spi@11014000 { 1261 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 reg = <0 0x11014000 0 0x1000>; 1265 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1266 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1267 <&topckgen CLK_TOP_SPI>, 1268 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1269 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1270 status = "disabled"; 1271 }; 1272 1273 spi5: spi@11015000 { 1274 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 reg = <0 0x11015000 0 0x1000>; 1278 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1279 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1280 <&topckgen CLK_TOP_SPI>, 1281 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1282 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1283 status = "disabled"; 1284 }; 1285 1286 imp_iic_wrap: clock-controller@11017000 { 1287 compatible = "mediatek,mt8186-imp_iic_wrap"; 1288 reg = <0 0x11017000 0 0x1000>; 1289 #clock-cells = <1>; 1290 }; 1291 1292 uart2: serial@11018000 { 1293 compatible = "mediatek,mt8186-uart", 1294 "mediatek,mt6577-uart"; 1295 reg = <0 0x11018000 0 0x1000>; 1296 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 1297 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1298 clock-names = "baud", "bus"; 1299 status = "disabled"; 1300 }; 1301 1302 i2c9: i2c@11019000 { 1303 compatible = "mediatek,mt8186-i2c"; 1304 reg = <0 0x11019000 0 0x1000>, 1305 <0 0x10200c00 0 0x180>; 1306 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1307 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 1308 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1309 clock-names = "main", "dma"; 1310 clock-div = <1>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 status = "disabled"; 1314 }; 1315 1316 afe: audio-controller@11210000 { 1317 compatible = "mediatek,mt8186-sound"; 1318 reg = <0 0x11210000 0 0x2000>; 1319 clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, 1320 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, 1321 <&topckgen CLK_TOP_AUDIO>, 1322 <&topckgen CLK_TOP_AUD_INTBUS>, 1323 <&topckgen CLK_TOP_MAINPLL_D2_D4>, 1324 <&topckgen CLK_TOP_AUD_1>, 1325 <&apmixedsys CLK_APMIXED_APLL1>, 1326 <&topckgen CLK_TOP_AUD_2>, 1327 <&apmixedsys CLK_APMIXED_APLL2>, 1328 <&topckgen CLK_TOP_AUD_ENGEN1>, 1329 <&topckgen CLK_TOP_APLL1_D8>, 1330 <&topckgen CLK_TOP_AUD_ENGEN2>, 1331 <&topckgen CLK_TOP_APLL2_D8>, 1332 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, 1333 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, 1334 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, 1335 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, 1336 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, 1337 <&topckgen CLK_TOP_APLL12_CK_DIV0>, 1338 <&topckgen CLK_TOP_APLL12_CK_DIV1>, 1339 <&topckgen CLK_TOP_APLL12_CK_DIV2>, 1340 <&topckgen CLK_TOP_APLL12_CK_DIV4>, 1341 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, 1342 <&topckgen CLK_TOP_AUDIO_H>, 1343 <&clk26m>; 1344 clock-names = "aud_infra_clk", 1345 "mtkaif_26m_clk", 1346 "top_mux_audio", 1347 "top_mux_audio_int", 1348 "top_mainpll_d2_d4", 1349 "top_mux_aud_1", 1350 "top_apll1_ck", 1351 "top_mux_aud_2", 1352 "top_apll2_ck", 1353 "top_mux_aud_eng1", 1354 "top_apll1_d8", 1355 "top_mux_aud_eng2", 1356 "top_apll2_d8", 1357 "top_i2s0_m_sel", 1358 "top_i2s1_m_sel", 1359 "top_i2s2_m_sel", 1360 "top_i2s4_m_sel", 1361 "top_tdm_m_sel", 1362 "top_apll12_div0", 1363 "top_apll12_div1", 1364 "top_apll12_div2", 1365 "top_apll12_div4", 1366 "top_apll12_div_tdm", 1367 "top_mux_audio_h", 1368 "top_clk26m_clk"; 1369 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1370 mediatek,apmixedsys = <&apmixedsys>; 1371 mediatek,infracfg = <&infracfg_ao>; 1372 mediatek,topckgen = <&topckgen>; 1373 resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; 1374 reset-names = "audiosys"; 1375 status = "disabled"; 1376 }; 1377 1378 ssusb0: usb@11201000 { 1379 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1380 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1381 reg-names = "mac", "ippc"; 1382 clocks = <&topckgen CLK_TOP_USB_TOP>, 1383 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1384 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1385 <&infracfg_ao CLK_INFRA_AO_ICUSB>; 1386 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1387 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>; 1388 phys = <&u2port0 PHY_TYPE_USB2>; 1389 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; 1390 #address-cells = <2>; 1391 #size-cells = <2>; 1392 ranges; 1393 status = "disabled"; 1394 1395 usb_host0: usb@11200000 { 1396 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1397 reg = <0 0x11200000 0 0x1000>; 1398 reg-names = "mac"; 1399 clocks = <&topckgen CLK_TOP_USB_TOP>, 1400 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1401 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1402 <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1403 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1404 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1405 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 1406 mediatek,syscon-wakeup = <&pericfg 0x420 2>; 1407 wakeup-source; 1408 status = "disabled"; 1409 }; 1410 }; 1411 1412 mmc0: mmc@11230000 { 1413 compatible = "mediatek,mt8186-mmc", 1414 "mediatek,mt8183-mmc"; 1415 reg = <0 0x11230000 0 0x10000>, 1416 <0 0x11cd0000 0 0x1000>; 1417 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1418 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1419 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1420 <&infracfg_ao CLK_INFRA_AO_MSDCFDE>; 1421 clock-names = "source", "hclk", "source_cg", "crypto"; 1422 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 1423 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 1424 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 1425 status = "disabled"; 1426 }; 1427 1428 mmc1: mmc@11240000 { 1429 compatible = "mediatek,mt8186-mmc", 1430 "mediatek,mt8183-mmc"; 1431 reg = <0 0x11240000 0 0x1000>, 1432 <0 0x11c90000 0 0x1000>; 1433 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1434 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1435 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1436 clock-names = "source", "hclk", "source_cg"; 1437 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 1438 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1439 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1440 status = "disabled"; 1441 }; 1442 1443 ssusb1: usb@11281000 { 1444 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1445 reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; 1446 reg-names = "mac", "ippc"; 1447 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1448 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1449 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1450 <&clk26m>; 1451 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1452 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 1453 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1454 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; 1455 #address-cells = <2>; 1456 #size-cells = <2>; 1457 ranges; 1458 status = "disabled"; 1459 1460 usb_host1: usb@11280000 { 1461 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1462 reg = <0 0x11280000 0 0x1000>; 1463 reg-names = "mac"; 1464 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1465 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1466 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1467 <&clk26m>, 1468 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1469 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; 1470 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1471 mediatek,syscon-wakeup = <&pericfg 0x424 2>; 1472 wakeup-source; 1473 status = "disabled"; 1474 }; 1475 }; 1476 1477 u3phy0: t-phy@11c80000 { 1478 compatible = "mediatek,mt8186-tphy", 1479 "mediatek,generic-tphy-v2"; 1480 #address-cells = <1>; 1481 #size-cells = <1>; 1482 ranges = <0x0 0x0 0x11c80000 0x1000>; 1483 status = "disabled"; 1484 1485 u2port1: usb-phy@0 { 1486 reg = <0x0 0x700>; 1487 clocks = <&clk26m>; 1488 clock-names = "ref"; 1489 #phy-cells = <1>; 1490 }; 1491 1492 u3port1: usb-phy@700 { 1493 reg = <0x700 0x900>; 1494 clocks = <&clk26m>; 1495 clock-names = "ref"; 1496 #phy-cells = <1>; 1497 }; 1498 }; 1499 1500 u3phy1: t-phy@11ca0000 { 1501 compatible = "mediatek,mt8186-tphy", 1502 "mediatek,generic-tphy-v2"; 1503 #address-cells = <1>; 1504 #size-cells = <1>; 1505 ranges = <0x0 0x0 0x11ca0000 0x1000>; 1506 status = "disabled"; 1507 1508 u2port0: usb-phy@0 { 1509 reg = <0x0 0x700>; 1510 clocks = <&clk26m>; 1511 clock-names = "ref"; 1512 #phy-cells = <1>; 1513 mediatek,discth = <0x8>; 1514 }; 1515 }; 1516 1517 efuse: efuse@11cb0000 { 1518 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 1519 reg = <0 0x11cb0000 0 0x1000>; 1520 #address-cells = <1>; 1521 #size-cells = <1>; 1522 1523 gpu_speedbin: gpu-speed-bin@59c { 1524 reg = <0x59c 0x4>; 1525 bits = <0 3>; 1526 }; 1527 }; 1528 1529 mipi_tx0: dsi-phy@11cc0000 { 1530 compatible = "mediatek,mt8183-mipi-tx"; 1531 reg = <0 0x11cc0000 0 0x1000>; 1532 clocks = <&clk26m>; 1533 #clock-cells = <0>; 1534 #phy-cells = <0>; 1535 clock-output-names = "mipi_tx0_pll"; 1536 status = "disabled"; 1537 }; 1538 1539 mfgsys: clock-controller@13000000 { 1540 compatible = "mediatek,mt8186-mfgsys"; 1541 reg = <0 0x13000000 0 0x1000>; 1542 #clock-cells = <1>; 1543 }; 1544 1545 gpu: gpu@13040000 { 1546 compatible = "mediatek,mt8186-mali", 1547 "arm,mali-bifrost"; 1548 reg = <0 0x13040000 0 0x4000>; 1549 1550 clocks = <&mfgsys CLK_MFG_BG3D>; 1551 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>, 1552 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>, 1553 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 1554 interrupt-names = "job", "mmu", "gpu"; 1555 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>, 1556 <&spm MT8186_POWER_DOMAIN_MFG3>; 1557 power-domain-names = "core0", "core1"; 1558 #cooling-cells = <2>; 1559 nvmem-cells = <&gpu_speedbin>; 1560 nvmem-cell-names = "speed-bin"; 1561 status = "disabled"; 1562 }; 1563 1564 mmsys: syscon@14000000 { 1565 compatible = "mediatek,mt8186-mmsys", "syscon"; 1566 reg = <0 0x14000000 0 0x1000>; 1567 #clock-cells = <1>; 1568 #reset-cells = <1>; 1569 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1570 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1571 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1572 }; 1573 1574 mutex: mutex@14001000 { 1575 compatible = "mediatek,mt8186-disp-mutex"; 1576 reg = <0 0x14001000 0 0x1000>; 1577 clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1578 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>; 1579 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1580 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1581 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1582 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1583 }; 1584 1585 smi_common: smi@14002000 { 1586 compatible = "mediatek,mt8186-smi-common"; 1587 reg = <0 0x14002000 0 0x1000>; 1588 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 1589 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 1590 clock-names = "apb", "smi", "gals0", "gals1"; 1591 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1592 }; 1593 1594 larb0: smi@14003000 { 1595 compatible = "mediatek,mt8186-smi-larb"; 1596 reg = <0 0x14003000 0 0x1000>; 1597 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1598 <&mmsys CLK_MM_SMI_COMMON>; 1599 clock-names = "apb", "smi"; 1600 mediatek,larb-id = <0>; 1601 mediatek,smi = <&smi_common>; 1602 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1603 }; 1604 1605 larb1: smi@14004000 { 1606 compatible = "mediatek,mt8186-smi-larb"; 1607 reg = <0 0x14004000 0 0x1000>; 1608 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1609 <&mmsys CLK_MM_SMI_COMMON>; 1610 clock-names = "apb", "smi"; 1611 mediatek,larb-id = <1>; 1612 mediatek,smi = <&smi_common>; 1613 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1614 }; 1615 1616 ovl0: ovl@14005000 { 1617 compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl"; 1618 reg = <0 0x14005000 0 0x1000>; 1619 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1620 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; 1621 iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; 1622 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1623 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1624 }; 1625 1626 ovl_2l0: ovl@14006000 { 1627 compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l"; 1628 reg = <0 0x14006000 0 0x1000>; 1629 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1630 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 1631 iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; 1632 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1633 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1634 }; 1635 1636 rdma0: rdma@14007000 { 1637 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1638 reg = <0 0x14007000 0 0x1000>; 1639 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1640 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>; 1641 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; 1642 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1643 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1644 }; 1645 1646 color: color@14009000 { 1647 compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color"; 1648 reg = <0 0x14009000 0 0x1000>; 1649 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1650 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>; 1651 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1652 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1653 }; 1654 1655 dpi: dpi@1400a000 { 1656 compatible = "mediatek,mt8186-dpi"; 1657 reg = <0 0x1400a000 0 0x1000>; 1658 clocks = <&topckgen CLK_TOP_DPI>, 1659 <&mmsys CLK_MM_DISP_DPI>, 1660 <&apmixedsys CLK_APMIXED_TVDPLL>; 1661 clock-names = "pixel", "engine", "pll"; 1662 assigned-clocks = <&topckgen CLK_TOP_DPI>; 1663 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; 1664 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; 1665 status = "disabled"; 1666 1667 port { 1668 dpi_out: endpoint { }; 1669 }; 1670 }; 1671 1672 ccorr: ccorr@1400b000 { 1673 compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 1674 reg = <0 0x1400b000 0 0x1000>; 1675 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1676 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>; 1677 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1678 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1679 }; 1680 1681 aal: aal@1400c000 { 1682 compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal"; 1683 reg = <0 0x1400c000 0 0x1000>; 1684 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1685 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>; 1686 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1687 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1688 }; 1689 1690 gamma: gamma@1400d000 { 1691 compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma"; 1692 reg = <0 0x1400d000 0 0x1000>; 1693 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1694 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 1695 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1696 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1697 }; 1698 1699 postmask: postmask@1400e000 { 1700 compatible = "mediatek,mt8186-disp-postmask", 1701 "mediatek,mt8192-disp-postmask"; 1702 reg = <0 0x1400e000 0 0x1000>; 1703 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1704 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 1705 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1706 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1707 }; 1708 1709 dither: dither@1400f000 { 1710 compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither"; 1711 reg = <0 0x1400f000 0 0x1000>; 1712 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1713 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>; 1714 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1715 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1716 }; 1717 1718 dsi0: dsi@14013000 { 1719 compatible = "mediatek,mt8186-dsi"; 1720 reg = <0 0x14013000 0 0x1000>; 1721 clocks = <&mmsys CLK_MM_DSI0>, 1722 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 1723 <&mipi_tx0>; 1724 clock-names = "engine", "digital", "hs"; 1725 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 1726 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1727 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 1728 phys = <&mipi_tx0>; 1729 phy-names = "dphy"; 1730 status = "disabled"; 1731 1732 port { 1733 dsi_out: endpoint { }; 1734 }; 1735 }; 1736 1737 iommu_mm: iommu@14016000 { 1738 compatible = "mediatek,mt8186-iommu-mm"; 1739 reg = <0 0x14016000 0 0x1000>; 1740 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1741 clock-names = "bclk"; 1742 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1743 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1744 &larb7 &larb8 &larb9 &larb11 1745 &larb13 &larb14 &larb16 &larb17 1746 &larb19 &larb20>; 1747 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1748 #iommu-cells = <1>; 1749 }; 1750 1751 rdma1: rdma@1401f000 { 1752 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1753 reg = <0 0x1401f000 0 0x1000>; 1754 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1755 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>; 1756 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; 1757 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>; 1758 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1759 }; 1760 1761 wpesys: clock-controller@14020000 { 1762 compatible = "mediatek,mt8186-wpesys"; 1763 reg = <0 0x14020000 0 0x1000>; 1764 #clock-cells = <1>; 1765 }; 1766 1767 larb8: smi@14023000 { 1768 compatible = "mediatek,mt8186-smi-larb"; 1769 reg = <0 0x14023000 0 0x1000>; 1770 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1771 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1772 clock-names = "apb", "smi"; 1773 mediatek,larb-id = <8>; 1774 mediatek,smi = <&smi_common>; 1775 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1776 }; 1777 1778 imgsys1: clock-controller@15020000 { 1779 compatible = "mediatek,mt8186-imgsys1"; 1780 reg = <0 0x15020000 0 0x1000>; 1781 #clock-cells = <1>; 1782 }; 1783 1784 larb9: smi@1502e000 { 1785 compatible = "mediatek,mt8186-smi-larb"; 1786 reg = <0 0x1502e000 0 0x1000>; 1787 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1788 <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1789 clock-names = "apb", "smi"; 1790 mediatek,larb-id = <9>; 1791 mediatek,smi = <&smi_common>; 1792 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 1793 }; 1794 1795 imgsys2: clock-controller@15820000 { 1796 compatible = "mediatek,mt8186-imgsys2"; 1797 reg = <0 0x15820000 0 0x1000>; 1798 #clock-cells = <1>; 1799 }; 1800 1801 larb11: smi@1582e000 { 1802 compatible = "mediatek,mt8186-smi-larb"; 1803 reg = <0 0x1582e000 0 0x1000>; 1804 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 1805 <&imgsys2 CLK_IMG2_LARB9_IMG2>; 1806 clock-names = "apb", "smi"; 1807 mediatek,larb-id = <11>; 1808 mediatek,smi = <&smi_common>; 1809 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 1810 }; 1811 1812 larb4: smi@1602e000 { 1813 compatible = "mediatek,mt8186-smi-larb"; 1814 reg = <0 0x1602e000 0 0x1000>; 1815 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 1816 <&vdecsys CLK_VDEC_LARB1_CKEN>; 1817 clock-names = "apb", "smi"; 1818 mediatek,larb-id = <4>; 1819 mediatek,smi = <&smi_common>; 1820 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 1821 }; 1822 1823 vdecsys: clock-controller@1602f000 { 1824 compatible = "mediatek,mt8186-vdecsys"; 1825 reg = <0 0x1602f000 0 0x1000>; 1826 #clock-cells = <1>; 1827 }; 1828 1829 vencsys: clock-controller@17000000 { 1830 compatible = "mediatek,mt8186-vencsys"; 1831 reg = <0 0x17000000 0 0x1000>; 1832 #clock-cells = <1>; 1833 }; 1834 1835 larb7: smi@17010000 { 1836 compatible = "mediatek,mt8186-smi-larb"; 1837 reg = <0 0x17010000 0 0x1000>; 1838 clocks = <&vencsys CLK_VENC_CKE1_VENC>, 1839 <&vencsys CLK_VENC_CKE1_VENC>; 1840 clock-names = "apb", "smi"; 1841 mediatek,larb-id = <7>; 1842 mediatek,smi = <&smi_common>; 1843 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 1844 }; 1845 1846 camsys: clock-controller@1a000000 { 1847 compatible = "mediatek,mt8186-camsys"; 1848 reg = <0 0x1a000000 0 0x1000>; 1849 #clock-cells = <1>; 1850 }; 1851 1852 larb13: smi@1a001000 { 1853 compatible = "mediatek,mt8186-smi-larb"; 1854 reg = <0 0x1a001000 0 0x1000>; 1855 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 1856 clock-names = "apb", "smi"; 1857 mediatek,larb-id = <13>; 1858 mediatek,smi = <&smi_common>; 1859 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1860 }; 1861 1862 larb14: smi@1a002000 { 1863 compatible = "mediatek,mt8186-smi-larb"; 1864 reg = <0 0x1a002000 0 0x1000>; 1865 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 1866 clock-names = "apb", "smi"; 1867 mediatek,larb-id = <14>; 1868 mediatek,smi = <&smi_common>; 1869 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1870 }; 1871 1872 larb16: smi@1a00f000 { 1873 compatible = "mediatek,mt8186-smi-larb"; 1874 reg = <0 0x1a00f000 0 0x1000>; 1875 clocks = <&camsys CLK_CAM_LARB14>, 1876 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 1877 clock-names = "apb", "smi"; 1878 mediatek,larb-id = <16>; 1879 mediatek,smi = <&smi_common>; 1880 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 1881 }; 1882 1883 larb17: smi@1a010000 { 1884 compatible = "mediatek,mt8186-smi-larb"; 1885 reg = <0 0x1a010000 0 0x1000>; 1886 clocks = <&camsys CLK_CAM_LARB13>, 1887 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 1888 clock-names = "apb", "smi"; 1889 mediatek,larb-id = <17>; 1890 mediatek,smi = <&smi_common>; 1891 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 1892 }; 1893 1894 camsys_rawa: clock-controller@1a04f000 { 1895 compatible = "mediatek,mt8186-camsys_rawa"; 1896 reg = <0 0x1a04f000 0 0x1000>; 1897 #clock-cells = <1>; 1898 }; 1899 1900 camsys_rawb: clock-controller@1a06f000 { 1901 compatible = "mediatek,mt8186-camsys_rawb"; 1902 reg = <0 0x1a06f000 0 0x1000>; 1903 #clock-cells = <1>; 1904 }; 1905 1906 mdpsys: clock-controller@1b000000 { 1907 compatible = "mediatek,mt8186-mdpsys"; 1908 reg = <0 0x1b000000 0 0x1000>; 1909 #clock-cells = <1>; 1910 }; 1911 1912 larb2: smi@1b002000 { 1913 compatible = "mediatek,mt8186-smi-larb"; 1914 reg = <0 0x1b002000 0 0x1000>; 1915 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 1916 clock-names = "apb", "smi"; 1917 mediatek,larb-id = <2>; 1918 mediatek,smi = <&smi_common>; 1919 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1920 }; 1921 1922 ipesys: clock-controller@1c000000 { 1923 compatible = "mediatek,mt8186-ipesys"; 1924 reg = <0 0x1c000000 0 0x1000>; 1925 #clock-cells = <1>; 1926 }; 1927 1928 larb20: smi@1c00f000 { 1929 compatible = "mediatek,mt8186-smi-larb"; 1930 reg = <0 0x1c00f000 0 0x1000>; 1931 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 1932 clock-names = "apb", "smi"; 1933 mediatek,larb-id = <20>; 1934 mediatek,smi = <&smi_common>; 1935 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1936 }; 1937 1938 larb19: smi@1c10f000 { 1939 compatible = "mediatek,mt8186-smi-larb"; 1940 reg = <0 0x1c10f000 0 0x1000>; 1941 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 1942 clock-names = "apb", "smi"; 1943 mediatek,larb-id = <19>; 1944 mediatek,smi = <&smi_common>; 1945 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1946 }; 1947 }; 1948}; 1949