1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/gce/mt8186-gce.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/memory/mt8186-memory-port.h> 12#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 13#include <dt-bindings/power/mt8186-power.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/reset/mt8186-resets.h> 16 17/ { 18 compatible = "mediatek,mt8186"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 ovl0 = &ovl0; 25 ovl_2l0 = &ovl_2l0; 26 rdma0 = &rdma0; 27 rdma1 = &rdma1; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu-map { 35 cluster0 { 36 core0 { 37 cpu = <&cpu0>; 38 }; 39 40 core1 { 41 cpu = <&cpu1>; 42 }; 43 44 core2 { 45 cpu = <&cpu2>; 46 }; 47 48 core3 { 49 cpu = <&cpu3>; 50 }; 51 52 core4 { 53 cpu = <&cpu4>; 54 }; 55 56 core5 { 57 cpu = <&cpu5>; 58 }; 59 60 core6 { 61 cpu = <&cpu6>; 62 }; 63 64 core7 { 65 cpu = <&cpu7>; 66 }; 67 }; 68 }; 69 70 cpu0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a55"; 73 reg = <0x000>; 74 enable-method = "psci"; 75 clock-frequency = <2000000000>; 76 capacity-dmips-mhz = <382>; 77 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 78 i-cache-size = <32768>; 79 i-cache-line-size = <64>; 80 i-cache-sets = <128>; 81 d-cache-size = <32768>; 82 d-cache-line-size = <64>; 83 d-cache-sets = <128>; 84 next-level-cache = <&l2_0>; 85 #cooling-cells = <2>; 86 }; 87 88 cpu1: cpu@100 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a55"; 91 reg = <0x100>; 92 enable-method = "psci"; 93 clock-frequency = <2000000000>; 94 capacity-dmips-mhz = <382>; 95 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 96 i-cache-size = <32768>; 97 i-cache-line-size = <64>; 98 i-cache-sets = <128>; 99 d-cache-size = <32768>; 100 d-cache-line-size = <64>; 101 d-cache-sets = <128>; 102 next-level-cache = <&l2_0>; 103 #cooling-cells = <2>; 104 }; 105 106 cpu2: cpu@200 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a55"; 109 reg = <0x200>; 110 enable-method = "psci"; 111 clock-frequency = <2000000000>; 112 capacity-dmips-mhz = <382>; 113 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 114 i-cache-size = <32768>; 115 i-cache-line-size = <64>; 116 i-cache-sets = <128>; 117 d-cache-size = <32768>; 118 d-cache-line-size = <64>; 119 d-cache-sets = <128>; 120 next-level-cache = <&l2_0>; 121 #cooling-cells = <2>; 122 }; 123 124 cpu3: cpu@300 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a55"; 127 reg = <0x300>; 128 enable-method = "psci"; 129 clock-frequency = <2000000000>; 130 capacity-dmips-mhz = <382>; 131 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 132 i-cache-size = <32768>; 133 i-cache-line-size = <64>; 134 i-cache-sets = <128>; 135 d-cache-size = <32768>; 136 d-cache-line-size = <64>; 137 d-cache-sets = <128>; 138 next-level-cache = <&l2_0>; 139 #cooling-cells = <2>; 140 }; 141 142 cpu4: cpu@400 { 143 device_type = "cpu"; 144 compatible = "arm,cortex-a55"; 145 reg = <0x400>; 146 enable-method = "psci"; 147 clock-frequency = <2000000000>; 148 capacity-dmips-mhz = <382>; 149 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 150 i-cache-size = <32768>; 151 i-cache-line-size = <64>; 152 i-cache-sets = <128>; 153 d-cache-size = <32768>; 154 d-cache-line-size = <64>; 155 d-cache-sets = <128>; 156 next-level-cache = <&l2_0>; 157 #cooling-cells = <2>; 158 }; 159 160 cpu5: cpu@500 { 161 device_type = "cpu"; 162 compatible = "arm,cortex-a55"; 163 reg = <0x500>; 164 enable-method = "psci"; 165 clock-frequency = <2000000000>; 166 capacity-dmips-mhz = <382>; 167 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 168 i-cache-size = <32768>; 169 i-cache-line-size = <64>; 170 i-cache-sets = <128>; 171 d-cache-size = <32768>; 172 d-cache-line-size = <64>; 173 d-cache-sets = <128>; 174 next-level-cache = <&l2_0>; 175 #cooling-cells = <2>; 176 }; 177 178 cpu6: cpu@600 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a76"; 181 reg = <0x600>; 182 enable-method = "psci"; 183 clock-frequency = <2050000000>; 184 capacity-dmips-mhz = <1024>; 185 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 186 i-cache-size = <65536>; 187 i-cache-line-size = <64>; 188 i-cache-sets = <256>; 189 d-cache-size = <65536>; 190 d-cache-line-size = <64>; 191 d-cache-sets = <256>; 192 next-level-cache = <&l2_1>; 193 #cooling-cells = <2>; 194 }; 195 196 cpu7: cpu@700 { 197 device_type = "cpu"; 198 compatible = "arm,cortex-a76"; 199 reg = <0x700>; 200 enable-method = "psci"; 201 clock-frequency = <2050000000>; 202 capacity-dmips-mhz = <1024>; 203 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 204 i-cache-size = <65536>; 205 i-cache-line-size = <64>; 206 i-cache-sets = <256>; 207 d-cache-size = <65536>; 208 d-cache-line-size = <64>; 209 d-cache-sets = <256>; 210 next-level-cache = <&l2_1>; 211 #cooling-cells = <2>; 212 }; 213 214 idle-states { 215 entry-method = "psci"; 216 217 cpu_ret_l: cpu-retention-l { 218 compatible = "arm,idle-state"; 219 arm,psci-suspend-param = <0x00010001>; 220 local-timer-stop; 221 entry-latency-us = <50>; 222 exit-latency-us = <100>; 223 min-residency-us = <1600>; 224 }; 225 226 cpu_ret_b: cpu-retention-b { 227 compatible = "arm,idle-state"; 228 arm,psci-suspend-param = <0x00010001>; 229 local-timer-stop; 230 entry-latency-us = <50>; 231 exit-latency-us = <100>; 232 min-residency-us = <1400>; 233 }; 234 235 cpu_off_l: cpu-off-l { 236 compatible = "arm,idle-state"; 237 arm,psci-suspend-param = <0x01010001>; 238 local-timer-stop; 239 entry-latency-us = <100>; 240 exit-latency-us = <250>; 241 min-residency-us = <2100>; 242 }; 243 244 cpu_off_b: cpu-off-b { 245 compatible = "arm,idle-state"; 246 arm,psci-suspend-param = <0x01010001>; 247 local-timer-stop; 248 entry-latency-us = <100>; 249 exit-latency-us = <250>; 250 min-residency-us = <1900>; 251 }; 252 }; 253 254 l2_0: l2-cache0 { 255 compatible = "cache"; 256 cache-level = <2>; 257 cache-size = <131072>; 258 cache-line-size = <64>; 259 cache-sets = <512>; 260 next-level-cache = <&l3_0>; 261 }; 262 263 l2_1: l2-cache1 { 264 compatible = "cache"; 265 cache-level = <2>; 266 cache-size = <262144>; 267 cache-line-size = <64>; 268 cache-sets = <512>; 269 next-level-cache = <&l3_0>; 270 }; 271 272 l3_0: l3-cache { 273 compatible = "cache"; 274 cache-level = <3>; 275 cache-size = <1048576>; 276 cache-line-size = <64>; 277 cache-sets = <1024>; 278 cache-unified; 279 }; 280 }; 281 282 clk13m: fixed-factor-clock-13m { 283 compatible = "fixed-factor-clock"; 284 #clock-cells = <0>; 285 clocks = <&clk26m>; 286 clock-div = <2>; 287 clock-mult = <1>; 288 clock-output-names = "clk13m"; 289 }; 290 291 clk26m: oscillator-26m { 292 compatible = "fixed-clock"; 293 #clock-cells = <0>; 294 clock-frequency = <26000000>; 295 clock-output-names = "clk26m"; 296 }; 297 298 clk32k: oscillator-32k { 299 compatible = "fixed-clock"; 300 #clock-cells = <0>; 301 clock-frequency = <32768>; 302 clock-output-names = "clk32k"; 303 }; 304 305 pmu-a55 { 306 compatible = "arm,cortex-a55-pmu"; 307 interrupt-parent = <&gic>; 308 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 309 }; 310 311 pmu-a76 { 312 compatible = "arm,cortex-a76-pmu"; 313 interrupt-parent = <&gic>; 314 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 315 }; 316 317 psci { 318 compatible = "arm,psci-1.0"; 319 method = "smc"; 320 }; 321 322 timer { 323 compatible = "arm,armv8-timer"; 324 interrupt-parent = <&gic>; 325 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 326 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 327 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 328 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 329 }; 330 331 soc { 332 #address-cells = <2>; 333 #size-cells = <2>; 334 compatible = "simple-bus"; 335 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 336 ranges; 337 338 gic: interrupt-controller@c000000 { 339 compatible = "arm,gic-v3"; 340 #interrupt-cells = <4>; 341 #redistributor-regions = <1>; 342 interrupt-parent = <&gic>; 343 interrupt-controller; 344 reg = <0 0x0c000000 0 0x40000>, 345 <0 0x0c040000 0 0x200000>; 346 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 347 348 ppi-partitions { 349 ppi_cluster0: interrupt-partition-0 { 350 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 351 }; 352 353 ppi_cluster1: interrupt-partition-1 { 354 affinity = <&cpu6 &cpu7>; 355 }; 356 }; 357 }; 358 359 mcusys: syscon@c53a000 { 360 compatible = "mediatek,mt8186-mcusys", "syscon"; 361 reg = <0 0xc53a000 0 0x1000>; 362 #clock-cells = <1>; 363 }; 364 365 topckgen: syscon@10000000 { 366 compatible = "mediatek,mt8186-topckgen", "syscon"; 367 reg = <0 0x10000000 0 0x1000>; 368 #clock-cells = <1>; 369 }; 370 371 infracfg_ao: syscon@10001000 { 372 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 373 reg = <0 0x10001000 0 0x1000>; 374 #clock-cells = <1>; 375 #reset-cells = <1>; 376 }; 377 378 pericfg: syscon@10003000 { 379 compatible = "mediatek,mt8186-pericfg", "syscon"; 380 reg = <0 0x10003000 0 0x1000>; 381 }; 382 383 pio: pinctrl@10005000 { 384 compatible = "mediatek,mt8186-pinctrl"; 385 reg = <0 0x10005000 0 0x1000>, 386 <0 0x10002000 0 0x0200>, 387 <0 0x10002200 0 0x0200>, 388 <0 0x10002400 0 0x0200>, 389 <0 0x10002600 0 0x0200>, 390 <0 0x10002a00 0 0x0200>, 391 <0 0x10002c00 0 0x0200>, 392 <0 0x1000b000 0 0x1000>; 393 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 394 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 395 gpio-controller; 396 #gpio-cells = <2>; 397 gpio-ranges = <&pio 0 0 185>; 398 interrupt-controller; 399 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 400 #interrupt-cells = <2>; 401 }; 402 403 scpsys: syscon@10006000 { 404 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 405 reg = <0 0x10006000 0 0x1000>; 406 407 /* System Power Manager */ 408 spm: power-controller { 409 compatible = "mediatek,mt8186-power-controller"; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 #power-domain-cells = <1>; 413 414 /* power domain of the SoC */ 415 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 416 reg = <MT8186_POWER_DOMAIN_MFG0>; 417 clocks = <&topckgen CLK_TOP_MFG>; 418 clock-names = "mfg00"; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 #power-domain-cells = <1>; 422 423 power-domain@MT8186_POWER_DOMAIN_MFG1 { 424 reg = <MT8186_POWER_DOMAIN_MFG1>; 425 mediatek,infracfg = <&infracfg_ao>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 #power-domain-cells = <1>; 429 430 power-domain@MT8186_POWER_DOMAIN_MFG2 { 431 reg = <MT8186_POWER_DOMAIN_MFG2>; 432 #power-domain-cells = <0>; 433 }; 434 435 power-domain@MT8186_POWER_DOMAIN_MFG3 { 436 reg = <MT8186_POWER_DOMAIN_MFG3>; 437 #power-domain-cells = <0>; 438 }; 439 }; 440 }; 441 442 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 443 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 444 clocks = <&topckgen CLK_TOP_SENINF>, 445 <&topckgen CLK_TOP_SENINF1>; 446 clock-names = "csirx_top0", "csirx_top1"; 447 #power-domain-cells = <0>; 448 }; 449 450 power-domain@MT8186_POWER_DOMAIN_SSUSB { 451 reg = <MT8186_POWER_DOMAIN_SSUSB>; 452 #power-domain-cells = <0>; 453 }; 454 455 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 456 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 457 #power-domain-cells = <0>; 458 }; 459 460 power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 461 reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 462 clocks = <&topckgen CLK_TOP_AUDIODSP>, 463 <&topckgen CLK_TOP_ADSP_BUS>; 464 clock-names = "audioadsp", "adsp_bus"; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 #power-domain-cells = <1>; 468 469 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 470 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 #power-domain-cells = <1>; 474 475 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 476 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 477 mediatek,infracfg = <&infracfg_ao>; 478 #power-domain-cells = <0>; 479 }; 480 }; 481 }; 482 483 power-domain@MT8186_POWER_DOMAIN_CONN_ON { 484 reg = <MT8186_POWER_DOMAIN_CONN_ON>; 485 mediatek,infracfg = <&infracfg_ao>; 486 #power-domain-cells = <0>; 487 }; 488 489 power-domain@MT8186_POWER_DOMAIN_DIS { 490 reg = <MT8186_POWER_DOMAIN_DIS>; 491 clocks = <&topckgen CLK_TOP_DISP>, 492 <&topckgen CLK_TOP_MDP>, 493 <&mmsys CLK_MM_SMI_INFRA>, 494 <&mmsys CLK_MM_SMI_COMMON>, 495 <&mmsys CLK_MM_SMI_GALS>, 496 <&mmsys CLK_MM_SMI_IOMMU>; 497 clock-names = "disp", "mdp", "smi_infra", "smi_common", 498 "smi_gals", "smi_iommu"; 499 mediatek,infracfg = <&infracfg_ao>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 #power-domain-cells = <1>; 503 504 power-domain@MT8186_POWER_DOMAIN_VDEC { 505 reg = <MT8186_POWER_DOMAIN_VDEC>; 506 clocks = <&topckgen CLK_TOP_VDEC>, 507 <&vdecsys CLK_VDEC_LARB1_CKEN>; 508 clock-names = "vdec0", "larb"; 509 mediatek,infracfg = <&infracfg_ao>; 510 #power-domain-cells = <0>; 511 }; 512 513 power-domain@MT8186_POWER_DOMAIN_CAM { 514 reg = <MT8186_POWER_DOMAIN_CAM>; 515 clocks = <&topckgen CLK_TOP_CAM>, 516 <&topckgen CLK_TOP_SENINF>, 517 <&topckgen CLK_TOP_SENINF1>, 518 <&topckgen CLK_TOP_SENINF2>, 519 <&topckgen CLK_TOP_SENINF3>, 520 <&topckgen CLK_TOP_CAMTM>, 521 <&camsys CLK_CAM2MM_GALS>; 522 clock-names = "cam-top", "cam0", "cam1", "cam2", 523 "cam3", "cam-tm", "gals"; 524 mediatek,infracfg = <&infracfg_ao>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 #power-domain-cells = <1>; 528 529 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 530 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 531 #power-domain-cells = <0>; 532 }; 533 534 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 535 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 536 #power-domain-cells = <0>; 537 }; 538 }; 539 540 power-domain@MT8186_POWER_DOMAIN_IMG { 541 reg = <MT8186_POWER_DOMAIN_IMG>; 542 clocks = <&topckgen CLK_TOP_IMG1>, 543 <&imgsys1 CLK_IMG1_GALS_IMG1>; 544 clock-names = "img-top", "gals"; 545 mediatek,infracfg = <&infracfg_ao>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 #power-domain-cells = <1>; 549 550 power-domain@MT8186_POWER_DOMAIN_IMG2 { 551 reg = <MT8186_POWER_DOMAIN_IMG2>; 552 #power-domain-cells = <0>; 553 }; 554 }; 555 556 power-domain@MT8186_POWER_DOMAIN_IPE { 557 reg = <MT8186_POWER_DOMAIN_IPE>; 558 clocks = <&topckgen CLK_TOP_IPE>, 559 <&ipesys CLK_IPE_LARB19>, 560 <&ipesys CLK_IPE_LARB20>, 561 <&ipesys CLK_IPE_SMI_SUBCOM>, 562 <&ipesys CLK_IPE_GALS_IPE>; 563 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", 564 "ipe-smi", "ipe-gals"; 565 mediatek,infracfg = <&infracfg_ao>; 566 #power-domain-cells = <0>; 567 }; 568 569 power-domain@MT8186_POWER_DOMAIN_VENC { 570 reg = <MT8186_POWER_DOMAIN_VENC>; 571 clocks = <&topckgen CLK_TOP_VENC>, 572 <&vencsys CLK_VENC_CKE1_VENC>; 573 clock-names = "venc0", "larb"; 574 mediatek,infracfg = <&infracfg_ao>; 575 #power-domain-cells = <0>; 576 }; 577 578 power-domain@MT8186_POWER_DOMAIN_WPE { 579 reg = <MT8186_POWER_DOMAIN_WPE>; 580 clocks = <&topckgen CLK_TOP_WPE>, 581 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 582 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 583 clock-names = "wpe0", "larb-ck", "larb-pclk"; 584 mediatek,infracfg = <&infracfg_ao>; 585 #power-domain-cells = <0>; 586 }; 587 }; 588 }; 589 }; 590 591 watchdog: watchdog@10007000 { 592 compatible = "mediatek,mt8186-wdt"; 593 mediatek,disable-extrst; 594 reg = <0 0x10007000 0 0x1000>; 595 #reset-cells = <1>; 596 }; 597 598 apmixedsys: syscon@1000c000 { 599 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 600 reg = <0 0x1000c000 0 0x1000>; 601 #clock-cells = <1>; 602 }; 603 604 pwrap: pwrap@1000d000 { 605 compatible = "mediatek,mt8186-pwrap", "syscon"; 606 reg = <0 0x1000d000 0 0x1000>; 607 reg-names = "pwrap"; 608 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 609 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 610 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 611 clock-names = "spi", "wrap"; 612 }; 613 614 spmi: spmi@10015000 { 615 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; 616 reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; 617 reg-names = "pmif", "spmimst"; 618 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 619 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 620 <&topckgen CLK_TOP_SPMI_MST>; 621 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 622 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; 623 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 624 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>, 625 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>; 626 status = "disabled"; 627 }; 628 629 systimer: timer@10017000 { 630 compatible = "mediatek,mt8186-timer", 631 "mediatek,mt6765-timer"; 632 reg = <0 0x10017000 0 0x1000>; 633 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 634 clocks = <&clk13m>; 635 }; 636 637 gce: mailbox@1022c000 { 638 compatible = "mediatek,mt8186-gce"; 639 reg = <0 0X1022c000 0 0x4000>; 640 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 641 clock-names = "gce"; 642 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 643 #mbox-cells = <2>; 644 }; 645 646 scp: scp@10500000 { 647 compatible = "mediatek,mt8186-scp"; 648 reg = <0 0x10500000 0 0x40000>, 649 <0 0x105c0000 0 0x19080>; 650 reg-names = "sram", "cfg"; 651 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 652 }; 653 654 adsp: adsp@10680000 { 655 compatible = "mediatek,mt8186-dsp"; 656 reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, 657 <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; 658 reg-names = "cfg", "sram", "sec", "bus"; 659 clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; 660 clock-names = "audiodsp", "adsp_bus"; 661 assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, 662 <&topckgen CLK_TOP_ADSP_BUS>; 663 assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; 664 mbox-names = "rx", "tx"; 665 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 666 power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; 667 status = "disabled"; 668 }; 669 670 adsp_mailbox0: mailbox@10686000 { 671 compatible = "mediatek,mt8186-adsp-mbox"; 672 #mbox-cells = <0>; 673 reg = <0 0x10686100 0 0x1000>; 674 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 675 }; 676 677 adsp_mailbox1: mailbox@10687000 { 678 compatible = "mediatek,mt8186-adsp-mbox"; 679 #mbox-cells = <0>; 680 reg = <0 0x10687100 0 0x1000>; 681 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>; 682 }; 683 684 nor_flash: spi@11000000 { 685 compatible = "mediatek,mt8186-nor"; 686 reg = <0 0x11000000 0 0x1000>; 687 clocks = <&topckgen CLK_TOP_SPINOR>, 688 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 689 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 690 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 691 clock-names = "spi", "sf", "axi", "axi_s"; 692 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 693 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 694 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 695 status = "disabled"; 696 }; 697 698 auxadc: adc@11001000 { 699 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 700 reg = <0 0x11001000 0 0x1000>; 701 #io-channel-cells = <1>; 702 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 703 clock-names = "main"; 704 }; 705 706 uart0: serial@11002000 { 707 compatible = "mediatek,mt8186-uart", 708 "mediatek,mt6577-uart"; 709 reg = <0 0x11002000 0 0x1000>; 710 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 711 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 712 clock-names = "baud", "bus"; 713 status = "disabled"; 714 }; 715 716 uart1: serial@11003000 { 717 compatible = "mediatek,mt8186-uart", 718 "mediatek,mt6577-uart"; 719 reg = <0 0x11003000 0 0x1000>; 720 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 721 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 722 clock-names = "baud", "bus"; 723 status = "disabled"; 724 }; 725 726 i2c0: i2c@11007000 { 727 compatible = "mediatek,mt8186-i2c"; 728 reg = <0 0x11007000 0 0x1000>, 729 <0 0x10200100 0 0x100>; 730 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 731 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 732 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 733 clock-names = "main", "dma"; 734 clock-div = <1>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 status = "disabled"; 738 }; 739 740 i2c1: i2c@11008000 { 741 compatible = "mediatek,mt8186-i2c"; 742 reg = <0 0x11008000 0 0x1000>, 743 <0 0x10200200 0 0x100>; 744 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 745 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 746 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 747 clock-names = "main", "dma"; 748 clock-div = <1>; 749 #address-cells = <1>; 750 #size-cells = <0>; 751 status = "disabled"; 752 }; 753 754 i2c2: i2c@11009000 { 755 compatible = "mediatek,mt8186-i2c"; 756 reg = <0 0x11009000 0 0x1000>, 757 <0 0x10200300 0 0x180>; 758 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 759 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 760 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 761 clock-names = "main", "dma"; 762 clock-div = <1>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 status = "disabled"; 766 }; 767 768 i2c3: i2c@1100f000 { 769 compatible = "mediatek,mt8186-i2c"; 770 reg = <0 0x1100f000 0 0x1000>, 771 <0 0x10200480 0 0x100>; 772 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 773 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 774 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 775 clock-names = "main", "dma"; 776 clock-div = <1>; 777 #address-cells = <1>; 778 #size-cells = <0>; 779 status = "disabled"; 780 }; 781 782 i2c4: i2c@11011000 { 783 compatible = "mediatek,mt8186-i2c"; 784 reg = <0 0x11011000 0 0x1000>, 785 <0 0x10200580 0 0x180>; 786 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 787 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 788 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 789 clock-names = "main", "dma"; 790 clock-div = <1>; 791 #address-cells = <1>; 792 #size-cells = <0>; 793 status = "disabled"; 794 }; 795 796 i2c5: i2c@11016000 { 797 compatible = "mediatek,mt8186-i2c"; 798 reg = <0 0x11016000 0 0x1000>, 799 <0 0x10200700 0 0x100>; 800 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 801 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 802 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 803 clock-names = "main", "dma"; 804 clock-div = <1>; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 status = "disabled"; 808 }; 809 810 i2c6: i2c@1100d000 { 811 compatible = "mediatek,mt8186-i2c"; 812 reg = <0 0x1100d000 0 0x1000>, 813 <0 0x10200800 0 0x100>; 814 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 815 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 816 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 817 clock-names = "main", "dma"; 818 clock-div = <1>; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 status = "disabled"; 822 }; 823 824 i2c7: i2c@11004000 { 825 compatible = "mediatek,mt8186-i2c"; 826 reg = <0 0x11004000 0 0x1000>, 827 <0 0x10200900 0 0x180>; 828 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 829 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 830 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 831 clock-names = "main", "dma"; 832 clock-div = <1>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 status = "disabled"; 836 }; 837 838 i2c8: i2c@11005000 { 839 compatible = "mediatek,mt8186-i2c"; 840 reg = <0 0x11005000 0 0x1000>, 841 <0 0x10200A80 0 0x180>; 842 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 843 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 844 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 845 clock-names = "main", "dma"; 846 clock-div = <1>; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 status = "disabled"; 850 }; 851 852 spi0: spi@1100a000 { 853 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 reg = <0 0x1100a000 0 0x1000>; 857 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 858 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 859 <&topckgen CLK_TOP_SPI>, 860 <&infracfg_ao CLK_INFRA_AO_SPI0>; 861 clock-names = "parent-clk", "sel-clk", "spi-clk"; 862 status = "disabled"; 863 }; 864 865 pwm0: pwm@1100e000 { 866 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 867 reg = <0 0x1100e000 0 0x1000>; 868 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 869 #pwm-cells = <2>; 870 clocks = <&topckgen CLK_TOP_DISP_PWM>, 871 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 872 clock-names = "main", "mm"; 873 status = "disabled"; 874 }; 875 876 spi1: spi@11010000 { 877 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 reg = <0 0x11010000 0 0x1000>; 881 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 882 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 883 <&topckgen CLK_TOP_SPI>, 884 <&infracfg_ao CLK_INFRA_AO_SPI1>; 885 clock-names = "parent-clk", "sel-clk", "spi-clk"; 886 status = "disabled"; 887 }; 888 889 spi2: spi@11012000 { 890 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 reg = <0 0x11012000 0 0x1000>; 894 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 895 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 896 <&topckgen CLK_TOP_SPI>, 897 <&infracfg_ao CLK_INFRA_AO_SPI2>; 898 clock-names = "parent-clk", "sel-clk", "spi-clk"; 899 status = "disabled"; 900 }; 901 902 spi3: spi@11013000 { 903 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 904 #address-cells = <1>; 905 #size-cells = <0>; 906 reg = <0 0x11013000 0 0x1000>; 907 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 908 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 909 <&topckgen CLK_TOP_SPI>, 910 <&infracfg_ao CLK_INFRA_AO_SPI3>; 911 clock-names = "parent-clk", "sel-clk", "spi-clk"; 912 status = "disabled"; 913 }; 914 915 spi4: spi@11014000 { 916 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 reg = <0 0x11014000 0 0x1000>; 920 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 921 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 922 <&topckgen CLK_TOP_SPI>, 923 <&infracfg_ao CLK_INFRA_AO_SPI4>; 924 clock-names = "parent-clk", "sel-clk", "spi-clk"; 925 status = "disabled"; 926 }; 927 928 spi5: spi@11015000 { 929 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 reg = <0 0x11015000 0 0x1000>; 933 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 934 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 935 <&topckgen CLK_TOP_SPI>, 936 <&infracfg_ao CLK_INFRA_AO_SPI5>; 937 clock-names = "parent-clk", "sel-clk", "spi-clk"; 938 status = "disabled"; 939 }; 940 941 imp_iic_wrap: clock-controller@11017000 { 942 compatible = "mediatek,mt8186-imp_iic_wrap"; 943 reg = <0 0x11017000 0 0x1000>; 944 #clock-cells = <1>; 945 }; 946 947 uart2: serial@11018000 { 948 compatible = "mediatek,mt8186-uart", 949 "mediatek,mt6577-uart"; 950 reg = <0 0x11018000 0 0x1000>; 951 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 952 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 953 clock-names = "baud", "bus"; 954 status = "disabled"; 955 }; 956 957 i2c9: i2c@11019000 { 958 compatible = "mediatek,mt8186-i2c"; 959 reg = <0 0x11019000 0 0x1000>, 960 <0 0x10200c00 0 0x180>; 961 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 962 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 963 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 964 clock-names = "main", "dma"; 965 clock-div = <1>; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 status = "disabled"; 969 }; 970 971 afe: audio-controller@11210000 { 972 compatible = "mediatek,mt8186-sound"; 973 reg = <0 0x11210000 0 0x2000>; 974 clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, 975 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, 976 <&topckgen CLK_TOP_AUDIO>, 977 <&topckgen CLK_TOP_AUD_INTBUS>, 978 <&topckgen CLK_TOP_MAINPLL_D2_D4>, 979 <&topckgen CLK_TOP_AUD_1>, 980 <&apmixedsys CLK_APMIXED_APLL1>, 981 <&topckgen CLK_TOP_AUD_2>, 982 <&apmixedsys CLK_APMIXED_APLL2>, 983 <&topckgen CLK_TOP_AUD_ENGEN1>, 984 <&topckgen CLK_TOP_APLL1_D8>, 985 <&topckgen CLK_TOP_AUD_ENGEN2>, 986 <&topckgen CLK_TOP_APLL2_D8>, 987 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, 988 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, 989 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, 990 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, 991 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, 992 <&topckgen CLK_TOP_APLL12_CK_DIV0>, 993 <&topckgen CLK_TOP_APLL12_CK_DIV1>, 994 <&topckgen CLK_TOP_APLL12_CK_DIV2>, 995 <&topckgen CLK_TOP_APLL12_CK_DIV4>, 996 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, 997 <&topckgen CLK_TOP_AUDIO_H>, 998 <&clk26m>; 999 clock-names = "aud_infra_clk", 1000 "mtkaif_26m_clk", 1001 "top_mux_audio", 1002 "top_mux_audio_int", 1003 "top_mainpll_d2_d4", 1004 "top_mux_aud_1", 1005 "top_apll1_ck", 1006 "top_mux_aud_2", 1007 "top_apll2_ck", 1008 "top_mux_aud_eng1", 1009 "top_apll1_d8", 1010 "top_mux_aud_eng2", 1011 "top_apll2_d8", 1012 "top_i2s0_m_sel", 1013 "top_i2s1_m_sel", 1014 "top_i2s2_m_sel", 1015 "top_i2s4_m_sel", 1016 "top_tdm_m_sel", 1017 "top_apll12_div0", 1018 "top_apll12_div1", 1019 "top_apll12_div2", 1020 "top_apll12_div4", 1021 "top_apll12_div_tdm", 1022 "top_mux_audio_h", 1023 "top_clk26m_clk"; 1024 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1025 mediatek,apmixedsys = <&apmixedsys>; 1026 mediatek,infracfg = <&infracfg_ao>; 1027 mediatek,topckgen = <&topckgen>; 1028 resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; 1029 reset-names = "audiosys"; 1030 status = "disabled"; 1031 }; 1032 1033 ssusb0: usb@11201000 { 1034 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1035 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1036 reg-names = "mac", "ippc"; 1037 clocks = <&topckgen CLK_TOP_USB_TOP>, 1038 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1039 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1040 <&infracfg_ao CLK_INFRA_AO_ICUSB>; 1041 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1042 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>; 1043 phys = <&u2port0 PHY_TYPE_USB2>; 1044 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; 1045 #address-cells = <2>; 1046 #size-cells = <2>; 1047 ranges; 1048 status = "disabled"; 1049 1050 usb_host0: usb@11200000 { 1051 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1052 reg = <0 0x11200000 0 0x1000>; 1053 reg-names = "mac"; 1054 clocks = <&topckgen CLK_TOP_USB_TOP>, 1055 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1056 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1057 <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1058 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1059 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1060 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 1061 mediatek,syscon-wakeup = <&pericfg 0x420 2>; 1062 wakeup-source; 1063 status = "disabled"; 1064 }; 1065 }; 1066 1067 mmc0: mmc@11230000 { 1068 compatible = "mediatek,mt8186-mmc", 1069 "mediatek,mt8183-mmc"; 1070 reg = <0 0x11230000 0 0x10000>, 1071 <0 0x11cd0000 0 0x1000>; 1072 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1073 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1074 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1075 <&infracfg_ao CLK_INFRA_AO_MSDCFDE>; 1076 clock-names = "source", "hclk", "source_cg", "crypto"; 1077 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 1078 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 1079 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 1080 status = "disabled"; 1081 }; 1082 1083 mmc1: mmc@11240000 { 1084 compatible = "mediatek,mt8186-mmc", 1085 "mediatek,mt8183-mmc"; 1086 reg = <0 0x11240000 0 0x1000>, 1087 <0 0x11c90000 0 0x1000>; 1088 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1089 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1090 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1091 clock-names = "source", "hclk", "source_cg"; 1092 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 1093 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1094 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1095 status = "disabled"; 1096 }; 1097 1098 ssusb1: usb@11281000 { 1099 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1100 reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; 1101 reg-names = "mac", "ippc"; 1102 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1103 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1104 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1105 <&clk26m>; 1106 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1107 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 1108 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1109 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; 1110 #address-cells = <2>; 1111 #size-cells = <2>; 1112 ranges; 1113 status = "disabled"; 1114 1115 usb_host1: usb@11280000 { 1116 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1117 reg = <0 0x11280000 0 0x1000>; 1118 reg-names = "mac"; 1119 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1120 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1121 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1122 <&clk26m>, 1123 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1124 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; 1125 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1126 mediatek,syscon-wakeup = <&pericfg 0x424 2>; 1127 wakeup-source; 1128 status = "disabled"; 1129 }; 1130 }; 1131 1132 u3phy0: t-phy@11c80000 { 1133 compatible = "mediatek,mt8186-tphy", 1134 "mediatek,generic-tphy-v2"; 1135 #address-cells = <1>; 1136 #size-cells = <1>; 1137 ranges = <0x0 0x0 0x11c80000 0x1000>; 1138 status = "disabled"; 1139 1140 u2port1: usb-phy@0 { 1141 reg = <0x0 0x700>; 1142 clocks = <&clk26m>; 1143 clock-names = "ref"; 1144 #phy-cells = <1>; 1145 }; 1146 1147 u3port1: usb-phy@700 { 1148 reg = <0x700 0x900>; 1149 clocks = <&clk26m>; 1150 clock-names = "ref"; 1151 #phy-cells = <1>; 1152 }; 1153 }; 1154 1155 u3phy1: t-phy@11ca0000 { 1156 compatible = "mediatek,mt8186-tphy", 1157 "mediatek,generic-tphy-v2"; 1158 #address-cells = <1>; 1159 #size-cells = <1>; 1160 ranges = <0x0 0x0 0x11ca0000 0x1000>; 1161 status = "disabled"; 1162 1163 u2port0: usb-phy@0 { 1164 reg = <0x0 0x700>; 1165 clocks = <&clk26m>; 1166 clock-names = "ref"; 1167 #phy-cells = <1>; 1168 mediatek,discth = <0x8>; 1169 }; 1170 }; 1171 1172 efuse: efuse@11cb0000 { 1173 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 1174 reg = <0 0x11cb0000 0 0x1000>; 1175 #address-cells = <1>; 1176 #size-cells = <1>; 1177 }; 1178 1179 mipi_tx0: dsi-phy@11cc0000 { 1180 compatible = "mediatek,mt8183-mipi-tx"; 1181 reg = <0 0x11cc0000 0 0x1000>; 1182 clocks = <&clk26m>; 1183 #clock-cells = <0>; 1184 #phy-cells = <0>; 1185 clock-output-names = "mipi_tx0_pll"; 1186 status = "disabled"; 1187 }; 1188 1189 mfgsys: clock-controller@13000000 { 1190 compatible = "mediatek,mt8186-mfgsys"; 1191 reg = <0 0x13000000 0 0x1000>; 1192 #clock-cells = <1>; 1193 }; 1194 1195 gpu: gpu@13040000 { 1196 compatible = "mediatek,mt8186-mali", 1197 "arm,mali-bifrost"; 1198 reg = <0 0x13040000 0 0x4000>; 1199 1200 clocks = <&mfgsys CLK_MFG_BG3D>; 1201 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>, 1202 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>, 1203 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 1204 interrupt-names = "job", "mmu", "gpu"; 1205 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>, 1206 <&spm MT8186_POWER_DOMAIN_MFG3>; 1207 power-domain-names = "core0", "core1"; 1208 #cooling-cells = <2>; 1209 status = "disabled"; 1210 }; 1211 1212 mmsys: syscon@14000000 { 1213 compatible = "mediatek,mt8186-mmsys", "syscon"; 1214 reg = <0 0x14000000 0 0x1000>; 1215 #clock-cells = <1>; 1216 #reset-cells = <1>; 1217 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1218 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1219 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1220 }; 1221 1222 mutex: mutex@14001000 { 1223 compatible = "mediatek,mt8186-disp-mutex"; 1224 reg = <0 0x14001000 0 0x1000>; 1225 clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1226 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>; 1227 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1228 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1229 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1230 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1231 }; 1232 1233 smi_common: smi@14002000 { 1234 compatible = "mediatek,mt8186-smi-common"; 1235 reg = <0 0x14002000 0 0x1000>; 1236 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 1237 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 1238 clock-names = "apb", "smi", "gals0", "gals1"; 1239 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1240 }; 1241 1242 larb0: smi@14003000 { 1243 compatible = "mediatek,mt8186-smi-larb"; 1244 reg = <0 0x14003000 0 0x1000>; 1245 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1246 <&mmsys CLK_MM_SMI_COMMON>; 1247 clock-names = "apb", "smi"; 1248 mediatek,larb-id = <0>; 1249 mediatek,smi = <&smi_common>; 1250 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1251 }; 1252 1253 larb1: smi@14004000 { 1254 compatible = "mediatek,mt8186-smi-larb"; 1255 reg = <0 0x14004000 0 0x1000>; 1256 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1257 <&mmsys CLK_MM_SMI_COMMON>; 1258 clock-names = "apb", "smi"; 1259 mediatek,larb-id = <1>; 1260 mediatek,smi = <&smi_common>; 1261 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1262 }; 1263 1264 ovl0: ovl@14005000 { 1265 compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl"; 1266 reg = <0 0x14005000 0 0x1000>; 1267 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1268 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; 1269 iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; 1270 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1271 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1272 }; 1273 1274 ovl_2l0: ovl@14006000 { 1275 compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l"; 1276 reg = <0 0x14006000 0 0x1000>; 1277 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1278 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 1279 iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; 1280 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1281 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1282 }; 1283 1284 rdma0: rdma@14007000 { 1285 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1286 reg = <0 0x14007000 0 0x1000>; 1287 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1288 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>; 1289 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; 1290 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1291 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1292 }; 1293 1294 color: color@14009000 { 1295 compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color"; 1296 reg = <0 0x14009000 0 0x1000>; 1297 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1298 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>; 1299 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1300 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1301 }; 1302 1303 dpi: dpi@1400a000 { 1304 compatible = "mediatek,mt8186-dpi"; 1305 reg = <0 0x1400a000 0 0x1000>; 1306 clocks = <&topckgen CLK_TOP_DPI>, 1307 <&mmsys CLK_MM_DISP_DPI>, 1308 <&apmixedsys CLK_APMIXED_TVDPLL>; 1309 clock-names = "pixel", "engine", "pll"; 1310 assigned-clocks = <&topckgen CLK_TOP_DPI>; 1311 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; 1312 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; 1313 status = "disabled"; 1314 1315 port { 1316 dpi_out: endpoint { }; 1317 }; 1318 }; 1319 1320 ccorr: ccorr@1400b000 { 1321 compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 1322 reg = <0 0x1400b000 0 0x1000>; 1323 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1324 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>; 1325 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1326 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1327 }; 1328 1329 aal: aal@1400c000 { 1330 compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal"; 1331 reg = <0 0x1400c000 0 0x1000>; 1332 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1333 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>; 1334 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1335 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1336 }; 1337 1338 gamma: gamma@1400d000 { 1339 compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma"; 1340 reg = <0 0x1400d000 0 0x1000>; 1341 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1342 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 1343 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1344 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1345 }; 1346 1347 postmask: postmask@1400e000 { 1348 compatible = "mediatek,mt8186-disp-postmask", 1349 "mediatek,mt8192-disp-postmask"; 1350 reg = <0 0x1400e000 0 0x1000>; 1351 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1352 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 1353 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1354 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1355 }; 1356 1357 dither: dither@1400f000 { 1358 compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither"; 1359 reg = <0 0x1400f000 0 0x1000>; 1360 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1361 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>; 1362 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1363 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1364 }; 1365 1366 dsi0: dsi@14013000 { 1367 compatible = "mediatek,mt8186-dsi"; 1368 reg = <0 0x14013000 0 0x1000>; 1369 clocks = <&mmsys CLK_MM_DSI0>, 1370 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 1371 <&mipi_tx0>; 1372 clock-names = "engine", "digital", "hs"; 1373 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 1374 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1375 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 1376 phys = <&mipi_tx0>; 1377 phy-names = "dphy"; 1378 status = "disabled"; 1379 1380 port { 1381 dsi_out: endpoint { }; 1382 }; 1383 }; 1384 1385 iommu_mm: iommu@14016000 { 1386 compatible = "mediatek,mt8186-iommu-mm"; 1387 reg = <0 0x14016000 0 0x1000>; 1388 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1389 clock-names = "bclk"; 1390 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1391 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1392 &larb7 &larb8 &larb9 &larb11 1393 &larb13 &larb14 &larb16 &larb17 1394 &larb19 &larb20>; 1395 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1396 #iommu-cells = <1>; 1397 }; 1398 1399 rdma1: rdma@1401f000 { 1400 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1401 reg = <0 0x1401f000 0 0x1000>; 1402 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1403 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>; 1404 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; 1405 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>; 1406 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1407 }; 1408 1409 wpesys: clock-controller@14020000 { 1410 compatible = "mediatek,mt8186-wpesys"; 1411 reg = <0 0x14020000 0 0x1000>; 1412 #clock-cells = <1>; 1413 }; 1414 1415 larb8: smi@14023000 { 1416 compatible = "mediatek,mt8186-smi-larb"; 1417 reg = <0 0x14023000 0 0x1000>; 1418 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1419 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1420 clock-names = "apb", "smi"; 1421 mediatek,larb-id = <8>; 1422 mediatek,smi = <&smi_common>; 1423 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1424 }; 1425 1426 imgsys1: clock-controller@15020000 { 1427 compatible = "mediatek,mt8186-imgsys1"; 1428 reg = <0 0x15020000 0 0x1000>; 1429 #clock-cells = <1>; 1430 }; 1431 1432 larb9: smi@1502e000 { 1433 compatible = "mediatek,mt8186-smi-larb"; 1434 reg = <0 0x1502e000 0 0x1000>; 1435 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1436 <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1437 clock-names = "apb", "smi"; 1438 mediatek,larb-id = <9>; 1439 mediatek,smi = <&smi_common>; 1440 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 1441 }; 1442 1443 imgsys2: clock-controller@15820000 { 1444 compatible = "mediatek,mt8186-imgsys2"; 1445 reg = <0 0x15820000 0 0x1000>; 1446 #clock-cells = <1>; 1447 }; 1448 1449 larb11: smi@1582e000 { 1450 compatible = "mediatek,mt8186-smi-larb"; 1451 reg = <0 0x1582e000 0 0x1000>; 1452 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 1453 <&imgsys2 CLK_IMG2_LARB9_IMG2>; 1454 clock-names = "apb", "smi"; 1455 mediatek,larb-id = <11>; 1456 mediatek,smi = <&smi_common>; 1457 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 1458 }; 1459 1460 larb4: smi@1602e000 { 1461 compatible = "mediatek,mt8186-smi-larb"; 1462 reg = <0 0x1602e000 0 0x1000>; 1463 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 1464 <&vdecsys CLK_VDEC_LARB1_CKEN>; 1465 clock-names = "apb", "smi"; 1466 mediatek,larb-id = <4>; 1467 mediatek,smi = <&smi_common>; 1468 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 1469 }; 1470 1471 vdecsys: clock-controller@1602f000 { 1472 compatible = "mediatek,mt8186-vdecsys"; 1473 reg = <0 0x1602f000 0 0x1000>; 1474 #clock-cells = <1>; 1475 }; 1476 1477 vencsys: clock-controller@17000000 { 1478 compatible = "mediatek,mt8186-vencsys"; 1479 reg = <0 0x17000000 0 0x1000>; 1480 #clock-cells = <1>; 1481 }; 1482 1483 larb7: smi@17010000 { 1484 compatible = "mediatek,mt8186-smi-larb"; 1485 reg = <0 0x17010000 0 0x1000>; 1486 clocks = <&vencsys CLK_VENC_CKE1_VENC>, 1487 <&vencsys CLK_VENC_CKE1_VENC>; 1488 clock-names = "apb", "smi"; 1489 mediatek,larb-id = <7>; 1490 mediatek,smi = <&smi_common>; 1491 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 1492 }; 1493 1494 camsys: clock-controller@1a000000 { 1495 compatible = "mediatek,mt8186-camsys"; 1496 reg = <0 0x1a000000 0 0x1000>; 1497 #clock-cells = <1>; 1498 }; 1499 1500 larb13: smi@1a001000 { 1501 compatible = "mediatek,mt8186-smi-larb"; 1502 reg = <0 0x1a001000 0 0x1000>; 1503 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 1504 clock-names = "apb", "smi"; 1505 mediatek,larb-id = <13>; 1506 mediatek,smi = <&smi_common>; 1507 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1508 }; 1509 1510 larb14: smi@1a002000 { 1511 compatible = "mediatek,mt8186-smi-larb"; 1512 reg = <0 0x1a002000 0 0x1000>; 1513 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 1514 clock-names = "apb", "smi"; 1515 mediatek,larb-id = <14>; 1516 mediatek,smi = <&smi_common>; 1517 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1518 }; 1519 1520 larb16: smi@1a00f000 { 1521 compatible = "mediatek,mt8186-smi-larb"; 1522 reg = <0 0x1a00f000 0 0x1000>; 1523 clocks = <&camsys CLK_CAM_LARB14>, 1524 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 1525 clock-names = "apb", "smi"; 1526 mediatek,larb-id = <16>; 1527 mediatek,smi = <&smi_common>; 1528 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 1529 }; 1530 1531 larb17: smi@1a010000 { 1532 compatible = "mediatek,mt8186-smi-larb"; 1533 reg = <0 0x1a010000 0 0x1000>; 1534 clocks = <&camsys CLK_CAM_LARB13>, 1535 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 1536 clock-names = "apb", "smi"; 1537 mediatek,larb-id = <17>; 1538 mediatek,smi = <&smi_common>; 1539 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 1540 }; 1541 1542 camsys_rawa: clock-controller@1a04f000 { 1543 compatible = "mediatek,mt8186-camsys_rawa"; 1544 reg = <0 0x1a04f000 0 0x1000>; 1545 #clock-cells = <1>; 1546 }; 1547 1548 camsys_rawb: clock-controller@1a06f000 { 1549 compatible = "mediatek,mt8186-camsys_rawb"; 1550 reg = <0 0x1a06f000 0 0x1000>; 1551 #clock-cells = <1>; 1552 }; 1553 1554 mdpsys: clock-controller@1b000000 { 1555 compatible = "mediatek,mt8186-mdpsys"; 1556 reg = <0 0x1b000000 0 0x1000>; 1557 #clock-cells = <1>; 1558 }; 1559 1560 larb2: smi@1b002000 { 1561 compatible = "mediatek,mt8186-smi-larb"; 1562 reg = <0 0x1b002000 0 0x1000>; 1563 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 1564 clock-names = "apb", "smi"; 1565 mediatek,larb-id = <2>; 1566 mediatek,smi = <&smi_common>; 1567 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1568 }; 1569 1570 ipesys: clock-controller@1c000000 { 1571 compatible = "mediatek,mt8186-ipesys"; 1572 reg = <0 0x1c000000 0 0x1000>; 1573 #clock-cells = <1>; 1574 }; 1575 1576 larb20: smi@1c00f000 { 1577 compatible = "mediatek,mt8186-smi-larb"; 1578 reg = <0 0x1c00f000 0 0x1000>; 1579 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 1580 clock-names = "apb", "smi"; 1581 mediatek,larb-id = <20>; 1582 mediatek,smi = <&smi_common>; 1583 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1584 }; 1585 1586 larb19: smi@1c10f000 { 1587 compatible = "mediatek,mt8186-smi-larb"; 1588 reg = <0 0x1c10f000 0 0x1000>; 1589 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 1590 clock-names = "apb", "smi"; 1591 mediatek,larb-id = <19>; 1592 mediatek,smi = <&smi_common>; 1593 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1594 }; 1595 }; 1596}; 1597