1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/gce/mt8186-gce.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/memory/mt8186-memory-port.h> 12#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 13#include <dt-bindings/power/mt8186-power.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/reset/mt8186-resets.h> 16 17/ { 18 compatible = "mediatek,mt8186"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 ovl0 = &ovl0; 25 ovl_2l0 = &ovl_2l0; 26 rdma0 = &rdma0; 27 rdma1 = &rdma1; 28 }; 29 30 cci: cci { 31 compatible = "mediatek,mt8186-cci"; 32 clocks = <&mcusys CLK_MCU_ARMPLL_BUS_SEL>, 33 <&apmixedsys CLK_APMIXED_MAINPLL>; 34 clock-names = "cci", "intermediate"; 35 operating-points-v2 = <&cci_opp>; 36 }; 37 38 cci_opp: opp-table-cci { 39 compatible = "operating-points-v2"; 40 opp-shared; 41 42 cci_opp_0: opp-500000000 { 43 opp-hz = /bits/ 64 <500000000>; 44 opp-microvolt = <600000>; 45 }; 46 47 cci_opp_1: opp-560000000 { 48 opp-hz = /bits/ 64 <560000000>; 49 opp-microvolt = <675000>; 50 }; 51 52 cci_opp_2: opp-612000000 { 53 opp-hz = /bits/ 64 <612000000>; 54 opp-microvolt = <693750>; 55 }; 56 57 cci_opp_3: opp-682000000 { 58 opp-hz = /bits/ 64 <682000000>; 59 opp-microvolt = <718750>; 60 }; 61 62 cci_opp_4: opp-752000000 { 63 opp-hz = /bits/ 64 <752000000>; 64 opp-microvolt = <743750>; 65 }; 66 67 cci_opp_5: opp-822000000 { 68 opp-hz = /bits/ 64 <822000000>; 69 opp-microvolt = <768750>; 70 }; 71 72 cci_opp_6: opp-875000000 { 73 opp-hz = /bits/ 64 <875000000>; 74 opp-microvolt = <781250>; 75 }; 76 77 cci_opp_7: opp-927000000 { 78 opp-hz = /bits/ 64 <927000000>; 79 opp-microvolt = <800000>; 80 }; 81 82 cci_opp_8: opp-980000000 { 83 opp-hz = /bits/ 64 <980000000>; 84 opp-microvolt = <818750>; 85 }; 86 87 cci_opp_9: opp-1050000000 { 88 opp-hz = /bits/ 64 <1050000000>; 89 opp-microvolt = <843750>; 90 }; 91 92 cci_opp_10: opp-1120000000 { 93 opp-hz = /bits/ 64 <1120000000>; 94 opp-microvolt = <862500>; 95 }; 96 97 cci_opp_11: opp-1155000000 { 98 opp-hz = /bits/ 64 <1155000000>; 99 opp-microvolt = <887500>; 100 }; 101 102 cci_opp_12: opp-1190000000 { 103 opp-hz = /bits/ 64 <1190000000>; 104 opp-microvolt = <906250>; 105 }; 106 107 cci_opp_13: opp-1260000000 { 108 opp-hz = /bits/ 64 <1260000000>; 109 opp-microvolt = <950000>; 110 }; 111 112 cci_opp_14: opp-1330000000 { 113 opp-hz = /bits/ 64 <1330000000>; 114 opp-microvolt = <993750>; 115 }; 116 117 cci_opp_15: opp-1400000000 { 118 opp-hz = /bits/ 64 <1400000000>; 119 opp-microvolt = <1031250>; 120 }; 121 }; 122 123 cpus { 124 #address-cells = <1>; 125 #size-cells = <0>; 126 127 cpu-map { 128 cluster0 { 129 core0 { 130 cpu = <&cpu0>; 131 }; 132 133 core1 { 134 cpu = <&cpu1>; 135 }; 136 137 core2 { 138 cpu = <&cpu2>; 139 }; 140 141 core3 { 142 cpu = <&cpu3>; 143 }; 144 145 core4 { 146 cpu = <&cpu4>; 147 }; 148 149 core5 { 150 cpu = <&cpu5>; 151 }; 152 153 core6 { 154 cpu = <&cpu6>; 155 }; 156 157 core7 { 158 cpu = <&cpu7>; 159 }; 160 }; 161 }; 162 163 cpu0: cpu@0 { 164 device_type = "cpu"; 165 compatible = "arm,cortex-a55"; 166 reg = <0x000>; 167 enable-method = "psci"; 168 clock-frequency = <2000000000>; 169 capacity-dmips-mhz = <382>; 170 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 171 i-cache-size = <32768>; 172 i-cache-line-size = <64>; 173 i-cache-sets = <128>; 174 d-cache-size = <32768>; 175 d-cache-line-size = <64>; 176 d-cache-sets = <128>; 177 next-level-cache = <&l2_0>; 178 #cooling-cells = <2>; 179 mediatek,cci = <&cci>; 180 }; 181 182 cpu1: cpu@100 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a55"; 185 reg = <0x100>; 186 enable-method = "psci"; 187 clock-frequency = <2000000000>; 188 capacity-dmips-mhz = <382>; 189 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 190 i-cache-size = <32768>; 191 i-cache-line-size = <64>; 192 i-cache-sets = <128>; 193 d-cache-size = <32768>; 194 d-cache-line-size = <64>; 195 d-cache-sets = <128>; 196 next-level-cache = <&l2_0>; 197 #cooling-cells = <2>; 198 mediatek,cci = <&cci>; 199 }; 200 201 cpu2: cpu@200 { 202 device_type = "cpu"; 203 compatible = "arm,cortex-a55"; 204 reg = <0x200>; 205 enable-method = "psci"; 206 clock-frequency = <2000000000>; 207 capacity-dmips-mhz = <382>; 208 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 209 i-cache-size = <32768>; 210 i-cache-line-size = <64>; 211 i-cache-sets = <128>; 212 d-cache-size = <32768>; 213 d-cache-line-size = <64>; 214 d-cache-sets = <128>; 215 next-level-cache = <&l2_0>; 216 #cooling-cells = <2>; 217 mediatek,cci = <&cci>; 218 }; 219 220 cpu3: cpu@300 { 221 device_type = "cpu"; 222 compatible = "arm,cortex-a55"; 223 reg = <0x300>; 224 enable-method = "psci"; 225 clock-frequency = <2000000000>; 226 capacity-dmips-mhz = <382>; 227 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 228 i-cache-size = <32768>; 229 i-cache-line-size = <64>; 230 i-cache-sets = <128>; 231 d-cache-size = <32768>; 232 d-cache-line-size = <64>; 233 d-cache-sets = <128>; 234 next-level-cache = <&l2_0>; 235 #cooling-cells = <2>; 236 mediatek,cci = <&cci>; 237 }; 238 239 cpu4: cpu@400 { 240 device_type = "cpu"; 241 compatible = "arm,cortex-a55"; 242 reg = <0x400>; 243 enable-method = "psci"; 244 clock-frequency = <2000000000>; 245 capacity-dmips-mhz = <382>; 246 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 247 i-cache-size = <32768>; 248 i-cache-line-size = <64>; 249 i-cache-sets = <128>; 250 d-cache-size = <32768>; 251 d-cache-line-size = <64>; 252 d-cache-sets = <128>; 253 next-level-cache = <&l2_0>; 254 #cooling-cells = <2>; 255 mediatek,cci = <&cci>; 256 }; 257 258 cpu5: cpu@500 { 259 device_type = "cpu"; 260 compatible = "arm,cortex-a55"; 261 reg = <0x500>; 262 enable-method = "psci"; 263 clock-frequency = <2000000000>; 264 capacity-dmips-mhz = <382>; 265 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 266 i-cache-size = <32768>; 267 i-cache-line-size = <64>; 268 i-cache-sets = <128>; 269 d-cache-size = <32768>; 270 d-cache-line-size = <64>; 271 d-cache-sets = <128>; 272 next-level-cache = <&l2_0>; 273 #cooling-cells = <2>; 274 mediatek,cci = <&cci>; 275 }; 276 277 cpu6: cpu@600 { 278 device_type = "cpu"; 279 compatible = "arm,cortex-a76"; 280 reg = <0x600>; 281 enable-method = "psci"; 282 clock-frequency = <2050000000>; 283 capacity-dmips-mhz = <1024>; 284 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 285 i-cache-size = <65536>; 286 i-cache-line-size = <64>; 287 i-cache-sets = <256>; 288 d-cache-size = <65536>; 289 d-cache-line-size = <64>; 290 d-cache-sets = <256>; 291 next-level-cache = <&l2_1>; 292 #cooling-cells = <2>; 293 mediatek,cci = <&cci>; 294 }; 295 296 cpu7: cpu@700 { 297 device_type = "cpu"; 298 compatible = "arm,cortex-a76"; 299 reg = <0x700>; 300 enable-method = "psci"; 301 clock-frequency = <2050000000>; 302 capacity-dmips-mhz = <1024>; 303 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 304 i-cache-size = <65536>; 305 i-cache-line-size = <64>; 306 i-cache-sets = <256>; 307 d-cache-size = <65536>; 308 d-cache-line-size = <64>; 309 d-cache-sets = <256>; 310 next-level-cache = <&l2_1>; 311 #cooling-cells = <2>; 312 mediatek,cci = <&cci>; 313 }; 314 315 idle-states { 316 entry-method = "psci"; 317 318 cpu_ret_l: cpu-retention-l { 319 compatible = "arm,idle-state"; 320 arm,psci-suspend-param = <0x00010001>; 321 local-timer-stop; 322 entry-latency-us = <50>; 323 exit-latency-us = <100>; 324 min-residency-us = <1600>; 325 }; 326 327 cpu_ret_b: cpu-retention-b { 328 compatible = "arm,idle-state"; 329 arm,psci-suspend-param = <0x00010001>; 330 local-timer-stop; 331 entry-latency-us = <50>; 332 exit-latency-us = <100>; 333 min-residency-us = <1400>; 334 }; 335 336 cpu_off_l: cpu-off-l { 337 compatible = "arm,idle-state"; 338 arm,psci-suspend-param = <0x01010001>; 339 local-timer-stop; 340 entry-latency-us = <100>; 341 exit-latency-us = <250>; 342 min-residency-us = <2100>; 343 }; 344 345 cpu_off_b: cpu-off-b { 346 compatible = "arm,idle-state"; 347 arm,psci-suspend-param = <0x01010001>; 348 local-timer-stop; 349 entry-latency-us = <100>; 350 exit-latency-us = <250>; 351 min-residency-us = <1900>; 352 }; 353 }; 354 355 l2_0: l2-cache0 { 356 compatible = "cache"; 357 cache-level = <2>; 358 cache-size = <131072>; 359 cache-line-size = <64>; 360 cache-sets = <512>; 361 next-level-cache = <&l3_0>; 362 cache-unified; 363 }; 364 365 l2_1: l2-cache1 { 366 compatible = "cache"; 367 cache-level = <2>; 368 cache-size = <262144>; 369 cache-line-size = <64>; 370 cache-sets = <512>; 371 next-level-cache = <&l3_0>; 372 cache-unified; 373 }; 374 375 l3_0: l3-cache { 376 compatible = "cache"; 377 cache-level = <3>; 378 cache-size = <1048576>; 379 cache-line-size = <64>; 380 cache-sets = <1024>; 381 cache-unified; 382 }; 383 }; 384 385 clk13m: fixed-factor-clock-13m { 386 compatible = "fixed-factor-clock"; 387 #clock-cells = <0>; 388 clocks = <&clk26m>; 389 clock-div = <2>; 390 clock-mult = <1>; 391 clock-output-names = "clk13m"; 392 }; 393 394 clk26m: oscillator-26m { 395 compatible = "fixed-clock"; 396 #clock-cells = <0>; 397 clock-frequency = <26000000>; 398 clock-output-names = "clk26m"; 399 }; 400 401 clk32k: oscillator-32k { 402 compatible = "fixed-clock"; 403 #clock-cells = <0>; 404 clock-frequency = <32768>; 405 clock-output-names = "clk32k"; 406 }; 407 408 pmu-a55 { 409 compatible = "arm,cortex-a55-pmu"; 410 interrupt-parent = <&gic>; 411 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 412 }; 413 414 pmu-a76 { 415 compatible = "arm,cortex-a76-pmu"; 416 interrupt-parent = <&gic>; 417 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 418 }; 419 420 psci { 421 compatible = "arm,psci-1.0"; 422 method = "smc"; 423 }; 424 425 timer { 426 compatible = "arm,armv8-timer"; 427 interrupt-parent = <&gic>; 428 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 429 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 430 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 431 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 432 }; 433 434 soc { 435 #address-cells = <2>; 436 #size-cells = <2>; 437 compatible = "simple-bus"; 438 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 439 ranges; 440 441 gic: interrupt-controller@c000000 { 442 compatible = "arm,gic-v3"; 443 #interrupt-cells = <4>; 444 #redistributor-regions = <1>; 445 interrupt-parent = <&gic>; 446 interrupt-controller; 447 reg = <0 0x0c000000 0 0x40000>, 448 <0 0x0c040000 0 0x200000>; 449 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 450 451 ppi-partitions { 452 ppi_cluster0: interrupt-partition-0 { 453 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 454 }; 455 456 ppi_cluster1: interrupt-partition-1 { 457 affinity = <&cpu6 &cpu7>; 458 }; 459 }; 460 }; 461 462 mcusys: syscon@c53a000 { 463 compatible = "mediatek,mt8186-mcusys", "syscon"; 464 reg = <0 0xc53a000 0 0x1000>; 465 #clock-cells = <1>; 466 }; 467 468 topckgen: syscon@10000000 { 469 compatible = "mediatek,mt8186-topckgen", "syscon"; 470 reg = <0 0x10000000 0 0x1000>; 471 #clock-cells = <1>; 472 }; 473 474 infracfg_ao: syscon@10001000 { 475 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 476 reg = <0 0x10001000 0 0x1000>; 477 #clock-cells = <1>; 478 #reset-cells = <1>; 479 }; 480 481 pericfg: syscon@10003000 { 482 compatible = "mediatek,mt8186-pericfg", "syscon"; 483 reg = <0 0x10003000 0 0x1000>; 484 }; 485 486 pio: pinctrl@10005000 { 487 compatible = "mediatek,mt8186-pinctrl"; 488 reg = <0 0x10005000 0 0x1000>, 489 <0 0x10002000 0 0x0200>, 490 <0 0x10002200 0 0x0200>, 491 <0 0x10002400 0 0x0200>, 492 <0 0x10002600 0 0x0200>, 493 <0 0x10002a00 0 0x0200>, 494 <0 0x10002c00 0 0x0200>, 495 <0 0x1000b000 0 0x1000>; 496 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 497 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 498 gpio-controller; 499 #gpio-cells = <2>; 500 gpio-ranges = <&pio 0 0 185>; 501 interrupt-controller; 502 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 503 #interrupt-cells = <2>; 504 }; 505 506 scpsys: syscon@10006000 { 507 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 508 reg = <0 0x10006000 0 0x1000>; 509 510 /* System Power Manager */ 511 spm: power-controller { 512 compatible = "mediatek,mt8186-power-controller"; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 #power-domain-cells = <1>; 516 517 /* power domain of the SoC */ 518 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 519 reg = <MT8186_POWER_DOMAIN_MFG0>; 520 clocks = <&topckgen CLK_TOP_MFG>; 521 clock-names = "mfg00"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 #power-domain-cells = <1>; 525 526 power-domain@MT8186_POWER_DOMAIN_MFG1 { 527 reg = <MT8186_POWER_DOMAIN_MFG1>; 528 mediatek,infracfg = <&infracfg_ao>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 #power-domain-cells = <1>; 532 533 power-domain@MT8186_POWER_DOMAIN_MFG2 { 534 reg = <MT8186_POWER_DOMAIN_MFG2>; 535 #power-domain-cells = <0>; 536 }; 537 538 power-domain@MT8186_POWER_DOMAIN_MFG3 { 539 reg = <MT8186_POWER_DOMAIN_MFG3>; 540 #power-domain-cells = <0>; 541 }; 542 }; 543 }; 544 545 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 546 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 547 clocks = <&topckgen CLK_TOP_SENINF>, 548 <&topckgen CLK_TOP_SENINF1>; 549 clock-names = "csirx_top0", "csirx_top1"; 550 #power-domain-cells = <0>; 551 }; 552 553 power-domain@MT8186_POWER_DOMAIN_SSUSB { 554 reg = <MT8186_POWER_DOMAIN_SSUSB>; 555 #power-domain-cells = <0>; 556 }; 557 558 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 559 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 560 #power-domain-cells = <0>; 561 }; 562 563 power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 564 reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 565 clocks = <&topckgen CLK_TOP_AUDIODSP>, 566 <&topckgen CLK_TOP_ADSP_BUS>; 567 clock-names = "audioadsp", "adsp_bus"; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 #power-domain-cells = <1>; 571 572 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 573 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 #power-domain-cells = <1>; 577 578 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 579 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 580 mediatek,infracfg = <&infracfg_ao>; 581 #power-domain-cells = <0>; 582 }; 583 }; 584 }; 585 586 power-domain@MT8186_POWER_DOMAIN_CONN_ON { 587 reg = <MT8186_POWER_DOMAIN_CONN_ON>; 588 mediatek,infracfg = <&infracfg_ao>; 589 #power-domain-cells = <0>; 590 }; 591 592 power-domain@MT8186_POWER_DOMAIN_DIS { 593 reg = <MT8186_POWER_DOMAIN_DIS>; 594 clocks = <&topckgen CLK_TOP_DISP>, 595 <&topckgen CLK_TOP_MDP>, 596 <&mmsys CLK_MM_SMI_INFRA>, 597 <&mmsys CLK_MM_SMI_COMMON>, 598 <&mmsys CLK_MM_SMI_GALS>, 599 <&mmsys CLK_MM_SMI_IOMMU>; 600 clock-names = "disp", "mdp", "smi_infra", "smi_common", 601 "smi_gals", "smi_iommu"; 602 mediatek,infracfg = <&infracfg_ao>; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 #power-domain-cells = <1>; 606 607 power-domain@MT8186_POWER_DOMAIN_VDEC { 608 reg = <MT8186_POWER_DOMAIN_VDEC>; 609 clocks = <&topckgen CLK_TOP_VDEC>, 610 <&vdecsys CLK_VDEC_LARB1_CKEN>; 611 clock-names = "vdec0", "larb"; 612 mediatek,infracfg = <&infracfg_ao>; 613 #power-domain-cells = <0>; 614 }; 615 616 power-domain@MT8186_POWER_DOMAIN_CAM { 617 reg = <MT8186_POWER_DOMAIN_CAM>; 618 clocks = <&topckgen CLK_TOP_CAM>, 619 <&topckgen CLK_TOP_SENINF>, 620 <&topckgen CLK_TOP_SENINF1>, 621 <&topckgen CLK_TOP_SENINF2>, 622 <&topckgen CLK_TOP_SENINF3>, 623 <&topckgen CLK_TOP_CAMTM>, 624 <&camsys CLK_CAM2MM_GALS>; 625 clock-names = "cam-top", "cam0", "cam1", "cam2", 626 "cam3", "cam-tm", "gals"; 627 mediatek,infracfg = <&infracfg_ao>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 #power-domain-cells = <1>; 631 632 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 633 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 634 #power-domain-cells = <0>; 635 }; 636 637 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 638 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 639 #power-domain-cells = <0>; 640 }; 641 }; 642 643 power-domain@MT8186_POWER_DOMAIN_IMG { 644 reg = <MT8186_POWER_DOMAIN_IMG>; 645 clocks = <&topckgen CLK_TOP_IMG1>, 646 <&imgsys1 CLK_IMG1_GALS_IMG1>; 647 clock-names = "img-top", "gals"; 648 mediatek,infracfg = <&infracfg_ao>; 649 #address-cells = <1>; 650 #size-cells = <0>; 651 #power-domain-cells = <1>; 652 653 power-domain@MT8186_POWER_DOMAIN_IMG2 { 654 reg = <MT8186_POWER_DOMAIN_IMG2>; 655 #power-domain-cells = <0>; 656 }; 657 }; 658 659 power-domain@MT8186_POWER_DOMAIN_IPE { 660 reg = <MT8186_POWER_DOMAIN_IPE>; 661 clocks = <&topckgen CLK_TOP_IPE>, 662 <&ipesys CLK_IPE_LARB19>, 663 <&ipesys CLK_IPE_LARB20>, 664 <&ipesys CLK_IPE_SMI_SUBCOM>, 665 <&ipesys CLK_IPE_GALS_IPE>; 666 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", 667 "ipe-smi", "ipe-gals"; 668 mediatek,infracfg = <&infracfg_ao>; 669 #power-domain-cells = <0>; 670 }; 671 672 power-domain@MT8186_POWER_DOMAIN_VENC { 673 reg = <MT8186_POWER_DOMAIN_VENC>; 674 clocks = <&topckgen CLK_TOP_VENC>, 675 <&vencsys CLK_VENC_CKE1_VENC>; 676 clock-names = "venc0", "larb"; 677 mediatek,infracfg = <&infracfg_ao>; 678 #power-domain-cells = <0>; 679 }; 680 681 power-domain@MT8186_POWER_DOMAIN_WPE { 682 reg = <MT8186_POWER_DOMAIN_WPE>; 683 clocks = <&topckgen CLK_TOP_WPE>, 684 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 685 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 686 clock-names = "wpe0", "larb-ck", "larb-pclk"; 687 mediatek,infracfg = <&infracfg_ao>; 688 #power-domain-cells = <0>; 689 }; 690 }; 691 }; 692 }; 693 694 watchdog: watchdog@10007000 { 695 compatible = "mediatek,mt8186-wdt"; 696 mediatek,disable-extrst; 697 reg = <0 0x10007000 0 0x1000>; 698 #reset-cells = <1>; 699 }; 700 701 apmixedsys: syscon@1000c000 { 702 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 703 reg = <0 0x1000c000 0 0x1000>; 704 #clock-cells = <1>; 705 }; 706 707 pwrap: pwrap@1000d000 { 708 compatible = "mediatek,mt8186-pwrap", "syscon"; 709 reg = <0 0x1000d000 0 0x1000>; 710 reg-names = "pwrap"; 711 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 712 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 713 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 714 clock-names = "spi", "wrap"; 715 }; 716 717 spmi: spmi@10015000 { 718 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; 719 reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; 720 reg-names = "pmif", "spmimst"; 721 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 722 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 723 <&topckgen CLK_TOP_SPMI_MST>; 724 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 725 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; 726 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 727 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>, 728 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>; 729 status = "disabled"; 730 }; 731 732 systimer: timer@10017000 { 733 compatible = "mediatek,mt8186-timer", 734 "mediatek,mt6765-timer"; 735 reg = <0 0x10017000 0 0x1000>; 736 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 737 clocks = <&clk13m>; 738 }; 739 740 gce: mailbox@1022c000 { 741 compatible = "mediatek,mt8186-gce"; 742 reg = <0 0X1022c000 0 0x4000>; 743 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 744 clock-names = "gce"; 745 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 746 #mbox-cells = <2>; 747 }; 748 749 scp: scp@10500000 { 750 compatible = "mediatek,mt8186-scp"; 751 reg = <0 0x10500000 0 0x40000>, 752 <0 0x105c0000 0 0x19080>; 753 reg-names = "sram", "cfg"; 754 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 755 }; 756 757 adsp: adsp@10680000 { 758 compatible = "mediatek,mt8186-dsp"; 759 reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, 760 <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; 761 reg-names = "cfg", "sram", "sec", "bus"; 762 clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; 763 clock-names = "audiodsp", "adsp_bus"; 764 assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, 765 <&topckgen CLK_TOP_ADSP_BUS>; 766 assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; 767 mbox-names = "rx", "tx"; 768 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 769 power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; 770 status = "disabled"; 771 }; 772 773 adsp_mailbox0: mailbox@10686000 { 774 compatible = "mediatek,mt8186-adsp-mbox"; 775 #mbox-cells = <0>; 776 reg = <0 0x10686100 0 0x1000>; 777 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 778 }; 779 780 adsp_mailbox1: mailbox@10687000 { 781 compatible = "mediatek,mt8186-adsp-mbox"; 782 #mbox-cells = <0>; 783 reg = <0 0x10687100 0 0x1000>; 784 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>; 785 }; 786 787 nor_flash: spi@11000000 { 788 compatible = "mediatek,mt8186-nor"; 789 reg = <0 0x11000000 0 0x1000>; 790 clocks = <&topckgen CLK_TOP_SPINOR>, 791 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 792 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 793 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 794 clock-names = "spi", "sf", "axi", "axi_s"; 795 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 796 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 797 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 798 status = "disabled"; 799 }; 800 801 auxadc: adc@11001000 { 802 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 803 reg = <0 0x11001000 0 0x1000>; 804 #io-channel-cells = <1>; 805 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 806 clock-names = "main"; 807 }; 808 809 uart0: serial@11002000 { 810 compatible = "mediatek,mt8186-uart", 811 "mediatek,mt6577-uart"; 812 reg = <0 0x11002000 0 0x1000>; 813 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 814 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 815 clock-names = "baud", "bus"; 816 status = "disabled"; 817 }; 818 819 uart1: serial@11003000 { 820 compatible = "mediatek,mt8186-uart", 821 "mediatek,mt6577-uart"; 822 reg = <0 0x11003000 0 0x1000>; 823 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 824 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 825 clock-names = "baud", "bus"; 826 status = "disabled"; 827 }; 828 829 i2c0: i2c@11007000 { 830 compatible = "mediatek,mt8186-i2c"; 831 reg = <0 0x11007000 0 0x1000>, 832 <0 0x10200100 0 0x100>; 833 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 834 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 835 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 836 clock-names = "main", "dma"; 837 clock-div = <1>; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 status = "disabled"; 841 }; 842 843 i2c1: i2c@11008000 { 844 compatible = "mediatek,mt8186-i2c"; 845 reg = <0 0x11008000 0 0x1000>, 846 <0 0x10200200 0 0x100>; 847 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 848 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 849 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 850 clock-names = "main", "dma"; 851 clock-div = <1>; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 status = "disabled"; 855 }; 856 857 i2c2: i2c@11009000 { 858 compatible = "mediatek,mt8186-i2c"; 859 reg = <0 0x11009000 0 0x1000>, 860 <0 0x10200300 0 0x180>; 861 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 862 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 863 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 864 clock-names = "main", "dma"; 865 clock-div = <1>; 866 #address-cells = <1>; 867 #size-cells = <0>; 868 status = "disabled"; 869 }; 870 871 i2c3: i2c@1100f000 { 872 compatible = "mediatek,mt8186-i2c"; 873 reg = <0 0x1100f000 0 0x1000>, 874 <0 0x10200480 0 0x100>; 875 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 876 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 877 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 878 clock-names = "main", "dma"; 879 clock-div = <1>; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 status = "disabled"; 883 }; 884 885 i2c4: i2c@11011000 { 886 compatible = "mediatek,mt8186-i2c"; 887 reg = <0 0x11011000 0 0x1000>, 888 <0 0x10200580 0 0x180>; 889 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 890 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 891 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 892 clock-names = "main", "dma"; 893 clock-div = <1>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 status = "disabled"; 897 }; 898 899 i2c5: i2c@11016000 { 900 compatible = "mediatek,mt8186-i2c"; 901 reg = <0 0x11016000 0 0x1000>, 902 <0 0x10200700 0 0x100>; 903 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 904 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 905 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 906 clock-names = "main", "dma"; 907 clock-div = <1>; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 status = "disabled"; 911 }; 912 913 i2c6: i2c@1100d000 { 914 compatible = "mediatek,mt8186-i2c"; 915 reg = <0 0x1100d000 0 0x1000>, 916 <0 0x10200800 0 0x100>; 917 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 918 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 919 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 920 clock-names = "main", "dma"; 921 clock-div = <1>; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 status = "disabled"; 925 }; 926 927 i2c7: i2c@11004000 { 928 compatible = "mediatek,mt8186-i2c"; 929 reg = <0 0x11004000 0 0x1000>, 930 <0 0x10200900 0 0x180>; 931 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 932 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 933 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 934 clock-names = "main", "dma"; 935 clock-div = <1>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 status = "disabled"; 939 }; 940 941 i2c8: i2c@11005000 { 942 compatible = "mediatek,mt8186-i2c"; 943 reg = <0 0x11005000 0 0x1000>, 944 <0 0x10200A80 0 0x180>; 945 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 946 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 947 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 948 clock-names = "main", "dma"; 949 clock-div = <1>; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 status = "disabled"; 953 }; 954 955 spi0: spi@1100a000 { 956 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 reg = <0 0x1100a000 0 0x1000>; 960 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 961 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 962 <&topckgen CLK_TOP_SPI>, 963 <&infracfg_ao CLK_INFRA_AO_SPI0>; 964 clock-names = "parent-clk", "sel-clk", "spi-clk"; 965 status = "disabled"; 966 }; 967 968 pwm0: pwm@1100e000 { 969 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 970 reg = <0 0x1100e000 0 0x1000>; 971 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 972 #pwm-cells = <2>; 973 clocks = <&topckgen CLK_TOP_DISP_PWM>, 974 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 975 clock-names = "main", "mm"; 976 status = "disabled"; 977 }; 978 979 spi1: spi@11010000 { 980 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 reg = <0 0x11010000 0 0x1000>; 984 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 985 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 986 <&topckgen CLK_TOP_SPI>, 987 <&infracfg_ao CLK_INFRA_AO_SPI1>; 988 clock-names = "parent-clk", "sel-clk", "spi-clk"; 989 status = "disabled"; 990 }; 991 992 spi2: spi@11012000 { 993 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 994 #address-cells = <1>; 995 #size-cells = <0>; 996 reg = <0 0x11012000 0 0x1000>; 997 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 998 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 999 <&topckgen CLK_TOP_SPI>, 1000 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1001 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1002 status = "disabled"; 1003 }; 1004 1005 spi3: spi@11013000 { 1006 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 reg = <0 0x11013000 0 0x1000>; 1010 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 1011 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1012 <&topckgen CLK_TOP_SPI>, 1013 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1014 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1015 status = "disabled"; 1016 }; 1017 1018 spi4: spi@11014000 { 1019 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 reg = <0 0x11014000 0 0x1000>; 1023 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1024 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1025 <&topckgen CLK_TOP_SPI>, 1026 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1027 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1028 status = "disabled"; 1029 }; 1030 1031 spi5: spi@11015000 { 1032 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 reg = <0 0x11015000 0 0x1000>; 1036 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1037 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 1038 <&topckgen CLK_TOP_SPI>, 1039 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1040 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1041 status = "disabled"; 1042 }; 1043 1044 imp_iic_wrap: clock-controller@11017000 { 1045 compatible = "mediatek,mt8186-imp_iic_wrap"; 1046 reg = <0 0x11017000 0 0x1000>; 1047 #clock-cells = <1>; 1048 }; 1049 1050 uart2: serial@11018000 { 1051 compatible = "mediatek,mt8186-uart", 1052 "mediatek,mt6577-uart"; 1053 reg = <0 0x11018000 0 0x1000>; 1054 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 1055 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1056 clock-names = "baud", "bus"; 1057 status = "disabled"; 1058 }; 1059 1060 i2c9: i2c@11019000 { 1061 compatible = "mediatek,mt8186-i2c"; 1062 reg = <0 0x11019000 0 0x1000>, 1063 <0 0x10200c00 0 0x180>; 1064 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 1065 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 1066 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 1067 clock-names = "main", "dma"; 1068 clock-div = <1>; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 status = "disabled"; 1072 }; 1073 1074 afe: audio-controller@11210000 { 1075 compatible = "mediatek,mt8186-sound"; 1076 reg = <0 0x11210000 0 0x2000>; 1077 clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, 1078 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, 1079 <&topckgen CLK_TOP_AUDIO>, 1080 <&topckgen CLK_TOP_AUD_INTBUS>, 1081 <&topckgen CLK_TOP_MAINPLL_D2_D4>, 1082 <&topckgen CLK_TOP_AUD_1>, 1083 <&apmixedsys CLK_APMIXED_APLL1>, 1084 <&topckgen CLK_TOP_AUD_2>, 1085 <&apmixedsys CLK_APMIXED_APLL2>, 1086 <&topckgen CLK_TOP_AUD_ENGEN1>, 1087 <&topckgen CLK_TOP_APLL1_D8>, 1088 <&topckgen CLK_TOP_AUD_ENGEN2>, 1089 <&topckgen CLK_TOP_APLL2_D8>, 1090 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, 1091 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, 1092 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, 1093 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, 1094 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, 1095 <&topckgen CLK_TOP_APLL12_CK_DIV0>, 1096 <&topckgen CLK_TOP_APLL12_CK_DIV1>, 1097 <&topckgen CLK_TOP_APLL12_CK_DIV2>, 1098 <&topckgen CLK_TOP_APLL12_CK_DIV4>, 1099 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, 1100 <&topckgen CLK_TOP_AUDIO_H>, 1101 <&clk26m>; 1102 clock-names = "aud_infra_clk", 1103 "mtkaif_26m_clk", 1104 "top_mux_audio", 1105 "top_mux_audio_int", 1106 "top_mainpll_d2_d4", 1107 "top_mux_aud_1", 1108 "top_apll1_ck", 1109 "top_mux_aud_2", 1110 "top_apll2_ck", 1111 "top_mux_aud_eng1", 1112 "top_apll1_d8", 1113 "top_mux_aud_eng2", 1114 "top_apll2_d8", 1115 "top_i2s0_m_sel", 1116 "top_i2s1_m_sel", 1117 "top_i2s2_m_sel", 1118 "top_i2s4_m_sel", 1119 "top_tdm_m_sel", 1120 "top_apll12_div0", 1121 "top_apll12_div1", 1122 "top_apll12_div2", 1123 "top_apll12_div4", 1124 "top_apll12_div_tdm", 1125 "top_mux_audio_h", 1126 "top_clk26m_clk"; 1127 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1128 mediatek,apmixedsys = <&apmixedsys>; 1129 mediatek,infracfg = <&infracfg_ao>; 1130 mediatek,topckgen = <&topckgen>; 1131 resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; 1132 reset-names = "audiosys"; 1133 status = "disabled"; 1134 }; 1135 1136 ssusb0: usb@11201000 { 1137 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1138 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1139 reg-names = "mac", "ippc"; 1140 clocks = <&topckgen CLK_TOP_USB_TOP>, 1141 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1142 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1143 <&infracfg_ao CLK_INFRA_AO_ICUSB>; 1144 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1145 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>; 1146 phys = <&u2port0 PHY_TYPE_USB2>; 1147 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; 1148 #address-cells = <2>; 1149 #size-cells = <2>; 1150 ranges; 1151 status = "disabled"; 1152 1153 usb_host0: usb@11200000 { 1154 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1155 reg = <0 0x11200000 0 0x1000>; 1156 reg-names = "mac"; 1157 clocks = <&topckgen CLK_TOP_USB_TOP>, 1158 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1159 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1160 <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1161 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1162 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1163 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 1164 mediatek,syscon-wakeup = <&pericfg 0x420 2>; 1165 wakeup-source; 1166 status = "disabled"; 1167 }; 1168 }; 1169 1170 mmc0: mmc@11230000 { 1171 compatible = "mediatek,mt8186-mmc", 1172 "mediatek,mt8183-mmc"; 1173 reg = <0 0x11230000 0 0x10000>, 1174 <0 0x11cd0000 0 0x1000>; 1175 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1176 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1177 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1178 <&infracfg_ao CLK_INFRA_AO_MSDCFDE>; 1179 clock-names = "source", "hclk", "source_cg", "crypto"; 1180 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 1181 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 1182 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 1183 status = "disabled"; 1184 }; 1185 1186 mmc1: mmc@11240000 { 1187 compatible = "mediatek,mt8186-mmc", 1188 "mediatek,mt8183-mmc"; 1189 reg = <0 0x11240000 0 0x1000>, 1190 <0 0x11c90000 0 0x1000>; 1191 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1192 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1193 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1194 clock-names = "source", "hclk", "source_cg"; 1195 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 1196 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1197 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1198 status = "disabled"; 1199 }; 1200 1201 ssusb1: usb@11281000 { 1202 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1203 reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; 1204 reg-names = "mac", "ippc"; 1205 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1206 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1207 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1208 <&clk26m>; 1209 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1210 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 1211 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1212 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; 1213 #address-cells = <2>; 1214 #size-cells = <2>; 1215 ranges; 1216 status = "disabled"; 1217 1218 usb_host1: usb@11280000 { 1219 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1220 reg = <0 0x11280000 0 0x1000>; 1221 reg-names = "mac"; 1222 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1223 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1224 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1225 <&clk26m>, 1226 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1227 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; 1228 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1229 mediatek,syscon-wakeup = <&pericfg 0x424 2>; 1230 wakeup-source; 1231 status = "disabled"; 1232 }; 1233 }; 1234 1235 u3phy0: t-phy@11c80000 { 1236 compatible = "mediatek,mt8186-tphy", 1237 "mediatek,generic-tphy-v2"; 1238 #address-cells = <1>; 1239 #size-cells = <1>; 1240 ranges = <0x0 0x0 0x11c80000 0x1000>; 1241 status = "disabled"; 1242 1243 u2port1: usb-phy@0 { 1244 reg = <0x0 0x700>; 1245 clocks = <&clk26m>; 1246 clock-names = "ref"; 1247 #phy-cells = <1>; 1248 }; 1249 1250 u3port1: usb-phy@700 { 1251 reg = <0x700 0x900>; 1252 clocks = <&clk26m>; 1253 clock-names = "ref"; 1254 #phy-cells = <1>; 1255 }; 1256 }; 1257 1258 u3phy1: t-phy@11ca0000 { 1259 compatible = "mediatek,mt8186-tphy", 1260 "mediatek,generic-tphy-v2"; 1261 #address-cells = <1>; 1262 #size-cells = <1>; 1263 ranges = <0x0 0x0 0x11ca0000 0x1000>; 1264 status = "disabled"; 1265 1266 u2port0: usb-phy@0 { 1267 reg = <0x0 0x700>; 1268 clocks = <&clk26m>; 1269 clock-names = "ref"; 1270 #phy-cells = <1>; 1271 mediatek,discth = <0x8>; 1272 }; 1273 }; 1274 1275 efuse: efuse@11cb0000 { 1276 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 1277 reg = <0 0x11cb0000 0 0x1000>; 1278 #address-cells = <1>; 1279 #size-cells = <1>; 1280 }; 1281 1282 mipi_tx0: dsi-phy@11cc0000 { 1283 compatible = "mediatek,mt8183-mipi-tx"; 1284 reg = <0 0x11cc0000 0 0x1000>; 1285 clocks = <&clk26m>; 1286 #clock-cells = <0>; 1287 #phy-cells = <0>; 1288 clock-output-names = "mipi_tx0_pll"; 1289 status = "disabled"; 1290 }; 1291 1292 mfgsys: clock-controller@13000000 { 1293 compatible = "mediatek,mt8186-mfgsys"; 1294 reg = <0 0x13000000 0 0x1000>; 1295 #clock-cells = <1>; 1296 }; 1297 1298 gpu: gpu@13040000 { 1299 compatible = "mediatek,mt8186-mali", 1300 "arm,mali-bifrost"; 1301 reg = <0 0x13040000 0 0x4000>; 1302 1303 clocks = <&mfgsys CLK_MFG_BG3D>; 1304 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>, 1305 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>, 1306 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 1307 interrupt-names = "job", "mmu", "gpu"; 1308 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>, 1309 <&spm MT8186_POWER_DOMAIN_MFG3>; 1310 power-domain-names = "core0", "core1"; 1311 #cooling-cells = <2>; 1312 status = "disabled"; 1313 }; 1314 1315 mmsys: syscon@14000000 { 1316 compatible = "mediatek,mt8186-mmsys", "syscon"; 1317 reg = <0 0x14000000 0 0x1000>; 1318 #clock-cells = <1>; 1319 #reset-cells = <1>; 1320 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1321 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1322 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1323 }; 1324 1325 mutex: mutex@14001000 { 1326 compatible = "mediatek,mt8186-disp-mutex"; 1327 reg = <0 0x14001000 0 0x1000>; 1328 clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1329 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>; 1330 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1331 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1332 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1333 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1334 }; 1335 1336 smi_common: smi@14002000 { 1337 compatible = "mediatek,mt8186-smi-common"; 1338 reg = <0 0x14002000 0 0x1000>; 1339 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 1340 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 1341 clock-names = "apb", "smi", "gals0", "gals1"; 1342 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1343 }; 1344 1345 larb0: smi@14003000 { 1346 compatible = "mediatek,mt8186-smi-larb"; 1347 reg = <0 0x14003000 0 0x1000>; 1348 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1349 <&mmsys CLK_MM_SMI_COMMON>; 1350 clock-names = "apb", "smi"; 1351 mediatek,larb-id = <0>; 1352 mediatek,smi = <&smi_common>; 1353 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1354 }; 1355 1356 larb1: smi@14004000 { 1357 compatible = "mediatek,mt8186-smi-larb"; 1358 reg = <0 0x14004000 0 0x1000>; 1359 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1360 <&mmsys CLK_MM_SMI_COMMON>; 1361 clock-names = "apb", "smi"; 1362 mediatek,larb-id = <1>; 1363 mediatek,smi = <&smi_common>; 1364 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1365 }; 1366 1367 ovl0: ovl@14005000 { 1368 compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl"; 1369 reg = <0 0x14005000 0 0x1000>; 1370 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1371 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; 1372 iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; 1373 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1374 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1375 }; 1376 1377 ovl_2l0: ovl@14006000 { 1378 compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l"; 1379 reg = <0 0x14006000 0 0x1000>; 1380 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1381 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 1382 iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; 1383 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1384 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1385 }; 1386 1387 rdma0: rdma@14007000 { 1388 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1389 reg = <0 0x14007000 0 0x1000>; 1390 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1391 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>; 1392 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; 1393 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1394 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1395 }; 1396 1397 color: color@14009000 { 1398 compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color"; 1399 reg = <0 0x14009000 0 0x1000>; 1400 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1401 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>; 1402 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1403 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1404 }; 1405 1406 dpi: dpi@1400a000 { 1407 compatible = "mediatek,mt8186-dpi"; 1408 reg = <0 0x1400a000 0 0x1000>; 1409 clocks = <&topckgen CLK_TOP_DPI>, 1410 <&mmsys CLK_MM_DISP_DPI>, 1411 <&apmixedsys CLK_APMIXED_TVDPLL>; 1412 clock-names = "pixel", "engine", "pll"; 1413 assigned-clocks = <&topckgen CLK_TOP_DPI>; 1414 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; 1415 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; 1416 status = "disabled"; 1417 1418 port { 1419 dpi_out: endpoint { }; 1420 }; 1421 }; 1422 1423 ccorr: ccorr@1400b000 { 1424 compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 1425 reg = <0 0x1400b000 0 0x1000>; 1426 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1427 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>; 1428 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1429 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1430 }; 1431 1432 aal: aal@1400c000 { 1433 compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal"; 1434 reg = <0 0x1400c000 0 0x1000>; 1435 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1436 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>; 1437 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1438 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1439 }; 1440 1441 gamma: gamma@1400d000 { 1442 compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma"; 1443 reg = <0 0x1400d000 0 0x1000>; 1444 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1445 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 1446 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1447 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1448 }; 1449 1450 postmask: postmask@1400e000 { 1451 compatible = "mediatek,mt8186-disp-postmask", 1452 "mediatek,mt8192-disp-postmask"; 1453 reg = <0 0x1400e000 0 0x1000>; 1454 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1455 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 1456 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1457 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1458 }; 1459 1460 dither: dither@1400f000 { 1461 compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither"; 1462 reg = <0 0x1400f000 0 0x1000>; 1463 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1464 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>; 1465 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1466 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1467 }; 1468 1469 dsi0: dsi@14013000 { 1470 compatible = "mediatek,mt8186-dsi"; 1471 reg = <0 0x14013000 0 0x1000>; 1472 clocks = <&mmsys CLK_MM_DSI0>, 1473 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 1474 <&mipi_tx0>; 1475 clock-names = "engine", "digital", "hs"; 1476 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 1477 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1478 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 1479 phys = <&mipi_tx0>; 1480 phy-names = "dphy"; 1481 status = "disabled"; 1482 1483 port { 1484 dsi_out: endpoint { }; 1485 }; 1486 }; 1487 1488 iommu_mm: iommu@14016000 { 1489 compatible = "mediatek,mt8186-iommu-mm"; 1490 reg = <0 0x14016000 0 0x1000>; 1491 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1492 clock-names = "bclk"; 1493 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1494 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1495 &larb7 &larb8 &larb9 &larb11 1496 &larb13 &larb14 &larb16 &larb17 1497 &larb19 &larb20>; 1498 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1499 #iommu-cells = <1>; 1500 }; 1501 1502 rdma1: rdma@1401f000 { 1503 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1504 reg = <0 0x1401f000 0 0x1000>; 1505 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1506 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>; 1507 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; 1508 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>; 1509 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1510 }; 1511 1512 wpesys: clock-controller@14020000 { 1513 compatible = "mediatek,mt8186-wpesys"; 1514 reg = <0 0x14020000 0 0x1000>; 1515 #clock-cells = <1>; 1516 }; 1517 1518 larb8: smi@14023000 { 1519 compatible = "mediatek,mt8186-smi-larb"; 1520 reg = <0 0x14023000 0 0x1000>; 1521 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1522 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1523 clock-names = "apb", "smi"; 1524 mediatek,larb-id = <8>; 1525 mediatek,smi = <&smi_common>; 1526 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1527 }; 1528 1529 imgsys1: clock-controller@15020000 { 1530 compatible = "mediatek,mt8186-imgsys1"; 1531 reg = <0 0x15020000 0 0x1000>; 1532 #clock-cells = <1>; 1533 }; 1534 1535 larb9: smi@1502e000 { 1536 compatible = "mediatek,mt8186-smi-larb"; 1537 reg = <0 0x1502e000 0 0x1000>; 1538 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1539 <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1540 clock-names = "apb", "smi"; 1541 mediatek,larb-id = <9>; 1542 mediatek,smi = <&smi_common>; 1543 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 1544 }; 1545 1546 imgsys2: clock-controller@15820000 { 1547 compatible = "mediatek,mt8186-imgsys2"; 1548 reg = <0 0x15820000 0 0x1000>; 1549 #clock-cells = <1>; 1550 }; 1551 1552 larb11: smi@1582e000 { 1553 compatible = "mediatek,mt8186-smi-larb"; 1554 reg = <0 0x1582e000 0 0x1000>; 1555 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 1556 <&imgsys2 CLK_IMG2_LARB9_IMG2>; 1557 clock-names = "apb", "smi"; 1558 mediatek,larb-id = <11>; 1559 mediatek,smi = <&smi_common>; 1560 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 1561 }; 1562 1563 larb4: smi@1602e000 { 1564 compatible = "mediatek,mt8186-smi-larb"; 1565 reg = <0 0x1602e000 0 0x1000>; 1566 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 1567 <&vdecsys CLK_VDEC_LARB1_CKEN>; 1568 clock-names = "apb", "smi"; 1569 mediatek,larb-id = <4>; 1570 mediatek,smi = <&smi_common>; 1571 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 1572 }; 1573 1574 vdecsys: clock-controller@1602f000 { 1575 compatible = "mediatek,mt8186-vdecsys"; 1576 reg = <0 0x1602f000 0 0x1000>; 1577 #clock-cells = <1>; 1578 }; 1579 1580 vencsys: clock-controller@17000000 { 1581 compatible = "mediatek,mt8186-vencsys"; 1582 reg = <0 0x17000000 0 0x1000>; 1583 #clock-cells = <1>; 1584 }; 1585 1586 larb7: smi@17010000 { 1587 compatible = "mediatek,mt8186-smi-larb"; 1588 reg = <0 0x17010000 0 0x1000>; 1589 clocks = <&vencsys CLK_VENC_CKE1_VENC>, 1590 <&vencsys CLK_VENC_CKE1_VENC>; 1591 clock-names = "apb", "smi"; 1592 mediatek,larb-id = <7>; 1593 mediatek,smi = <&smi_common>; 1594 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 1595 }; 1596 1597 camsys: clock-controller@1a000000 { 1598 compatible = "mediatek,mt8186-camsys"; 1599 reg = <0 0x1a000000 0 0x1000>; 1600 #clock-cells = <1>; 1601 }; 1602 1603 larb13: smi@1a001000 { 1604 compatible = "mediatek,mt8186-smi-larb"; 1605 reg = <0 0x1a001000 0 0x1000>; 1606 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 1607 clock-names = "apb", "smi"; 1608 mediatek,larb-id = <13>; 1609 mediatek,smi = <&smi_common>; 1610 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1611 }; 1612 1613 larb14: smi@1a002000 { 1614 compatible = "mediatek,mt8186-smi-larb"; 1615 reg = <0 0x1a002000 0 0x1000>; 1616 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 1617 clock-names = "apb", "smi"; 1618 mediatek,larb-id = <14>; 1619 mediatek,smi = <&smi_common>; 1620 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1621 }; 1622 1623 larb16: smi@1a00f000 { 1624 compatible = "mediatek,mt8186-smi-larb"; 1625 reg = <0 0x1a00f000 0 0x1000>; 1626 clocks = <&camsys CLK_CAM_LARB14>, 1627 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 1628 clock-names = "apb", "smi"; 1629 mediatek,larb-id = <16>; 1630 mediatek,smi = <&smi_common>; 1631 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 1632 }; 1633 1634 larb17: smi@1a010000 { 1635 compatible = "mediatek,mt8186-smi-larb"; 1636 reg = <0 0x1a010000 0 0x1000>; 1637 clocks = <&camsys CLK_CAM_LARB13>, 1638 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 1639 clock-names = "apb", "smi"; 1640 mediatek,larb-id = <17>; 1641 mediatek,smi = <&smi_common>; 1642 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 1643 }; 1644 1645 camsys_rawa: clock-controller@1a04f000 { 1646 compatible = "mediatek,mt8186-camsys_rawa"; 1647 reg = <0 0x1a04f000 0 0x1000>; 1648 #clock-cells = <1>; 1649 }; 1650 1651 camsys_rawb: clock-controller@1a06f000 { 1652 compatible = "mediatek,mt8186-camsys_rawb"; 1653 reg = <0 0x1a06f000 0 0x1000>; 1654 #clock-cells = <1>; 1655 }; 1656 1657 mdpsys: clock-controller@1b000000 { 1658 compatible = "mediatek,mt8186-mdpsys"; 1659 reg = <0 0x1b000000 0 0x1000>; 1660 #clock-cells = <1>; 1661 }; 1662 1663 larb2: smi@1b002000 { 1664 compatible = "mediatek,mt8186-smi-larb"; 1665 reg = <0 0x1b002000 0 0x1000>; 1666 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 1667 clock-names = "apb", "smi"; 1668 mediatek,larb-id = <2>; 1669 mediatek,smi = <&smi_common>; 1670 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1671 }; 1672 1673 ipesys: clock-controller@1c000000 { 1674 compatible = "mediatek,mt8186-ipesys"; 1675 reg = <0 0x1c000000 0 0x1000>; 1676 #clock-cells = <1>; 1677 }; 1678 1679 larb20: smi@1c00f000 { 1680 compatible = "mediatek,mt8186-smi-larb"; 1681 reg = <0 0x1c00f000 0 0x1000>; 1682 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 1683 clock-names = "apb", "smi"; 1684 mediatek,larb-id = <20>; 1685 mediatek,smi = <&smi_common>; 1686 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1687 }; 1688 1689 larb19: smi@1c10f000 { 1690 compatible = "mediatek,mt8186-smi-larb"; 1691 reg = <0 0x1c10f000 0 0x1000>; 1692 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 1693 clock-names = "apb", "smi"; 1694 mediatek,larb-id = <19>; 1695 mediatek,smi = <&smi_common>; 1696 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1697 }; 1698 }; 1699}; 1700