1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/memory/mt8186-memory-port.h> 11#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 12#include <dt-bindings/power/mt8186-power.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/reset/mt8186-resets.h> 15 16/ { 17 compatible = "mediatek,mt8186"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 32 core1 { 33 cpu = <&cpu1>; 34 }; 35 36 core2 { 37 cpu = <&cpu2>; 38 }; 39 40 core3 { 41 cpu = <&cpu3>; 42 }; 43 44 core4 { 45 cpu = <&cpu4>; 46 }; 47 48 core5 { 49 cpu = <&cpu5>; 50 }; 51 52 core6 { 53 cpu = <&cpu6>; 54 }; 55 56 core7 { 57 cpu = <&cpu7>; 58 }; 59 }; 60 }; 61 62 cpu0: cpu@0 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a55"; 65 reg = <0x000>; 66 enable-method = "psci"; 67 clock-frequency = <2000000000>; 68 capacity-dmips-mhz = <382>; 69 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 70 i-cache-size = <32768>; 71 i-cache-line-size = <64>; 72 i-cache-sets = <128>; 73 d-cache-size = <32768>; 74 d-cache-line-size = <64>; 75 d-cache-sets = <128>; 76 next-level-cache = <&l2_0>; 77 #cooling-cells = <2>; 78 }; 79 80 cpu1: cpu@100 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x100>; 84 enable-method = "psci"; 85 clock-frequency = <2000000000>; 86 capacity-dmips-mhz = <382>; 87 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 88 i-cache-size = <32768>; 89 i-cache-line-size = <64>; 90 i-cache-sets = <128>; 91 d-cache-size = <32768>; 92 d-cache-line-size = <64>; 93 d-cache-sets = <128>; 94 next-level-cache = <&l2_0>; 95 #cooling-cells = <2>; 96 }; 97 98 cpu2: cpu@200 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a55"; 101 reg = <0x200>; 102 enable-method = "psci"; 103 clock-frequency = <2000000000>; 104 capacity-dmips-mhz = <382>; 105 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 106 i-cache-size = <32768>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <128>; 109 d-cache-size = <32768>; 110 d-cache-line-size = <64>; 111 d-cache-sets = <128>; 112 next-level-cache = <&l2_0>; 113 #cooling-cells = <2>; 114 }; 115 116 cpu3: cpu@300 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a55"; 119 reg = <0x300>; 120 enable-method = "psci"; 121 clock-frequency = <2000000000>; 122 capacity-dmips-mhz = <382>; 123 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 124 i-cache-size = <32768>; 125 i-cache-line-size = <64>; 126 i-cache-sets = <128>; 127 d-cache-size = <32768>; 128 d-cache-line-size = <64>; 129 d-cache-sets = <128>; 130 next-level-cache = <&l2_0>; 131 #cooling-cells = <2>; 132 }; 133 134 cpu4: cpu@400 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a55"; 137 reg = <0x400>; 138 enable-method = "psci"; 139 clock-frequency = <2000000000>; 140 capacity-dmips-mhz = <382>; 141 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 142 i-cache-size = <32768>; 143 i-cache-line-size = <64>; 144 i-cache-sets = <128>; 145 d-cache-size = <32768>; 146 d-cache-line-size = <64>; 147 d-cache-sets = <128>; 148 next-level-cache = <&l2_0>; 149 #cooling-cells = <2>; 150 }; 151 152 cpu5: cpu@500 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a55"; 155 reg = <0x500>; 156 enable-method = "psci"; 157 clock-frequency = <2000000000>; 158 capacity-dmips-mhz = <382>; 159 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 160 i-cache-size = <32768>; 161 i-cache-line-size = <64>; 162 i-cache-sets = <128>; 163 d-cache-size = <32768>; 164 d-cache-line-size = <64>; 165 d-cache-sets = <128>; 166 next-level-cache = <&l2_0>; 167 #cooling-cells = <2>; 168 }; 169 170 cpu6: cpu@600 { 171 device_type = "cpu"; 172 compatible = "arm,cortex-a76"; 173 reg = <0x600>; 174 enable-method = "psci"; 175 clock-frequency = <2050000000>; 176 capacity-dmips-mhz = <1024>; 177 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 178 i-cache-size = <65536>; 179 i-cache-line-size = <64>; 180 i-cache-sets = <256>; 181 d-cache-size = <65536>; 182 d-cache-line-size = <64>; 183 d-cache-sets = <256>; 184 next-level-cache = <&l2_1>; 185 #cooling-cells = <2>; 186 }; 187 188 cpu7: cpu@700 { 189 device_type = "cpu"; 190 compatible = "arm,cortex-a76"; 191 reg = <0x700>; 192 enable-method = "psci"; 193 clock-frequency = <2050000000>; 194 capacity-dmips-mhz = <1024>; 195 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 196 i-cache-size = <65536>; 197 i-cache-line-size = <64>; 198 i-cache-sets = <256>; 199 d-cache-size = <65536>; 200 d-cache-line-size = <64>; 201 d-cache-sets = <256>; 202 next-level-cache = <&l2_1>; 203 #cooling-cells = <2>; 204 }; 205 206 idle-states { 207 entry-method = "psci"; 208 209 cpu_ret_l: cpu-retention-l { 210 compatible = "arm,idle-state"; 211 arm,psci-suspend-param = <0x00010001>; 212 local-timer-stop; 213 entry-latency-us = <50>; 214 exit-latency-us = <100>; 215 min-residency-us = <1600>; 216 }; 217 218 cpu_ret_b: cpu-retention-b { 219 compatible = "arm,idle-state"; 220 arm,psci-suspend-param = <0x00010001>; 221 local-timer-stop; 222 entry-latency-us = <50>; 223 exit-latency-us = <100>; 224 min-residency-us = <1400>; 225 }; 226 227 cpu_off_l: cpu-off-l { 228 compatible = "arm,idle-state"; 229 arm,psci-suspend-param = <0x01010001>; 230 local-timer-stop; 231 entry-latency-us = <100>; 232 exit-latency-us = <250>; 233 min-residency-us = <2100>; 234 }; 235 236 cpu_off_b: cpu-off-b { 237 compatible = "arm,idle-state"; 238 arm,psci-suspend-param = <0x01010001>; 239 local-timer-stop; 240 entry-latency-us = <100>; 241 exit-latency-us = <250>; 242 min-residency-us = <1900>; 243 }; 244 }; 245 246 l2_0: l2-cache0 { 247 compatible = "cache"; 248 cache-level = <2>; 249 cache-size = <131072>; 250 cache-line-size = <64>; 251 cache-sets = <512>; 252 next-level-cache = <&l3_0>; 253 }; 254 255 l2_1: l2-cache1 { 256 compatible = "cache"; 257 cache-level = <2>; 258 cache-size = <262144>; 259 cache-line-size = <64>; 260 cache-sets = <512>; 261 next-level-cache = <&l3_0>; 262 }; 263 264 l3_0: l3-cache { 265 compatible = "cache"; 266 cache-level = <3>; 267 cache-size = <1048576>; 268 cache-line-size = <64>; 269 cache-sets = <1024>; 270 cache-unified; 271 }; 272 }; 273 274 clk13m: fixed-factor-clock-13m { 275 compatible = "fixed-factor-clock"; 276 #clock-cells = <0>; 277 clocks = <&clk26m>; 278 clock-div = <2>; 279 clock-mult = <1>; 280 clock-output-names = "clk13m"; 281 }; 282 283 clk26m: oscillator-26m { 284 compatible = "fixed-clock"; 285 #clock-cells = <0>; 286 clock-frequency = <26000000>; 287 clock-output-names = "clk26m"; 288 }; 289 290 clk32k: oscillator-32k { 291 compatible = "fixed-clock"; 292 #clock-cells = <0>; 293 clock-frequency = <32768>; 294 clock-output-names = "clk32k"; 295 }; 296 297 pmu-a55 { 298 compatible = "arm,cortex-a55-pmu"; 299 interrupt-parent = <&gic>; 300 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 301 }; 302 303 pmu-a76 { 304 compatible = "arm,cortex-a76-pmu"; 305 interrupt-parent = <&gic>; 306 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 307 }; 308 309 psci { 310 compatible = "arm,psci-1.0"; 311 method = "smc"; 312 }; 313 314 timer { 315 compatible = "arm,armv8-timer"; 316 interrupt-parent = <&gic>; 317 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 318 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 319 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 320 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 321 }; 322 323 soc { 324 #address-cells = <2>; 325 #size-cells = <2>; 326 compatible = "simple-bus"; 327 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 328 ranges; 329 330 gic: interrupt-controller@c000000 { 331 compatible = "arm,gic-v3"; 332 #interrupt-cells = <4>; 333 #redistributor-regions = <1>; 334 interrupt-parent = <&gic>; 335 interrupt-controller; 336 reg = <0 0x0c000000 0 0x40000>, 337 <0 0x0c040000 0 0x200000>; 338 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 339 340 ppi-partitions { 341 ppi_cluster0: interrupt-partition-0 { 342 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 343 }; 344 345 ppi_cluster1: interrupt-partition-1 { 346 affinity = <&cpu6 &cpu7>; 347 }; 348 }; 349 }; 350 351 mcusys: syscon@c53a000 { 352 compatible = "mediatek,mt8186-mcusys", "syscon"; 353 reg = <0 0xc53a000 0 0x1000>; 354 #clock-cells = <1>; 355 }; 356 357 topckgen: syscon@10000000 { 358 compatible = "mediatek,mt8186-topckgen", "syscon"; 359 reg = <0 0x10000000 0 0x1000>; 360 #clock-cells = <1>; 361 }; 362 363 infracfg_ao: syscon@10001000 { 364 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 365 reg = <0 0x10001000 0 0x1000>; 366 #clock-cells = <1>; 367 #reset-cells = <1>; 368 }; 369 370 pericfg: syscon@10003000 { 371 compatible = "mediatek,mt8186-pericfg", "syscon"; 372 reg = <0 0x10003000 0 0x1000>; 373 }; 374 375 pio: pinctrl@10005000 { 376 compatible = "mediatek,mt8186-pinctrl"; 377 reg = <0 0x10005000 0 0x1000>, 378 <0 0x10002000 0 0x0200>, 379 <0 0x10002200 0 0x0200>, 380 <0 0x10002400 0 0x0200>, 381 <0 0x10002600 0 0x0200>, 382 <0 0x10002a00 0 0x0200>, 383 <0 0x10002c00 0 0x0200>, 384 <0 0x1000b000 0 0x1000>; 385 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 386 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 387 gpio-controller; 388 #gpio-cells = <2>; 389 gpio-ranges = <&pio 0 0 185>; 390 interrupt-controller; 391 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 392 #interrupt-cells = <2>; 393 }; 394 395 scpsys: syscon@10006000 { 396 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 397 reg = <0 0x10006000 0 0x1000>; 398 399 /* System Power Manager */ 400 spm: power-controller { 401 compatible = "mediatek,mt8186-power-controller"; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 #power-domain-cells = <1>; 405 406 /* power domain of the SoC */ 407 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 408 reg = <MT8186_POWER_DOMAIN_MFG0>; 409 clocks = <&topckgen CLK_TOP_MFG>; 410 clock-names = "mfg00"; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 #power-domain-cells = <1>; 414 415 power-domain@MT8186_POWER_DOMAIN_MFG1 { 416 reg = <MT8186_POWER_DOMAIN_MFG1>; 417 mediatek,infracfg = <&infracfg_ao>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 #power-domain-cells = <1>; 421 422 power-domain@MT8186_POWER_DOMAIN_MFG2 { 423 reg = <MT8186_POWER_DOMAIN_MFG2>; 424 #power-domain-cells = <0>; 425 }; 426 427 power-domain@MT8186_POWER_DOMAIN_MFG3 { 428 reg = <MT8186_POWER_DOMAIN_MFG3>; 429 #power-domain-cells = <0>; 430 }; 431 }; 432 }; 433 434 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 435 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 436 clocks = <&topckgen CLK_TOP_SENINF>, 437 <&topckgen CLK_TOP_SENINF1>; 438 clock-names = "csirx_top0", "csirx_top1"; 439 #power-domain-cells = <0>; 440 }; 441 442 power-domain@MT8186_POWER_DOMAIN_SSUSB { 443 reg = <MT8186_POWER_DOMAIN_SSUSB>; 444 #power-domain-cells = <0>; 445 }; 446 447 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 448 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 449 #power-domain-cells = <0>; 450 }; 451 452 power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 453 reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 454 clocks = <&topckgen CLK_TOP_AUDIODSP>, 455 <&topckgen CLK_TOP_ADSP_BUS>; 456 clock-names = "audioadsp", "adsp_bus"; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 #power-domain-cells = <1>; 460 461 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 462 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 #power-domain-cells = <1>; 466 467 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 468 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 469 mediatek,infracfg = <&infracfg_ao>; 470 #power-domain-cells = <0>; 471 }; 472 }; 473 }; 474 475 power-domain@MT8186_POWER_DOMAIN_CONN_ON { 476 reg = <MT8186_POWER_DOMAIN_CONN_ON>; 477 mediatek,infracfg = <&infracfg_ao>; 478 #power-domain-cells = <0>; 479 }; 480 481 power-domain@MT8186_POWER_DOMAIN_DIS { 482 reg = <MT8186_POWER_DOMAIN_DIS>; 483 clocks = <&topckgen CLK_TOP_DISP>, 484 <&topckgen CLK_TOP_MDP>, 485 <&mmsys CLK_MM_SMI_INFRA>, 486 <&mmsys CLK_MM_SMI_COMMON>, 487 <&mmsys CLK_MM_SMI_GALS>, 488 <&mmsys CLK_MM_SMI_IOMMU>; 489 clock-names = "disp", "mdp", "smi_infra", "smi_common", 490 "smi_gals", "smi_iommu"; 491 mediatek,infracfg = <&infracfg_ao>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 #power-domain-cells = <1>; 495 496 power-domain@MT8186_POWER_DOMAIN_VDEC { 497 reg = <MT8186_POWER_DOMAIN_VDEC>; 498 clocks = <&topckgen CLK_TOP_VDEC>, 499 <&vdecsys CLK_VDEC_LARB1_CKEN>; 500 clock-names = "vdec0", "larb"; 501 mediatek,infracfg = <&infracfg_ao>; 502 #power-domain-cells = <0>; 503 }; 504 505 power-domain@MT8186_POWER_DOMAIN_CAM { 506 reg = <MT8186_POWER_DOMAIN_CAM>; 507 clocks = <&topckgen CLK_TOP_CAM>, 508 <&topckgen CLK_TOP_SENINF>, 509 <&topckgen CLK_TOP_SENINF1>, 510 <&topckgen CLK_TOP_SENINF2>, 511 <&topckgen CLK_TOP_SENINF3>, 512 <&topckgen CLK_TOP_CAMTM>, 513 <&camsys CLK_CAM2MM_GALS>; 514 clock-names = "cam-top", "cam0", "cam1", "cam2", 515 "cam3", "cam-tm", "gals"; 516 mediatek,infracfg = <&infracfg_ao>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 #power-domain-cells = <1>; 520 521 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 522 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 523 #power-domain-cells = <0>; 524 }; 525 526 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 527 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 528 #power-domain-cells = <0>; 529 }; 530 }; 531 532 power-domain@MT8186_POWER_DOMAIN_IMG { 533 reg = <MT8186_POWER_DOMAIN_IMG>; 534 clocks = <&topckgen CLK_TOP_IMG1>, 535 <&imgsys1 CLK_IMG1_GALS_IMG1>; 536 clock-names = "img-top", "gals"; 537 mediatek,infracfg = <&infracfg_ao>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 #power-domain-cells = <1>; 541 542 power-domain@MT8186_POWER_DOMAIN_IMG2 { 543 reg = <MT8186_POWER_DOMAIN_IMG2>; 544 #power-domain-cells = <0>; 545 }; 546 }; 547 548 power-domain@MT8186_POWER_DOMAIN_IPE { 549 reg = <MT8186_POWER_DOMAIN_IPE>; 550 clocks = <&topckgen CLK_TOP_IPE>, 551 <&ipesys CLK_IPE_LARB19>, 552 <&ipesys CLK_IPE_LARB20>, 553 <&ipesys CLK_IPE_SMI_SUBCOM>, 554 <&ipesys CLK_IPE_GALS_IPE>; 555 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", 556 "ipe-smi", "ipe-gals"; 557 mediatek,infracfg = <&infracfg_ao>; 558 #power-domain-cells = <0>; 559 }; 560 561 power-domain@MT8186_POWER_DOMAIN_VENC { 562 reg = <MT8186_POWER_DOMAIN_VENC>; 563 clocks = <&topckgen CLK_TOP_VENC>, 564 <&vencsys CLK_VENC_CKE1_VENC>; 565 clock-names = "venc0", "larb"; 566 mediatek,infracfg = <&infracfg_ao>; 567 #power-domain-cells = <0>; 568 }; 569 570 power-domain@MT8186_POWER_DOMAIN_WPE { 571 reg = <MT8186_POWER_DOMAIN_WPE>; 572 clocks = <&topckgen CLK_TOP_WPE>, 573 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 574 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 575 clock-names = "wpe0", "larb-ck", "larb-pclk"; 576 mediatek,infracfg = <&infracfg_ao>; 577 #power-domain-cells = <0>; 578 }; 579 }; 580 }; 581 }; 582 583 watchdog: watchdog@10007000 { 584 compatible = "mediatek,mt8186-wdt"; 585 mediatek,disable-extrst; 586 reg = <0 0x10007000 0 0x1000>; 587 #reset-cells = <1>; 588 }; 589 590 apmixedsys: syscon@1000c000 { 591 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 592 reg = <0 0x1000c000 0 0x1000>; 593 #clock-cells = <1>; 594 }; 595 596 pwrap: pwrap@1000d000 { 597 compatible = "mediatek,mt8186-pwrap", "syscon"; 598 reg = <0 0x1000d000 0 0x1000>; 599 reg-names = "pwrap"; 600 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 601 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 602 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 603 clock-names = "spi", "wrap"; 604 }; 605 606 spmi: spmi@10015000 { 607 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; 608 reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; 609 reg-names = "pmif", "spmimst"; 610 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 611 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 612 <&topckgen CLK_TOP_SPMI_MST>; 613 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 614 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; 615 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 616 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>, 617 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>; 618 status = "disabled"; 619 }; 620 621 systimer: timer@10017000 { 622 compatible = "mediatek,mt8186-timer", 623 "mediatek,mt6765-timer"; 624 reg = <0 0x10017000 0 0x1000>; 625 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 626 clocks = <&clk13m>; 627 }; 628 629 scp: scp@10500000 { 630 compatible = "mediatek,mt8186-scp"; 631 reg = <0 0x10500000 0 0x40000>, 632 <0 0x105c0000 0 0x19080>; 633 reg-names = "sram", "cfg"; 634 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 635 }; 636 637 adsp_mailbox0: mailbox@10686000 { 638 compatible = "mediatek,mt8186-adsp-mbox"; 639 #mbox-cells = <0>; 640 reg = <0 0x10686100 0 0x1000>; 641 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 642 }; 643 644 adsp_mailbox1: mailbox@10687000 { 645 compatible = "mediatek,mt8186-adsp-mbox"; 646 #mbox-cells = <0>; 647 reg = <0 0x10687100 0 0x1000>; 648 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>; 649 }; 650 651 nor_flash: spi@11000000 { 652 compatible = "mediatek,mt8186-nor"; 653 reg = <0 0x11000000 0 0x1000>; 654 clocks = <&topckgen CLK_TOP_SPINOR>, 655 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 656 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 657 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 658 clock-names = "spi", "sf", "axi", "axi_s"; 659 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 660 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 661 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 662 status = "disabled"; 663 }; 664 665 auxadc: adc@11001000 { 666 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 667 reg = <0 0x11001000 0 0x1000>; 668 #io-channel-cells = <1>; 669 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 670 clock-names = "main"; 671 }; 672 673 uart0: serial@11002000 { 674 compatible = "mediatek,mt8186-uart", 675 "mediatek,mt6577-uart"; 676 reg = <0 0x11002000 0 0x1000>; 677 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 678 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 679 clock-names = "baud", "bus"; 680 status = "disabled"; 681 }; 682 683 uart1: serial@11003000 { 684 compatible = "mediatek,mt8186-uart", 685 "mediatek,mt6577-uart"; 686 reg = <0 0x11003000 0 0x1000>; 687 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 688 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 689 clock-names = "baud", "bus"; 690 status = "disabled"; 691 }; 692 693 i2c0: i2c@11007000 { 694 compatible = "mediatek,mt8186-i2c"; 695 reg = <0 0x11007000 0 0x1000>, 696 <0 0x10200100 0 0x100>; 697 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 698 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 699 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 700 clock-names = "main", "dma"; 701 clock-div = <1>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 status = "disabled"; 705 }; 706 707 i2c1: i2c@11008000 { 708 compatible = "mediatek,mt8186-i2c"; 709 reg = <0 0x11008000 0 0x1000>, 710 <0 0x10200200 0 0x100>; 711 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 712 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 713 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 714 clock-names = "main", "dma"; 715 clock-div = <1>; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 status = "disabled"; 719 }; 720 721 i2c2: i2c@11009000 { 722 compatible = "mediatek,mt8186-i2c"; 723 reg = <0 0x11009000 0 0x1000>, 724 <0 0x10200300 0 0x180>; 725 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 726 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 727 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 728 clock-names = "main", "dma"; 729 clock-div = <1>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 status = "disabled"; 733 }; 734 735 i2c3: i2c@1100f000 { 736 compatible = "mediatek,mt8186-i2c"; 737 reg = <0 0x1100f000 0 0x1000>, 738 <0 0x10200480 0 0x100>; 739 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 740 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 741 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 742 clock-names = "main", "dma"; 743 clock-div = <1>; 744 #address-cells = <1>; 745 #size-cells = <0>; 746 status = "disabled"; 747 }; 748 749 i2c4: i2c@11011000 { 750 compatible = "mediatek,mt8186-i2c"; 751 reg = <0 0x11011000 0 0x1000>, 752 <0 0x10200580 0 0x180>; 753 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 754 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 755 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 756 clock-names = "main", "dma"; 757 clock-div = <1>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 status = "disabled"; 761 }; 762 763 i2c5: i2c@11016000 { 764 compatible = "mediatek,mt8186-i2c"; 765 reg = <0 0x11016000 0 0x1000>, 766 <0 0x10200700 0 0x100>; 767 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 768 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 769 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 770 clock-names = "main", "dma"; 771 clock-div = <1>; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 status = "disabled"; 775 }; 776 777 i2c6: i2c@1100d000 { 778 compatible = "mediatek,mt8186-i2c"; 779 reg = <0 0x1100d000 0 0x1000>, 780 <0 0x10200800 0 0x100>; 781 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 782 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 783 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 784 clock-names = "main", "dma"; 785 clock-div = <1>; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 status = "disabled"; 789 }; 790 791 i2c7: i2c@11004000 { 792 compatible = "mediatek,mt8186-i2c"; 793 reg = <0 0x11004000 0 0x1000>, 794 <0 0x10200900 0 0x180>; 795 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 796 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 797 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 798 clock-names = "main", "dma"; 799 clock-div = <1>; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 status = "disabled"; 803 }; 804 805 i2c8: i2c@11005000 { 806 compatible = "mediatek,mt8186-i2c"; 807 reg = <0 0x11005000 0 0x1000>, 808 <0 0x10200A80 0 0x180>; 809 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 810 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 811 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 812 clock-names = "main", "dma"; 813 clock-div = <1>; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 status = "disabled"; 817 }; 818 819 spi0: spi@1100a000 { 820 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 reg = <0 0x1100a000 0 0x1000>; 824 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 825 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 826 <&topckgen CLK_TOP_SPI>, 827 <&infracfg_ao CLK_INFRA_AO_SPI0>; 828 clock-names = "parent-clk", "sel-clk", "spi-clk"; 829 status = "disabled"; 830 }; 831 832 pwm0: pwm@1100e000 { 833 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 834 reg = <0 0x1100e000 0 0x1000>; 835 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 836 #pwm-cells = <2>; 837 clocks = <&topckgen CLK_TOP_DISP_PWM>, 838 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 839 clock-names = "main", "mm"; 840 status = "disabled"; 841 }; 842 843 spi1: spi@11010000 { 844 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 reg = <0 0x11010000 0 0x1000>; 848 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 849 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 850 <&topckgen CLK_TOP_SPI>, 851 <&infracfg_ao CLK_INFRA_AO_SPI1>; 852 clock-names = "parent-clk", "sel-clk", "spi-clk"; 853 status = "disabled"; 854 }; 855 856 spi2: spi@11012000 { 857 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 reg = <0 0x11012000 0 0x1000>; 861 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 862 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 863 <&topckgen CLK_TOP_SPI>, 864 <&infracfg_ao CLK_INFRA_AO_SPI2>; 865 clock-names = "parent-clk", "sel-clk", "spi-clk"; 866 status = "disabled"; 867 }; 868 869 spi3: spi@11013000 { 870 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 reg = <0 0x11013000 0 0x1000>; 874 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 875 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 876 <&topckgen CLK_TOP_SPI>, 877 <&infracfg_ao CLK_INFRA_AO_SPI3>; 878 clock-names = "parent-clk", "sel-clk", "spi-clk"; 879 status = "disabled"; 880 }; 881 882 spi4: spi@11014000 { 883 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 reg = <0 0x11014000 0 0x1000>; 887 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 888 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 889 <&topckgen CLK_TOP_SPI>, 890 <&infracfg_ao CLK_INFRA_AO_SPI4>; 891 clock-names = "parent-clk", "sel-clk", "spi-clk"; 892 status = "disabled"; 893 }; 894 895 spi5: spi@11015000 { 896 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 897 #address-cells = <1>; 898 #size-cells = <0>; 899 reg = <0 0x11015000 0 0x1000>; 900 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 901 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 902 <&topckgen CLK_TOP_SPI>, 903 <&infracfg_ao CLK_INFRA_AO_SPI5>; 904 clock-names = "parent-clk", "sel-clk", "spi-clk"; 905 status = "disabled"; 906 }; 907 908 imp_iic_wrap: clock-controller@11017000 { 909 compatible = "mediatek,mt8186-imp_iic_wrap"; 910 reg = <0 0x11017000 0 0x1000>; 911 #clock-cells = <1>; 912 }; 913 914 uart2: serial@11018000 { 915 compatible = "mediatek,mt8186-uart", 916 "mediatek,mt6577-uart"; 917 reg = <0 0x11018000 0 0x1000>; 918 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 919 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 920 clock-names = "baud", "bus"; 921 status = "disabled"; 922 }; 923 924 i2c9: i2c@11019000 { 925 compatible = "mediatek,mt8186-i2c"; 926 reg = <0 0x11019000 0 0x1000>, 927 <0 0x10200c00 0 0x180>; 928 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 929 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 930 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 931 clock-names = "main", "dma"; 932 clock-div = <1>; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 status = "disabled"; 936 }; 937 938 afe: audio-controller@11210000 { 939 compatible = "mediatek,mt8186-sound"; 940 reg = <0 0x11210000 0 0x2000>; 941 clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, 942 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, 943 <&topckgen CLK_TOP_AUDIO>, 944 <&topckgen CLK_TOP_AUD_INTBUS>, 945 <&topckgen CLK_TOP_MAINPLL_D2_D4>, 946 <&topckgen CLK_TOP_AUD_1>, 947 <&apmixedsys CLK_APMIXED_APLL1>, 948 <&topckgen CLK_TOP_AUD_2>, 949 <&apmixedsys CLK_APMIXED_APLL2>, 950 <&topckgen CLK_TOP_AUD_ENGEN1>, 951 <&topckgen CLK_TOP_APLL1_D8>, 952 <&topckgen CLK_TOP_AUD_ENGEN2>, 953 <&topckgen CLK_TOP_APLL2_D8>, 954 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, 955 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, 956 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, 957 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, 958 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, 959 <&topckgen CLK_TOP_APLL12_CK_DIV0>, 960 <&topckgen CLK_TOP_APLL12_CK_DIV1>, 961 <&topckgen CLK_TOP_APLL12_CK_DIV2>, 962 <&topckgen CLK_TOP_APLL12_CK_DIV4>, 963 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, 964 <&topckgen CLK_TOP_AUDIO_H>, 965 <&clk26m>; 966 clock-names = "aud_infra_clk", 967 "mtkaif_26m_clk", 968 "top_mux_audio", 969 "top_mux_audio_int", 970 "top_mainpll_d2_d4", 971 "top_mux_aud_1", 972 "top_apll1_ck", 973 "top_mux_aud_2", 974 "top_apll2_ck", 975 "top_mux_aud_eng1", 976 "top_apll1_d8", 977 "top_mux_aud_eng2", 978 "top_apll2_d8", 979 "top_i2s0_m_sel", 980 "top_i2s1_m_sel", 981 "top_i2s2_m_sel", 982 "top_i2s4_m_sel", 983 "top_tdm_m_sel", 984 "top_apll12_div0", 985 "top_apll12_div1", 986 "top_apll12_div2", 987 "top_apll12_div4", 988 "top_apll12_div_tdm", 989 "top_mux_audio_h", 990 "top_clk26m_clk"; 991 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 992 mediatek,apmixedsys = <&apmixedsys>; 993 mediatek,infracfg = <&infracfg_ao>; 994 mediatek,topckgen = <&topckgen>; 995 resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; 996 reset-names = "audiosys"; 997 status = "disabled"; 998 }; 999 1000 ssusb0: usb@11201000 { 1001 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1002 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1003 reg-names = "mac", "ippc"; 1004 clocks = <&topckgen CLK_TOP_USB_TOP>, 1005 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1006 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1007 <&infracfg_ao CLK_INFRA_AO_ICUSB>; 1008 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1009 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>; 1010 phys = <&u2port0 PHY_TYPE_USB2>; 1011 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; 1012 #address-cells = <2>; 1013 #size-cells = <2>; 1014 ranges; 1015 status = "disabled"; 1016 1017 usb_host0: usb@11200000 { 1018 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1019 reg = <0 0x11200000 0 0x1000>; 1020 reg-names = "mac"; 1021 clocks = <&topckgen CLK_TOP_USB_TOP>, 1022 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1023 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1024 <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1025 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1026 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1027 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 1028 mediatek,syscon-wakeup = <&pericfg 0x420 2>; 1029 wakeup-source; 1030 status = "disabled"; 1031 }; 1032 }; 1033 1034 mmc0: mmc@11230000 { 1035 compatible = "mediatek,mt8186-mmc", 1036 "mediatek,mt8183-mmc"; 1037 reg = <0 0x11230000 0 0x10000>, 1038 <0 0x11cd0000 0 0x1000>; 1039 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1040 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1041 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1042 <&infracfg_ao CLK_INFRA_AO_MSDCFDE>; 1043 clock-names = "source", "hclk", "source_cg", "crypto"; 1044 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 1045 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 1046 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 1047 status = "disabled"; 1048 }; 1049 1050 mmc1: mmc@11240000 { 1051 compatible = "mediatek,mt8186-mmc", 1052 "mediatek,mt8183-mmc"; 1053 reg = <0 0x11240000 0 0x1000>, 1054 <0 0x11c90000 0 0x1000>; 1055 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1056 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1057 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1058 clock-names = "source", "hclk", "source_cg"; 1059 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 1060 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1061 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1062 status = "disabled"; 1063 }; 1064 1065 ssusb1: usb@11281000 { 1066 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1067 reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; 1068 reg-names = "mac", "ippc"; 1069 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1070 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1071 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1072 <&clk26m>; 1073 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1074 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 1075 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1076 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; 1077 #address-cells = <2>; 1078 #size-cells = <2>; 1079 ranges; 1080 status = "disabled"; 1081 1082 usb_host1: usb@11280000 { 1083 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1084 reg = <0 0x11280000 0 0x1000>; 1085 reg-names = "mac"; 1086 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1087 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1088 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1089 <&clk26m>, 1090 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1091 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; 1092 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1093 mediatek,syscon-wakeup = <&pericfg 0x424 2>; 1094 wakeup-source; 1095 status = "disabled"; 1096 }; 1097 }; 1098 1099 u3phy0: t-phy@11c80000 { 1100 compatible = "mediatek,mt8186-tphy", 1101 "mediatek,generic-tphy-v2"; 1102 #address-cells = <1>; 1103 #size-cells = <1>; 1104 ranges = <0x0 0x0 0x11c80000 0x1000>; 1105 status = "disabled"; 1106 1107 u2port1: usb-phy@0 { 1108 reg = <0x0 0x700>; 1109 clocks = <&clk26m>; 1110 clock-names = "ref"; 1111 #phy-cells = <1>; 1112 }; 1113 1114 u3port1: usb-phy@700 { 1115 reg = <0x700 0x900>; 1116 clocks = <&clk26m>; 1117 clock-names = "ref"; 1118 #phy-cells = <1>; 1119 }; 1120 }; 1121 1122 u3phy1: t-phy@11ca0000 { 1123 compatible = "mediatek,mt8186-tphy", 1124 "mediatek,generic-tphy-v2"; 1125 #address-cells = <1>; 1126 #size-cells = <1>; 1127 ranges = <0x0 0x0 0x11ca0000 0x1000>; 1128 status = "disabled"; 1129 1130 u2port0: usb-phy@0 { 1131 reg = <0x0 0x700>; 1132 clocks = <&clk26m>; 1133 clock-names = "ref"; 1134 #phy-cells = <1>; 1135 mediatek,discth = <0x8>; 1136 }; 1137 }; 1138 1139 efuse: efuse@11cb0000 { 1140 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 1141 reg = <0 0x11cb0000 0 0x1000>; 1142 #address-cells = <1>; 1143 #size-cells = <1>; 1144 }; 1145 1146 mipi_tx0: dsi-phy@11cc0000 { 1147 compatible = "mediatek,mt8183-mipi-tx"; 1148 reg = <0 0x11cc0000 0 0x1000>; 1149 clocks = <&clk26m>; 1150 #clock-cells = <0>; 1151 #phy-cells = <0>; 1152 clock-output-names = "mipi_tx0_pll"; 1153 status = "disabled"; 1154 }; 1155 1156 mfgsys: clock-controller@13000000 { 1157 compatible = "mediatek,mt8186-mfgsys"; 1158 reg = <0 0x13000000 0 0x1000>; 1159 #clock-cells = <1>; 1160 }; 1161 1162 gpu: gpu@13040000 { 1163 compatible = "mediatek,mt8186-mali", 1164 "arm,mali-bifrost"; 1165 reg = <0 0x13040000 0 0x4000>; 1166 1167 clocks = <&mfgsys CLK_MFG_BG3D>; 1168 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>, 1169 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>, 1170 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 1171 interrupt-names = "job", "mmu", "gpu"; 1172 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>, 1173 <&spm MT8186_POWER_DOMAIN_MFG3>; 1174 power-domain-names = "core0", "core1"; 1175 #cooling-cells = <2>; 1176 status = "disabled"; 1177 }; 1178 1179 mmsys: syscon@14000000 { 1180 compatible = "mediatek,mt8186-mmsys", "syscon"; 1181 reg = <0 0x14000000 0 0x1000>; 1182 #clock-cells = <1>; 1183 #reset-cells = <1>; 1184 }; 1185 1186 smi_common: smi@14002000 { 1187 compatible = "mediatek,mt8186-smi-common"; 1188 reg = <0 0x14002000 0 0x1000>; 1189 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 1190 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 1191 clock-names = "apb", "smi", "gals0", "gals1"; 1192 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1193 }; 1194 1195 larb0: smi@14003000 { 1196 compatible = "mediatek,mt8186-smi-larb"; 1197 reg = <0 0x14003000 0 0x1000>; 1198 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1199 <&mmsys CLK_MM_SMI_COMMON>; 1200 clock-names = "apb", "smi"; 1201 mediatek,larb-id = <0>; 1202 mediatek,smi = <&smi_common>; 1203 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1204 }; 1205 1206 larb1: smi@14004000 { 1207 compatible = "mediatek,mt8186-smi-larb"; 1208 reg = <0 0x14004000 0 0x1000>; 1209 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1210 <&mmsys CLK_MM_SMI_COMMON>; 1211 clock-names = "apb", "smi"; 1212 mediatek,larb-id = <1>; 1213 mediatek,smi = <&smi_common>; 1214 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1215 }; 1216 1217 dpi: dpi@1400a000 { 1218 compatible = "mediatek,mt8186-dpi"; 1219 reg = <0 0x1400a000 0 0x1000>; 1220 clocks = <&topckgen CLK_TOP_DPI>, 1221 <&mmsys CLK_MM_DISP_DPI>, 1222 <&apmixedsys CLK_APMIXED_TVDPLL>; 1223 clock-names = "pixel", "engine", "pll"; 1224 assigned-clocks = <&topckgen CLK_TOP_DPI>; 1225 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; 1226 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; 1227 status = "disabled"; 1228 1229 port { 1230 dpi_out: endpoint { }; 1231 }; 1232 }; 1233 1234 dsi0: dsi@14013000 { 1235 compatible = "mediatek,mt8186-dsi"; 1236 reg = <0 0x14013000 0 0x1000>; 1237 clocks = <&mmsys CLK_MM_DSI0>, 1238 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 1239 <&mipi_tx0>; 1240 clock-names = "engine", "digital", "hs"; 1241 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 1242 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1243 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 1244 phys = <&mipi_tx0>; 1245 phy-names = "dphy"; 1246 status = "disabled"; 1247 1248 port { 1249 dsi_out: endpoint { }; 1250 }; 1251 }; 1252 1253 iommu_mm: iommu@14016000 { 1254 compatible = "mediatek,mt8186-iommu-mm"; 1255 reg = <0 0x14016000 0 0x1000>; 1256 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1257 clock-names = "bclk"; 1258 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1259 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1260 &larb7 &larb8 &larb9 &larb11 1261 &larb13 &larb14 &larb16 &larb17 1262 &larb19 &larb20>; 1263 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1264 #iommu-cells = <1>; 1265 }; 1266 1267 wpesys: clock-controller@14020000 { 1268 compatible = "mediatek,mt8186-wpesys"; 1269 reg = <0 0x14020000 0 0x1000>; 1270 #clock-cells = <1>; 1271 }; 1272 1273 larb8: smi@14023000 { 1274 compatible = "mediatek,mt8186-smi-larb"; 1275 reg = <0 0x14023000 0 0x1000>; 1276 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1277 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1278 clock-names = "apb", "smi"; 1279 mediatek,larb-id = <8>; 1280 mediatek,smi = <&smi_common>; 1281 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1282 }; 1283 1284 imgsys1: clock-controller@15020000 { 1285 compatible = "mediatek,mt8186-imgsys1"; 1286 reg = <0 0x15020000 0 0x1000>; 1287 #clock-cells = <1>; 1288 }; 1289 1290 larb9: smi@1502e000 { 1291 compatible = "mediatek,mt8186-smi-larb"; 1292 reg = <0 0x1502e000 0 0x1000>; 1293 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1294 <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1295 clock-names = "apb", "smi"; 1296 mediatek,larb-id = <9>; 1297 mediatek,smi = <&smi_common>; 1298 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 1299 }; 1300 1301 imgsys2: clock-controller@15820000 { 1302 compatible = "mediatek,mt8186-imgsys2"; 1303 reg = <0 0x15820000 0 0x1000>; 1304 #clock-cells = <1>; 1305 }; 1306 1307 larb11: smi@1582e000 { 1308 compatible = "mediatek,mt8186-smi-larb"; 1309 reg = <0 0x1582e000 0 0x1000>; 1310 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 1311 <&imgsys2 CLK_IMG2_LARB9_IMG2>; 1312 clock-names = "apb", "smi"; 1313 mediatek,larb-id = <11>; 1314 mediatek,smi = <&smi_common>; 1315 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 1316 }; 1317 1318 larb4: smi@1602e000 { 1319 compatible = "mediatek,mt8186-smi-larb"; 1320 reg = <0 0x1602e000 0 0x1000>; 1321 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 1322 <&vdecsys CLK_VDEC_LARB1_CKEN>; 1323 clock-names = "apb", "smi"; 1324 mediatek,larb-id = <4>; 1325 mediatek,smi = <&smi_common>; 1326 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 1327 }; 1328 1329 vdecsys: clock-controller@1602f000 { 1330 compatible = "mediatek,mt8186-vdecsys"; 1331 reg = <0 0x1602f000 0 0x1000>; 1332 #clock-cells = <1>; 1333 }; 1334 1335 vencsys: clock-controller@17000000 { 1336 compatible = "mediatek,mt8186-vencsys"; 1337 reg = <0 0x17000000 0 0x1000>; 1338 #clock-cells = <1>; 1339 }; 1340 1341 larb7: smi@17010000 { 1342 compatible = "mediatek,mt8186-smi-larb"; 1343 reg = <0 0x17010000 0 0x1000>; 1344 clocks = <&vencsys CLK_VENC_CKE1_VENC>, 1345 <&vencsys CLK_VENC_CKE1_VENC>; 1346 clock-names = "apb", "smi"; 1347 mediatek,larb-id = <7>; 1348 mediatek,smi = <&smi_common>; 1349 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 1350 }; 1351 1352 camsys: clock-controller@1a000000 { 1353 compatible = "mediatek,mt8186-camsys"; 1354 reg = <0 0x1a000000 0 0x1000>; 1355 #clock-cells = <1>; 1356 }; 1357 1358 larb13: smi@1a001000 { 1359 compatible = "mediatek,mt8186-smi-larb"; 1360 reg = <0 0x1a001000 0 0x1000>; 1361 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 1362 clock-names = "apb", "smi"; 1363 mediatek,larb-id = <13>; 1364 mediatek,smi = <&smi_common>; 1365 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1366 }; 1367 1368 larb14: smi@1a002000 { 1369 compatible = "mediatek,mt8186-smi-larb"; 1370 reg = <0 0x1a002000 0 0x1000>; 1371 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 1372 clock-names = "apb", "smi"; 1373 mediatek,larb-id = <14>; 1374 mediatek,smi = <&smi_common>; 1375 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1376 }; 1377 1378 larb16: smi@1a00f000 { 1379 compatible = "mediatek,mt8186-smi-larb"; 1380 reg = <0 0x1a00f000 0 0x1000>; 1381 clocks = <&camsys CLK_CAM_LARB14>, 1382 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 1383 clock-names = "apb", "smi"; 1384 mediatek,larb-id = <16>; 1385 mediatek,smi = <&smi_common>; 1386 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 1387 }; 1388 1389 larb17: smi@1a010000 { 1390 compatible = "mediatek,mt8186-smi-larb"; 1391 reg = <0 0x1a010000 0 0x1000>; 1392 clocks = <&camsys CLK_CAM_LARB13>, 1393 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 1394 clock-names = "apb", "smi"; 1395 mediatek,larb-id = <17>; 1396 mediatek,smi = <&smi_common>; 1397 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 1398 }; 1399 1400 camsys_rawa: clock-controller@1a04f000 { 1401 compatible = "mediatek,mt8186-camsys_rawa"; 1402 reg = <0 0x1a04f000 0 0x1000>; 1403 #clock-cells = <1>; 1404 }; 1405 1406 camsys_rawb: clock-controller@1a06f000 { 1407 compatible = "mediatek,mt8186-camsys_rawb"; 1408 reg = <0 0x1a06f000 0 0x1000>; 1409 #clock-cells = <1>; 1410 }; 1411 1412 mdpsys: clock-controller@1b000000 { 1413 compatible = "mediatek,mt8186-mdpsys"; 1414 reg = <0 0x1b000000 0 0x1000>; 1415 #clock-cells = <1>; 1416 }; 1417 1418 larb2: smi@1b002000 { 1419 compatible = "mediatek,mt8186-smi-larb"; 1420 reg = <0 0x1b002000 0 0x1000>; 1421 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 1422 clock-names = "apb", "smi"; 1423 mediatek,larb-id = <2>; 1424 mediatek,smi = <&smi_common>; 1425 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1426 }; 1427 1428 ipesys: clock-controller@1c000000 { 1429 compatible = "mediatek,mt8186-ipesys"; 1430 reg = <0 0x1c000000 0 0x1000>; 1431 #clock-cells = <1>; 1432 }; 1433 1434 larb20: smi@1c00f000 { 1435 compatible = "mediatek,mt8186-smi-larb"; 1436 reg = <0 0x1c00f000 0 0x1000>; 1437 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 1438 clock-names = "apb", "smi"; 1439 mediatek,larb-id = <20>; 1440 mediatek,smi = <&smi_common>; 1441 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1442 }; 1443 1444 larb19: smi@1c10f000 { 1445 compatible = "mediatek,mt8186-smi-larb"; 1446 reg = <0 0x1c10f000 0 0x1000>; 1447 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 1448 clock-names = "apb", "smi"; 1449 mediatek,larb-id = <19>; 1450 mediatek,smi = <&smi_common>; 1451 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1452 }; 1453 }; 1454}; 1455