1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/memory/mt8186-memory-port.h> 11#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 12#include <dt-bindings/power/mt8186-power.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/reset/mt8186-resets.h> 15 16/ { 17 compatible = "mediatek,mt8186"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 32 core1 { 33 cpu = <&cpu1>; 34 }; 35 36 core2 { 37 cpu = <&cpu2>; 38 }; 39 40 core3 { 41 cpu = <&cpu3>; 42 }; 43 44 core4 { 45 cpu = <&cpu4>; 46 }; 47 48 core5 { 49 cpu = <&cpu5>; 50 }; 51 52 core6 { 53 cpu = <&cpu6>; 54 }; 55 56 core7 { 57 cpu = <&cpu7>; 58 }; 59 }; 60 }; 61 62 cpu0: cpu@0 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a55"; 65 reg = <0x000>; 66 enable-method = "psci"; 67 clock-frequency = <2000000000>; 68 capacity-dmips-mhz = <382>; 69 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 70 i-cache-size = <32768>; 71 i-cache-line-size = <64>; 72 i-cache-sets = <128>; 73 d-cache-size = <32768>; 74 d-cache-line-size = <64>; 75 d-cache-sets = <128>; 76 next-level-cache = <&l2_0>; 77 #cooling-cells = <2>; 78 }; 79 80 cpu1: cpu@100 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x100>; 84 enable-method = "psci"; 85 clock-frequency = <2000000000>; 86 capacity-dmips-mhz = <382>; 87 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 88 i-cache-size = <32768>; 89 i-cache-line-size = <64>; 90 i-cache-sets = <128>; 91 d-cache-size = <32768>; 92 d-cache-line-size = <64>; 93 d-cache-sets = <128>; 94 next-level-cache = <&l2_0>; 95 #cooling-cells = <2>; 96 }; 97 98 cpu2: cpu@200 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a55"; 101 reg = <0x200>; 102 enable-method = "psci"; 103 clock-frequency = <2000000000>; 104 capacity-dmips-mhz = <382>; 105 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 106 i-cache-size = <32768>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <128>; 109 d-cache-size = <32768>; 110 d-cache-line-size = <64>; 111 d-cache-sets = <128>; 112 next-level-cache = <&l2_0>; 113 #cooling-cells = <2>; 114 }; 115 116 cpu3: cpu@300 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a55"; 119 reg = <0x300>; 120 enable-method = "psci"; 121 clock-frequency = <2000000000>; 122 capacity-dmips-mhz = <382>; 123 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 124 i-cache-size = <32768>; 125 i-cache-line-size = <64>; 126 i-cache-sets = <128>; 127 d-cache-size = <32768>; 128 d-cache-line-size = <64>; 129 d-cache-sets = <128>; 130 next-level-cache = <&l2_0>; 131 #cooling-cells = <2>; 132 }; 133 134 cpu4: cpu@400 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a55"; 137 reg = <0x400>; 138 enable-method = "psci"; 139 clock-frequency = <2000000000>; 140 capacity-dmips-mhz = <382>; 141 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 142 i-cache-size = <32768>; 143 i-cache-line-size = <64>; 144 i-cache-sets = <128>; 145 d-cache-size = <32768>; 146 d-cache-line-size = <64>; 147 d-cache-sets = <128>; 148 next-level-cache = <&l2_0>; 149 #cooling-cells = <2>; 150 }; 151 152 cpu5: cpu@500 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a55"; 155 reg = <0x500>; 156 enable-method = "psci"; 157 clock-frequency = <2000000000>; 158 capacity-dmips-mhz = <382>; 159 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 160 i-cache-size = <32768>; 161 i-cache-line-size = <64>; 162 i-cache-sets = <128>; 163 d-cache-size = <32768>; 164 d-cache-line-size = <64>; 165 d-cache-sets = <128>; 166 next-level-cache = <&l2_0>; 167 #cooling-cells = <2>; 168 }; 169 170 cpu6: cpu@600 { 171 device_type = "cpu"; 172 compatible = "arm,cortex-a76"; 173 reg = <0x600>; 174 enable-method = "psci"; 175 clock-frequency = <2050000000>; 176 capacity-dmips-mhz = <1024>; 177 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 178 i-cache-size = <65536>; 179 i-cache-line-size = <64>; 180 i-cache-sets = <256>; 181 d-cache-size = <65536>; 182 d-cache-line-size = <64>; 183 d-cache-sets = <256>; 184 next-level-cache = <&l2_1>; 185 #cooling-cells = <2>; 186 }; 187 188 cpu7: cpu@700 { 189 device_type = "cpu"; 190 compatible = "arm,cortex-a76"; 191 reg = <0x700>; 192 enable-method = "psci"; 193 clock-frequency = <2050000000>; 194 capacity-dmips-mhz = <1024>; 195 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 196 i-cache-size = <65536>; 197 i-cache-line-size = <64>; 198 i-cache-sets = <256>; 199 d-cache-size = <65536>; 200 d-cache-line-size = <64>; 201 d-cache-sets = <256>; 202 next-level-cache = <&l2_1>; 203 #cooling-cells = <2>; 204 }; 205 206 idle-states { 207 entry-method = "psci"; 208 209 cpu_ret_l: cpu-retention-l { 210 compatible = "arm,idle-state"; 211 arm,psci-suspend-param = <0x00010001>; 212 local-timer-stop; 213 entry-latency-us = <50>; 214 exit-latency-us = <100>; 215 min-residency-us = <1600>; 216 }; 217 218 cpu_ret_b: cpu-retention-b { 219 compatible = "arm,idle-state"; 220 arm,psci-suspend-param = <0x00010001>; 221 local-timer-stop; 222 entry-latency-us = <50>; 223 exit-latency-us = <100>; 224 min-residency-us = <1400>; 225 }; 226 227 cpu_off_l: cpu-off-l { 228 compatible = "arm,idle-state"; 229 arm,psci-suspend-param = <0x01010001>; 230 local-timer-stop; 231 entry-latency-us = <100>; 232 exit-latency-us = <250>; 233 min-residency-us = <2100>; 234 }; 235 236 cpu_off_b: cpu-off-b { 237 compatible = "arm,idle-state"; 238 arm,psci-suspend-param = <0x01010001>; 239 local-timer-stop; 240 entry-latency-us = <100>; 241 exit-latency-us = <250>; 242 min-residency-us = <1900>; 243 }; 244 }; 245 246 l2_0: l2-cache0 { 247 compatible = "cache"; 248 cache-level = <2>; 249 cache-size = <131072>; 250 cache-line-size = <64>; 251 cache-sets = <512>; 252 next-level-cache = <&l3_0>; 253 }; 254 255 l2_1: l2-cache1 { 256 compatible = "cache"; 257 cache-level = <2>; 258 cache-size = <262144>; 259 cache-line-size = <64>; 260 cache-sets = <512>; 261 next-level-cache = <&l3_0>; 262 }; 263 264 l3_0: l3-cache { 265 compatible = "cache"; 266 cache-level = <3>; 267 cache-size = <1048576>; 268 cache-line-size = <64>; 269 cache-sets = <1024>; 270 cache-unified; 271 }; 272 }; 273 274 clk13m: fixed-factor-clock-13m { 275 compatible = "fixed-factor-clock"; 276 #clock-cells = <0>; 277 clocks = <&clk26m>; 278 clock-div = <2>; 279 clock-mult = <1>; 280 clock-output-names = "clk13m"; 281 }; 282 283 clk26m: oscillator-26m { 284 compatible = "fixed-clock"; 285 #clock-cells = <0>; 286 clock-frequency = <26000000>; 287 clock-output-names = "clk26m"; 288 }; 289 290 clk32k: oscillator-32k { 291 compatible = "fixed-clock"; 292 #clock-cells = <0>; 293 clock-frequency = <32768>; 294 clock-output-names = "clk32k"; 295 }; 296 297 pmu-a55 { 298 compatible = "arm,cortex-a55-pmu"; 299 interrupt-parent = <&gic>; 300 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 301 }; 302 303 pmu-a76 { 304 compatible = "arm,cortex-a76-pmu"; 305 interrupt-parent = <&gic>; 306 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 307 }; 308 309 psci { 310 compatible = "arm,psci-1.0"; 311 method = "smc"; 312 }; 313 314 timer { 315 compatible = "arm,armv8-timer"; 316 interrupt-parent = <&gic>; 317 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 318 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 319 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 320 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 321 }; 322 323 soc { 324 #address-cells = <2>; 325 #size-cells = <2>; 326 compatible = "simple-bus"; 327 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 328 ranges; 329 330 gic: interrupt-controller@c000000 { 331 compatible = "arm,gic-v3"; 332 #interrupt-cells = <4>; 333 #redistributor-regions = <1>; 334 interrupt-parent = <&gic>; 335 interrupt-controller; 336 reg = <0 0x0c000000 0 0x40000>, 337 <0 0x0c040000 0 0x200000>; 338 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 339 340 ppi-partitions { 341 ppi_cluster0: interrupt-partition-0 { 342 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 343 }; 344 345 ppi_cluster1: interrupt-partition-1 { 346 affinity = <&cpu6 &cpu7>; 347 }; 348 }; 349 }; 350 351 mcusys: syscon@c53a000 { 352 compatible = "mediatek,mt8186-mcusys", "syscon"; 353 reg = <0 0xc53a000 0 0x1000>; 354 #clock-cells = <1>; 355 }; 356 357 topckgen: syscon@10000000 { 358 compatible = "mediatek,mt8186-topckgen", "syscon"; 359 reg = <0 0x10000000 0 0x1000>; 360 #clock-cells = <1>; 361 }; 362 363 infracfg_ao: syscon@10001000 { 364 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 365 reg = <0 0x10001000 0 0x1000>; 366 #clock-cells = <1>; 367 #reset-cells = <1>; 368 }; 369 370 pericfg: syscon@10003000 { 371 compatible = "mediatek,mt8186-pericfg", "syscon"; 372 reg = <0 0x10003000 0 0x1000>; 373 }; 374 375 pio: pinctrl@10005000 { 376 compatible = "mediatek,mt8186-pinctrl"; 377 reg = <0 0x10005000 0 0x1000>, 378 <0 0x10002000 0 0x0200>, 379 <0 0x10002200 0 0x0200>, 380 <0 0x10002400 0 0x0200>, 381 <0 0x10002600 0 0x0200>, 382 <0 0x10002a00 0 0x0200>, 383 <0 0x10002c00 0 0x0200>, 384 <0 0x1000b000 0 0x1000>; 385 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 386 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 387 gpio-controller; 388 #gpio-cells = <2>; 389 gpio-ranges = <&pio 0 0 185>; 390 interrupt-controller; 391 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 392 #interrupt-cells = <2>; 393 }; 394 395 scpsys: syscon@10006000 { 396 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 397 reg = <0 0x10006000 0 0x1000>; 398 399 /* System Power Manager */ 400 spm: power-controller { 401 compatible = "mediatek,mt8186-power-controller"; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 #power-domain-cells = <1>; 405 406 /* power domain of the SoC */ 407 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 408 reg = <MT8186_POWER_DOMAIN_MFG0>; 409 clocks = <&topckgen CLK_TOP_MFG>; 410 clock-names = "mfg00"; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 #power-domain-cells = <1>; 414 415 power-domain@MT8186_POWER_DOMAIN_MFG1 { 416 reg = <MT8186_POWER_DOMAIN_MFG1>; 417 mediatek,infracfg = <&infracfg_ao>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 #power-domain-cells = <1>; 421 422 power-domain@MT8186_POWER_DOMAIN_MFG2 { 423 reg = <MT8186_POWER_DOMAIN_MFG2>; 424 #power-domain-cells = <0>; 425 }; 426 427 power-domain@MT8186_POWER_DOMAIN_MFG3 { 428 reg = <MT8186_POWER_DOMAIN_MFG3>; 429 #power-domain-cells = <0>; 430 }; 431 }; 432 }; 433 434 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 435 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 436 clocks = <&topckgen CLK_TOP_SENINF>, 437 <&topckgen CLK_TOP_SENINF1>; 438 clock-names = "csirx_top0", "csirx_top1"; 439 #power-domain-cells = <0>; 440 }; 441 442 power-domain@MT8186_POWER_DOMAIN_SSUSB { 443 reg = <MT8186_POWER_DOMAIN_SSUSB>; 444 #power-domain-cells = <0>; 445 }; 446 447 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 448 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 449 #power-domain-cells = <0>; 450 }; 451 452 power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 453 reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 454 clocks = <&topckgen CLK_TOP_AUDIODSP>, 455 <&topckgen CLK_TOP_ADSP_BUS>; 456 clock-names = "audioadsp", "adsp_bus"; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 #power-domain-cells = <1>; 460 461 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 462 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 #power-domain-cells = <1>; 466 467 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 468 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 469 mediatek,infracfg = <&infracfg_ao>; 470 #power-domain-cells = <0>; 471 }; 472 }; 473 }; 474 475 power-domain@MT8186_POWER_DOMAIN_CONN_ON { 476 reg = <MT8186_POWER_DOMAIN_CONN_ON>; 477 mediatek,infracfg = <&infracfg_ao>; 478 #power-domain-cells = <0>; 479 }; 480 481 power-domain@MT8186_POWER_DOMAIN_DIS { 482 reg = <MT8186_POWER_DOMAIN_DIS>; 483 clocks = <&topckgen CLK_TOP_DISP>, 484 <&topckgen CLK_TOP_MDP>, 485 <&mmsys CLK_MM_SMI_INFRA>, 486 <&mmsys CLK_MM_SMI_COMMON>, 487 <&mmsys CLK_MM_SMI_GALS>, 488 <&mmsys CLK_MM_SMI_IOMMU>; 489 clock-names = "disp", "mdp", "smi_infra", "smi_common", 490 "smi_gals", "smi_iommu"; 491 mediatek,infracfg = <&infracfg_ao>; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 #power-domain-cells = <1>; 495 496 power-domain@MT8186_POWER_DOMAIN_VDEC { 497 reg = <MT8186_POWER_DOMAIN_VDEC>; 498 clocks = <&topckgen CLK_TOP_VDEC>, 499 <&vdecsys CLK_VDEC_LARB1_CKEN>; 500 clock-names = "vdec0", "larb"; 501 mediatek,infracfg = <&infracfg_ao>; 502 #power-domain-cells = <0>; 503 }; 504 505 power-domain@MT8186_POWER_DOMAIN_CAM { 506 reg = <MT8186_POWER_DOMAIN_CAM>; 507 clocks = <&topckgen CLK_TOP_CAM>, 508 <&topckgen CLK_TOP_SENINF>, 509 <&topckgen CLK_TOP_SENINF1>, 510 <&topckgen CLK_TOP_SENINF2>, 511 <&topckgen CLK_TOP_SENINF3>, 512 <&topckgen CLK_TOP_CAMTM>, 513 <&camsys CLK_CAM2MM_GALS>; 514 clock-names = "cam-top", "cam0", "cam1", "cam2", 515 "cam3", "cam-tm", "gals"; 516 mediatek,infracfg = <&infracfg_ao>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 #power-domain-cells = <1>; 520 521 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 522 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 523 #power-domain-cells = <0>; 524 }; 525 526 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 527 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 528 #power-domain-cells = <0>; 529 }; 530 }; 531 532 power-domain@MT8186_POWER_DOMAIN_IMG { 533 reg = <MT8186_POWER_DOMAIN_IMG>; 534 clocks = <&topckgen CLK_TOP_IMG1>, 535 <&imgsys1 CLK_IMG1_GALS_IMG1>; 536 clock-names = "img-top", "gals"; 537 mediatek,infracfg = <&infracfg_ao>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 #power-domain-cells = <1>; 541 542 power-domain@MT8186_POWER_DOMAIN_IMG2 { 543 reg = <MT8186_POWER_DOMAIN_IMG2>; 544 #power-domain-cells = <0>; 545 }; 546 }; 547 548 power-domain@MT8186_POWER_DOMAIN_IPE { 549 reg = <MT8186_POWER_DOMAIN_IPE>; 550 clocks = <&topckgen CLK_TOP_IPE>, 551 <&ipesys CLK_IPE_LARB19>, 552 <&ipesys CLK_IPE_LARB20>, 553 <&ipesys CLK_IPE_SMI_SUBCOM>, 554 <&ipesys CLK_IPE_GALS_IPE>; 555 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", 556 "ipe-smi", "ipe-gals"; 557 mediatek,infracfg = <&infracfg_ao>; 558 #power-domain-cells = <0>; 559 }; 560 561 power-domain@MT8186_POWER_DOMAIN_VENC { 562 reg = <MT8186_POWER_DOMAIN_VENC>; 563 clocks = <&topckgen CLK_TOP_VENC>, 564 <&vencsys CLK_VENC_CKE1_VENC>; 565 clock-names = "venc0", "larb"; 566 mediatek,infracfg = <&infracfg_ao>; 567 #power-domain-cells = <0>; 568 }; 569 570 power-domain@MT8186_POWER_DOMAIN_WPE { 571 reg = <MT8186_POWER_DOMAIN_WPE>; 572 clocks = <&topckgen CLK_TOP_WPE>, 573 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 574 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 575 clock-names = "wpe0", "larb-ck", "larb-pclk"; 576 mediatek,infracfg = <&infracfg_ao>; 577 #power-domain-cells = <0>; 578 }; 579 }; 580 }; 581 }; 582 583 watchdog: watchdog@10007000 { 584 compatible = "mediatek,mt8186-wdt"; 585 mediatek,disable-extrst; 586 reg = <0 0x10007000 0 0x1000>; 587 #reset-cells = <1>; 588 }; 589 590 apmixedsys: syscon@1000c000 { 591 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 592 reg = <0 0x1000c000 0 0x1000>; 593 #clock-cells = <1>; 594 }; 595 596 pwrap: pwrap@1000d000 { 597 compatible = "mediatek,mt8186-pwrap", "syscon"; 598 reg = <0 0x1000d000 0 0x1000>; 599 reg-names = "pwrap"; 600 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 601 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 602 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 603 clock-names = "spi", "wrap"; 604 }; 605 606 spmi: spmi@10015000 { 607 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; 608 reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; 609 reg-names = "pmif", "spmimst"; 610 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 611 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 612 <&topckgen CLK_TOP_SPMI_MST>; 613 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 614 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; 615 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 616 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>, 617 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>; 618 status = "disabled"; 619 }; 620 621 systimer: timer@10017000 { 622 compatible = "mediatek,mt8186-timer", 623 "mediatek,mt6765-timer"; 624 reg = <0 0x10017000 0 0x1000>; 625 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 626 clocks = <&clk13m>; 627 }; 628 629 scp: scp@10500000 { 630 compatible = "mediatek,mt8186-scp"; 631 reg = <0 0x10500000 0 0x40000>, 632 <0 0x105c0000 0 0x19080>; 633 reg-names = "sram", "cfg"; 634 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 635 }; 636 637 adsp: adsp@10680000 { 638 compatible = "mediatek,mt8186-dsp"; 639 reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, 640 <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; 641 reg-names = "cfg", "sram", "sec", "bus"; 642 clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; 643 clock-names = "audiodsp", "adsp_bus"; 644 assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, 645 <&topckgen CLK_TOP_ADSP_BUS>; 646 assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; 647 mbox-names = "rx", "tx"; 648 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 649 power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; 650 status = "disabled"; 651 }; 652 653 adsp_mailbox0: mailbox@10686000 { 654 compatible = "mediatek,mt8186-adsp-mbox"; 655 #mbox-cells = <0>; 656 reg = <0 0x10686100 0 0x1000>; 657 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 658 }; 659 660 adsp_mailbox1: mailbox@10687000 { 661 compatible = "mediatek,mt8186-adsp-mbox"; 662 #mbox-cells = <0>; 663 reg = <0 0x10687100 0 0x1000>; 664 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>; 665 }; 666 667 nor_flash: spi@11000000 { 668 compatible = "mediatek,mt8186-nor"; 669 reg = <0 0x11000000 0 0x1000>; 670 clocks = <&topckgen CLK_TOP_SPINOR>, 671 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 672 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 673 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 674 clock-names = "spi", "sf", "axi", "axi_s"; 675 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 676 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 677 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 678 status = "disabled"; 679 }; 680 681 auxadc: adc@11001000 { 682 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 683 reg = <0 0x11001000 0 0x1000>; 684 #io-channel-cells = <1>; 685 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 686 clock-names = "main"; 687 }; 688 689 uart0: serial@11002000 { 690 compatible = "mediatek,mt8186-uart", 691 "mediatek,mt6577-uart"; 692 reg = <0 0x11002000 0 0x1000>; 693 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 694 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 695 clock-names = "baud", "bus"; 696 status = "disabled"; 697 }; 698 699 uart1: serial@11003000 { 700 compatible = "mediatek,mt8186-uart", 701 "mediatek,mt6577-uart"; 702 reg = <0 0x11003000 0 0x1000>; 703 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 704 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 705 clock-names = "baud", "bus"; 706 status = "disabled"; 707 }; 708 709 i2c0: i2c@11007000 { 710 compatible = "mediatek,mt8186-i2c"; 711 reg = <0 0x11007000 0 0x1000>, 712 <0 0x10200100 0 0x100>; 713 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 714 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 715 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 716 clock-names = "main", "dma"; 717 clock-div = <1>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 status = "disabled"; 721 }; 722 723 i2c1: i2c@11008000 { 724 compatible = "mediatek,mt8186-i2c"; 725 reg = <0 0x11008000 0 0x1000>, 726 <0 0x10200200 0 0x100>; 727 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 728 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 729 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 730 clock-names = "main", "dma"; 731 clock-div = <1>; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 status = "disabled"; 735 }; 736 737 i2c2: i2c@11009000 { 738 compatible = "mediatek,mt8186-i2c"; 739 reg = <0 0x11009000 0 0x1000>, 740 <0 0x10200300 0 0x180>; 741 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 742 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 743 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 744 clock-names = "main", "dma"; 745 clock-div = <1>; 746 #address-cells = <1>; 747 #size-cells = <0>; 748 status = "disabled"; 749 }; 750 751 i2c3: i2c@1100f000 { 752 compatible = "mediatek,mt8186-i2c"; 753 reg = <0 0x1100f000 0 0x1000>, 754 <0 0x10200480 0 0x100>; 755 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 756 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 757 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 758 clock-names = "main", "dma"; 759 clock-div = <1>; 760 #address-cells = <1>; 761 #size-cells = <0>; 762 status = "disabled"; 763 }; 764 765 i2c4: i2c@11011000 { 766 compatible = "mediatek,mt8186-i2c"; 767 reg = <0 0x11011000 0 0x1000>, 768 <0 0x10200580 0 0x180>; 769 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 770 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 771 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 772 clock-names = "main", "dma"; 773 clock-div = <1>; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 status = "disabled"; 777 }; 778 779 i2c5: i2c@11016000 { 780 compatible = "mediatek,mt8186-i2c"; 781 reg = <0 0x11016000 0 0x1000>, 782 <0 0x10200700 0 0x100>; 783 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 784 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 785 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 786 clock-names = "main", "dma"; 787 clock-div = <1>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 status = "disabled"; 791 }; 792 793 i2c6: i2c@1100d000 { 794 compatible = "mediatek,mt8186-i2c"; 795 reg = <0 0x1100d000 0 0x1000>, 796 <0 0x10200800 0 0x100>; 797 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 798 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 799 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 800 clock-names = "main", "dma"; 801 clock-div = <1>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 status = "disabled"; 805 }; 806 807 i2c7: i2c@11004000 { 808 compatible = "mediatek,mt8186-i2c"; 809 reg = <0 0x11004000 0 0x1000>, 810 <0 0x10200900 0 0x180>; 811 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 812 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 813 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 814 clock-names = "main", "dma"; 815 clock-div = <1>; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 status = "disabled"; 819 }; 820 821 i2c8: i2c@11005000 { 822 compatible = "mediatek,mt8186-i2c"; 823 reg = <0 0x11005000 0 0x1000>, 824 <0 0x10200A80 0 0x180>; 825 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 826 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 827 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 828 clock-names = "main", "dma"; 829 clock-div = <1>; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 status = "disabled"; 833 }; 834 835 spi0: spi@1100a000 { 836 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 reg = <0 0x1100a000 0 0x1000>; 840 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 841 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 842 <&topckgen CLK_TOP_SPI>, 843 <&infracfg_ao CLK_INFRA_AO_SPI0>; 844 clock-names = "parent-clk", "sel-clk", "spi-clk"; 845 status = "disabled"; 846 }; 847 848 pwm0: pwm@1100e000 { 849 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 850 reg = <0 0x1100e000 0 0x1000>; 851 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 852 #pwm-cells = <2>; 853 clocks = <&topckgen CLK_TOP_DISP_PWM>, 854 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 855 clock-names = "main", "mm"; 856 status = "disabled"; 857 }; 858 859 spi1: spi@11010000 { 860 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 861 #address-cells = <1>; 862 #size-cells = <0>; 863 reg = <0 0x11010000 0 0x1000>; 864 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 865 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 866 <&topckgen CLK_TOP_SPI>, 867 <&infracfg_ao CLK_INFRA_AO_SPI1>; 868 clock-names = "parent-clk", "sel-clk", "spi-clk"; 869 status = "disabled"; 870 }; 871 872 spi2: spi@11012000 { 873 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 reg = <0 0x11012000 0 0x1000>; 877 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 878 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 879 <&topckgen CLK_TOP_SPI>, 880 <&infracfg_ao CLK_INFRA_AO_SPI2>; 881 clock-names = "parent-clk", "sel-clk", "spi-clk"; 882 status = "disabled"; 883 }; 884 885 spi3: spi@11013000 { 886 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 reg = <0 0x11013000 0 0x1000>; 890 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 891 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 892 <&topckgen CLK_TOP_SPI>, 893 <&infracfg_ao CLK_INFRA_AO_SPI3>; 894 clock-names = "parent-clk", "sel-clk", "spi-clk"; 895 status = "disabled"; 896 }; 897 898 spi4: spi@11014000 { 899 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 reg = <0 0x11014000 0 0x1000>; 903 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 904 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 905 <&topckgen CLK_TOP_SPI>, 906 <&infracfg_ao CLK_INFRA_AO_SPI4>; 907 clock-names = "parent-clk", "sel-clk", "spi-clk"; 908 status = "disabled"; 909 }; 910 911 spi5: spi@11015000 { 912 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 reg = <0 0x11015000 0 0x1000>; 916 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 917 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 918 <&topckgen CLK_TOP_SPI>, 919 <&infracfg_ao CLK_INFRA_AO_SPI5>; 920 clock-names = "parent-clk", "sel-clk", "spi-clk"; 921 status = "disabled"; 922 }; 923 924 imp_iic_wrap: clock-controller@11017000 { 925 compatible = "mediatek,mt8186-imp_iic_wrap"; 926 reg = <0 0x11017000 0 0x1000>; 927 #clock-cells = <1>; 928 }; 929 930 uart2: serial@11018000 { 931 compatible = "mediatek,mt8186-uart", 932 "mediatek,mt6577-uart"; 933 reg = <0 0x11018000 0 0x1000>; 934 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 935 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 936 clock-names = "baud", "bus"; 937 status = "disabled"; 938 }; 939 940 i2c9: i2c@11019000 { 941 compatible = "mediatek,mt8186-i2c"; 942 reg = <0 0x11019000 0 0x1000>, 943 <0 0x10200c00 0 0x180>; 944 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 945 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 946 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 947 clock-names = "main", "dma"; 948 clock-div = <1>; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 status = "disabled"; 952 }; 953 954 afe: audio-controller@11210000 { 955 compatible = "mediatek,mt8186-sound"; 956 reg = <0 0x11210000 0 0x2000>; 957 clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, 958 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, 959 <&topckgen CLK_TOP_AUDIO>, 960 <&topckgen CLK_TOP_AUD_INTBUS>, 961 <&topckgen CLK_TOP_MAINPLL_D2_D4>, 962 <&topckgen CLK_TOP_AUD_1>, 963 <&apmixedsys CLK_APMIXED_APLL1>, 964 <&topckgen CLK_TOP_AUD_2>, 965 <&apmixedsys CLK_APMIXED_APLL2>, 966 <&topckgen CLK_TOP_AUD_ENGEN1>, 967 <&topckgen CLK_TOP_APLL1_D8>, 968 <&topckgen CLK_TOP_AUD_ENGEN2>, 969 <&topckgen CLK_TOP_APLL2_D8>, 970 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, 971 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, 972 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, 973 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, 974 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, 975 <&topckgen CLK_TOP_APLL12_CK_DIV0>, 976 <&topckgen CLK_TOP_APLL12_CK_DIV1>, 977 <&topckgen CLK_TOP_APLL12_CK_DIV2>, 978 <&topckgen CLK_TOP_APLL12_CK_DIV4>, 979 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, 980 <&topckgen CLK_TOP_AUDIO_H>, 981 <&clk26m>; 982 clock-names = "aud_infra_clk", 983 "mtkaif_26m_clk", 984 "top_mux_audio", 985 "top_mux_audio_int", 986 "top_mainpll_d2_d4", 987 "top_mux_aud_1", 988 "top_apll1_ck", 989 "top_mux_aud_2", 990 "top_apll2_ck", 991 "top_mux_aud_eng1", 992 "top_apll1_d8", 993 "top_mux_aud_eng2", 994 "top_apll2_d8", 995 "top_i2s0_m_sel", 996 "top_i2s1_m_sel", 997 "top_i2s2_m_sel", 998 "top_i2s4_m_sel", 999 "top_tdm_m_sel", 1000 "top_apll12_div0", 1001 "top_apll12_div1", 1002 "top_apll12_div2", 1003 "top_apll12_div4", 1004 "top_apll12_div_tdm", 1005 "top_mux_audio_h", 1006 "top_clk26m_clk"; 1007 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1008 mediatek,apmixedsys = <&apmixedsys>; 1009 mediatek,infracfg = <&infracfg_ao>; 1010 mediatek,topckgen = <&topckgen>; 1011 resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; 1012 reset-names = "audiosys"; 1013 status = "disabled"; 1014 }; 1015 1016 ssusb0: usb@11201000 { 1017 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1018 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1019 reg-names = "mac", "ippc"; 1020 clocks = <&topckgen CLK_TOP_USB_TOP>, 1021 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1022 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1023 <&infracfg_ao CLK_INFRA_AO_ICUSB>; 1024 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1025 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>; 1026 phys = <&u2port0 PHY_TYPE_USB2>; 1027 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; 1028 #address-cells = <2>; 1029 #size-cells = <2>; 1030 ranges; 1031 status = "disabled"; 1032 1033 usb_host0: usb@11200000 { 1034 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1035 reg = <0 0x11200000 0 0x1000>; 1036 reg-names = "mac"; 1037 clocks = <&topckgen CLK_TOP_USB_TOP>, 1038 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1039 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1040 <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1041 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1042 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1043 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 1044 mediatek,syscon-wakeup = <&pericfg 0x420 2>; 1045 wakeup-source; 1046 status = "disabled"; 1047 }; 1048 }; 1049 1050 mmc0: mmc@11230000 { 1051 compatible = "mediatek,mt8186-mmc", 1052 "mediatek,mt8183-mmc"; 1053 reg = <0 0x11230000 0 0x10000>, 1054 <0 0x11cd0000 0 0x1000>; 1055 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1056 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1057 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1058 <&infracfg_ao CLK_INFRA_AO_MSDCFDE>; 1059 clock-names = "source", "hclk", "source_cg", "crypto"; 1060 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 1061 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 1062 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 1063 status = "disabled"; 1064 }; 1065 1066 mmc1: mmc@11240000 { 1067 compatible = "mediatek,mt8186-mmc", 1068 "mediatek,mt8183-mmc"; 1069 reg = <0 0x11240000 0 0x1000>, 1070 <0 0x11c90000 0 0x1000>; 1071 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1072 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1073 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1074 clock-names = "source", "hclk", "source_cg"; 1075 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 1076 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1077 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1078 status = "disabled"; 1079 }; 1080 1081 ssusb1: usb@11281000 { 1082 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1083 reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; 1084 reg-names = "mac", "ippc"; 1085 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1086 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1087 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1088 <&clk26m>; 1089 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1090 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 1091 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1092 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; 1093 #address-cells = <2>; 1094 #size-cells = <2>; 1095 ranges; 1096 status = "disabled"; 1097 1098 usb_host1: usb@11280000 { 1099 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1100 reg = <0 0x11280000 0 0x1000>; 1101 reg-names = "mac"; 1102 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1103 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1104 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1105 <&clk26m>, 1106 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1107 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; 1108 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1109 mediatek,syscon-wakeup = <&pericfg 0x424 2>; 1110 wakeup-source; 1111 status = "disabled"; 1112 }; 1113 }; 1114 1115 u3phy0: t-phy@11c80000 { 1116 compatible = "mediatek,mt8186-tphy", 1117 "mediatek,generic-tphy-v2"; 1118 #address-cells = <1>; 1119 #size-cells = <1>; 1120 ranges = <0x0 0x0 0x11c80000 0x1000>; 1121 status = "disabled"; 1122 1123 u2port1: usb-phy@0 { 1124 reg = <0x0 0x700>; 1125 clocks = <&clk26m>; 1126 clock-names = "ref"; 1127 #phy-cells = <1>; 1128 }; 1129 1130 u3port1: usb-phy@700 { 1131 reg = <0x700 0x900>; 1132 clocks = <&clk26m>; 1133 clock-names = "ref"; 1134 #phy-cells = <1>; 1135 }; 1136 }; 1137 1138 u3phy1: t-phy@11ca0000 { 1139 compatible = "mediatek,mt8186-tphy", 1140 "mediatek,generic-tphy-v2"; 1141 #address-cells = <1>; 1142 #size-cells = <1>; 1143 ranges = <0x0 0x0 0x11ca0000 0x1000>; 1144 status = "disabled"; 1145 1146 u2port0: usb-phy@0 { 1147 reg = <0x0 0x700>; 1148 clocks = <&clk26m>; 1149 clock-names = "ref"; 1150 #phy-cells = <1>; 1151 mediatek,discth = <0x8>; 1152 }; 1153 }; 1154 1155 efuse: efuse@11cb0000 { 1156 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 1157 reg = <0 0x11cb0000 0 0x1000>; 1158 #address-cells = <1>; 1159 #size-cells = <1>; 1160 }; 1161 1162 mipi_tx0: dsi-phy@11cc0000 { 1163 compatible = "mediatek,mt8183-mipi-tx"; 1164 reg = <0 0x11cc0000 0 0x1000>; 1165 clocks = <&clk26m>; 1166 #clock-cells = <0>; 1167 #phy-cells = <0>; 1168 clock-output-names = "mipi_tx0_pll"; 1169 status = "disabled"; 1170 }; 1171 1172 mfgsys: clock-controller@13000000 { 1173 compatible = "mediatek,mt8186-mfgsys"; 1174 reg = <0 0x13000000 0 0x1000>; 1175 #clock-cells = <1>; 1176 }; 1177 1178 gpu: gpu@13040000 { 1179 compatible = "mediatek,mt8186-mali", 1180 "arm,mali-bifrost"; 1181 reg = <0 0x13040000 0 0x4000>; 1182 1183 clocks = <&mfgsys CLK_MFG_BG3D>; 1184 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>, 1185 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>, 1186 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 1187 interrupt-names = "job", "mmu", "gpu"; 1188 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>, 1189 <&spm MT8186_POWER_DOMAIN_MFG3>; 1190 power-domain-names = "core0", "core1"; 1191 #cooling-cells = <2>; 1192 status = "disabled"; 1193 }; 1194 1195 mmsys: syscon@14000000 { 1196 compatible = "mediatek,mt8186-mmsys", "syscon"; 1197 reg = <0 0x14000000 0 0x1000>; 1198 #clock-cells = <1>; 1199 #reset-cells = <1>; 1200 }; 1201 1202 smi_common: smi@14002000 { 1203 compatible = "mediatek,mt8186-smi-common"; 1204 reg = <0 0x14002000 0 0x1000>; 1205 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 1206 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 1207 clock-names = "apb", "smi", "gals0", "gals1"; 1208 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1209 }; 1210 1211 larb0: smi@14003000 { 1212 compatible = "mediatek,mt8186-smi-larb"; 1213 reg = <0 0x14003000 0 0x1000>; 1214 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1215 <&mmsys CLK_MM_SMI_COMMON>; 1216 clock-names = "apb", "smi"; 1217 mediatek,larb-id = <0>; 1218 mediatek,smi = <&smi_common>; 1219 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1220 }; 1221 1222 larb1: smi@14004000 { 1223 compatible = "mediatek,mt8186-smi-larb"; 1224 reg = <0 0x14004000 0 0x1000>; 1225 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1226 <&mmsys CLK_MM_SMI_COMMON>; 1227 clock-names = "apb", "smi"; 1228 mediatek,larb-id = <1>; 1229 mediatek,smi = <&smi_common>; 1230 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1231 }; 1232 1233 dpi: dpi@1400a000 { 1234 compatible = "mediatek,mt8186-dpi"; 1235 reg = <0 0x1400a000 0 0x1000>; 1236 clocks = <&topckgen CLK_TOP_DPI>, 1237 <&mmsys CLK_MM_DISP_DPI>, 1238 <&apmixedsys CLK_APMIXED_TVDPLL>; 1239 clock-names = "pixel", "engine", "pll"; 1240 assigned-clocks = <&topckgen CLK_TOP_DPI>; 1241 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; 1242 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; 1243 status = "disabled"; 1244 1245 port { 1246 dpi_out: endpoint { }; 1247 }; 1248 }; 1249 1250 dsi0: dsi@14013000 { 1251 compatible = "mediatek,mt8186-dsi"; 1252 reg = <0 0x14013000 0 0x1000>; 1253 clocks = <&mmsys CLK_MM_DSI0>, 1254 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 1255 <&mipi_tx0>; 1256 clock-names = "engine", "digital", "hs"; 1257 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 1258 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1259 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 1260 phys = <&mipi_tx0>; 1261 phy-names = "dphy"; 1262 status = "disabled"; 1263 1264 port { 1265 dsi_out: endpoint { }; 1266 }; 1267 }; 1268 1269 iommu_mm: iommu@14016000 { 1270 compatible = "mediatek,mt8186-iommu-mm"; 1271 reg = <0 0x14016000 0 0x1000>; 1272 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1273 clock-names = "bclk"; 1274 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1275 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1276 &larb7 &larb8 &larb9 &larb11 1277 &larb13 &larb14 &larb16 &larb17 1278 &larb19 &larb20>; 1279 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1280 #iommu-cells = <1>; 1281 }; 1282 1283 wpesys: clock-controller@14020000 { 1284 compatible = "mediatek,mt8186-wpesys"; 1285 reg = <0 0x14020000 0 0x1000>; 1286 #clock-cells = <1>; 1287 }; 1288 1289 larb8: smi@14023000 { 1290 compatible = "mediatek,mt8186-smi-larb"; 1291 reg = <0 0x14023000 0 0x1000>; 1292 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1293 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1294 clock-names = "apb", "smi"; 1295 mediatek,larb-id = <8>; 1296 mediatek,smi = <&smi_common>; 1297 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1298 }; 1299 1300 imgsys1: clock-controller@15020000 { 1301 compatible = "mediatek,mt8186-imgsys1"; 1302 reg = <0 0x15020000 0 0x1000>; 1303 #clock-cells = <1>; 1304 }; 1305 1306 larb9: smi@1502e000 { 1307 compatible = "mediatek,mt8186-smi-larb"; 1308 reg = <0 0x1502e000 0 0x1000>; 1309 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1310 <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1311 clock-names = "apb", "smi"; 1312 mediatek,larb-id = <9>; 1313 mediatek,smi = <&smi_common>; 1314 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 1315 }; 1316 1317 imgsys2: clock-controller@15820000 { 1318 compatible = "mediatek,mt8186-imgsys2"; 1319 reg = <0 0x15820000 0 0x1000>; 1320 #clock-cells = <1>; 1321 }; 1322 1323 larb11: smi@1582e000 { 1324 compatible = "mediatek,mt8186-smi-larb"; 1325 reg = <0 0x1582e000 0 0x1000>; 1326 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 1327 <&imgsys2 CLK_IMG2_LARB9_IMG2>; 1328 clock-names = "apb", "smi"; 1329 mediatek,larb-id = <11>; 1330 mediatek,smi = <&smi_common>; 1331 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 1332 }; 1333 1334 larb4: smi@1602e000 { 1335 compatible = "mediatek,mt8186-smi-larb"; 1336 reg = <0 0x1602e000 0 0x1000>; 1337 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 1338 <&vdecsys CLK_VDEC_LARB1_CKEN>; 1339 clock-names = "apb", "smi"; 1340 mediatek,larb-id = <4>; 1341 mediatek,smi = <&smi_common>; 1342 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 1343 }; 1344 1345 vdecsys: clock-controller@1602f000 { 1346 compatible = "mediatek,mt8186-vdecsys"; 1347 reg = <0 0x1602f000 0 0x1000>; 1348 #clock-cells = <1>; 1349 }; 1350 1351 vencsys: clock-controller@17000000 { 1352 compatible = "mediatek,mt8186-vencsys"; 1353 reg = <0 0x17000000 0 0x1000>; 1354 #clock-cells = <1>; 1355 }; 1356 1357 larb7: smi@17010000 { 1358 compatible = "mediatek,mt8186-smi-larb"; 1359 reg = <0 0x17010000 0 0x1000>; 1360 clocks = <&vencsys CLK_VENC_CKE1_VENC>, 1361 <&vencsys CLK_VENC_CKE1_VENC>; 1362 clock-names = "apb", "smi"; 1363 mediatek,larb-id = <7>; 1364 mediatek,smi = <&smi_common>; 1365 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 1366 }; 1367 1368 camsys: clock-controller@1a000000 { 1369 compatible = "mediatek,mt8186-camsys"; 1370 reg = <0 0x1a000000 0 0x1000>; 1371 #clock-cells = <1>; 1372 }; 1373 1374 larb13: smi@1a001000 { 1375 compatible = "mediatek,mt8186-smi-larb"; 1376 reg = <0 0x1a001000 0 0x1000>; 1377 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 1378 clock-names = "apb", "smi"; 1379 mediatek,larb-id = <13>; 1380 mediatek,smi = <&smi_common>; 1381 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1382 }; 1383 1384 larb14: smi@1a002000 { 1385 compatible = "mediatek,mt8186-smi-larb"; 1386 reg = <0 0x1a002000 0 0x1000>; 1387 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 1388 clock-names = "apb", "smi"; 1389 mediatek,larb-id = <14>; 1390 mediatek,smi = <&smi_common>; 1391 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1392 }; 1393 1394 larb16: smi@1a00f000 { 1395 compatible = "mediatek,mt8186-smi-larb"; 1396 reg = <0 0x1a00f000 0 0x1000>; 1397 clocks = <&camsys CLK_CAM_LARB14>, 1398 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 1399 clock-names = "apb", "smi"; 1400 mediatek,larb-id = <16>; 1401 mediatek,smi = <&smi_common>; 1402 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 1403 }; 1404 1405 larb17: smi@1a010000 { 1406 compatible = "mediatek,mt8186-smi-larb"; 1407 reg = <0 0x1a010000 0 0x1000>; 1408 clocks = <&camsys CLK_CAM_LARB13>, 1409 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 1410 clock-names = "apb", "smi"; 1411 mediatek,larb-id = <17>; 1412 mediatek,smi = <&smi_common>; 1413 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 1414 }; 1415 1416 camsys_rawa: clock-controller@1a04f000 { 1417 compatible = "mediatek,mt8186-camsys_rawa"; 1418 reg = <0 0x1a04f000 0 0x1000>; 1419 #clock-cells = <1>; 1420 }; 1421 1422 camsys_rawb: clock-controller@1a06f000 { 1423 compatible = "mediatek,mt8186-camsys_rawb"; 1424 reg = <0 0x1a06f000 0 0x1000>; 1425 #clock-cells = <1>; 1426 }; 1427 1428 mdpsys: clock-controller@1b000000 { 1429 compatible = "mediatek,mt8186-mdpsys"; 1430 reg = <0 0x1b000000 0 0x1000>; 1431 #clock-cells = <1>; 1432 }; 1433 1434 larb2: smi@1b002000 { 1435 compatible = "mediatek,mt8186-smi-larb"; 1436 reg = <0 0x1b002000 0 0x1000>; 1437 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 1438 clock-names = "apb", "smi"; 1439 mediatek,larb-id = <2>; 1440 mediatek,smi = <&smi_common>; 1441 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1442 }; 1443 1444 ipesys: clock-controller@1c000000 { 1445 compatible = "mediatek,mt8186-ipesys"; 1446 reg = <0 0x1c000000 0 0x1000>; 1447 #clock-cells = <1>; 1448 }; 1449 1450 larb20: smi@1c00f000 { 1451 compatible = "mediatek,mt8186-smi-larb"; 1452 reg = <0 0x1c00f000 0 0x1000>; 1453 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 1454 clock-names = "apb", "smi"; 1455 mediatek,larb-id = <20>; 1456 mediatek,smi = <&smi_common>; 1457 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1458 }; 1459 1460 larb19: smi@1c10f000 { 1461 compatible = "mediatek,mt8186-smi-larb"; 1462 reg = <0 0x1c10f000 0 0x1000>; 1463 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 1464 clock-names = "apb", "smi"; 1465 mediatek,larb-id = <19>; 1466 mediatek,smi = <&smi_common>; 1467 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1468 }; 1469 }; 1470}; 1471