1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/gce/mt8186-gce.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/memory/mt8186-memory-port.h> 12#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 13#include <dt-bindings/power/mt8186-power.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/reset/mt8186-resets.h> 16 17/ { 18 compatible = "mediatek,mt8186"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu-map { 28 cluster0 { 29 core0 { 30 cpu = <&cpu0>; 31 }; 32 33 core1 { 34 cpu = <&cpu1>; 35 }; 36 37 core2 { 38 cpu = <&cpu2>; 39 }; 40 41 core3 { 42 cpu = <&cpu3>; 43 }; 44 45 core4 { 46 cpu = <&cpu4>; 47 }; 48 49 core5 { 50 cpu = <&cpu5>; 51 }; 52 53 core6 { 54 cpu = <&cpu6>; 55 }; 56 57 core7 { 58 cpu = <&cpu7>; 59 }; 60 }; 61 }; 62 63 cpu0: cpu@0 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a55"; 66 reg = <0x000>; 67 enable-method = "psci"; 68 clock-frequency = <2000000000>; 69 capacity-dmips-mhz = <382>; 70 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 71 i-cache-size = <32768>; 72 i-cache-line-size = <64>; 73 i-cache-sets = <128>; 74 d-cache-size = <32768>; 75 d-cache-line-size = <64>; 76 d-cache-sets = <128>; 77 next-level-cache = <&l2_0>; 78 #cooling-cells = <2>; 79 }; 80 81 cpu1: cpu@100 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a55"; 84 reg = <0x100>; 85 enable-method = "psci"; 86 clock-frequency = <2000000000>; 87 capacity-dmips-mhz = <382>; 88 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 89 i-cache-size = <32768>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <128>; 92 d-cache-size = <32768>; 93 d-cache-line-size = <64>; 94 d-cache-sets = <128>; 95 next-level-cache = <&l2_0>; 96 #cooling-cells = <2>; 97 }; 98 99 cpu2: cpu@200 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a55"; 102 reg = <0x200>; 103 enable-method = "psci"; 104 clock-frequency = <2000000000>; 105 capacity-dmips-mhz = <382>; 106 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 107 i-cache-size = <32768>; 108 i-cache-line-size = <64>; 109 i-cache-sets = <128>; 110 d-cache-size = <32768>; 111 d-cache-line-size = <64>; 112 d-cache-sets = <128>; 113 next-level-cache = <&l2_0>; 114 #cooling-cells = <2>; 115 }; 116 117 cpu3: cpu@300 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a55"; 120 reg = <0x300>; 121 enable-method = "psci"; 122 clock-frequency = <2000000000>; 123 capacity-dmips-mhz = <382>; 124 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 125 i-cache-size = <32768>; 126 i-cache-line-size = <64>; 127 i-cache-sets = <128>; 128 d-cache-size = <32768>; 129 d-cache-line-size = <64>; 130 d-cache-sets = <128>; 131 next-level-cache = <&l2_0>; 132 #cooling-cells = <2>; 133 }; 134 135 cpu4: cpu@400 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a55"; 138 reg = <0x400>; 139 enable-method = "psci"; 140 clock-frequency = <2000000000>; 141 capacity-dmips-mhz = <382>; 142 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 143 i-cache-size = <32768>; 144 i-cache-line-size = <64>; 145 i-cache-sets = <128>; 146 d-cache-size = <32768>; 147 d-cache-line-size = <64>; 148 d-cache-sets = <128>; 149 next-level-cache = <&l2_0>; 150 #cooling-cells = <2>; 151 }; 152 153 cpu5: cpu@500 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a55"; 156 reg = <0x500>; 157 enable-method = "psci"; 158 clock-frequency = <2000000000>; 159 capacity-dmips-mhz = <382>; 160 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 161 i-cache-size = <32768>; 162 i-cache-line-size = <64>; 163 i-cache-sets = <128>; 164 d-cache-size = <32768>; 165 d-cache-line-size = <64>; 166 d-cache-sets = <128>; 167 next-level-cache = <&l2_0>; 168 #cooling-cells = <2>; 169 }; 170 171 cpu6: cpu@600 { 172 device_type = "cpu"; 173 compatible = "arm,cortex-a76"; 174 reg = <0x600>; 175 enable-method = "psci"; 176 clock-frequency = <2050000000>; 177 capacity-dmips-mhz = <1024>; 178 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 179 i-cache-size = <65536>; 180 i-cache-line-size = <64>; 181 i-cache-sets = <256>; 182 d-cache-size = <65536>; 183 d-cache-line-size = <64>; 184 d-cache-sets = <256>; 185 next-level-cache = <&l2_1>; 186 #cooling-cells = <2>; 187 }; 188 189 cpu7: cpu@700 { 190 device_type = "cpu"; 191 compatible = "arm,cortex-a76"; 192 reg = <0x700>; 193 enable-method = "psci"; 194 clock-frequency = <2050000000>; 195 capacity-dmips-mhz = <1024>; 196 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 197 i-cache-size = <65536>; 198 i-cache-line-size = <64>; 199 i-cache-sets = <256>; 200 d-cache-size = <65536>; 201 d-cache-line-size = <64>; 202 d-cache-sets = <256>; 203 next-level-cache = <&l2_1>; 204 #cooling-cells = <2>; 205 }; 206 207 idle-states { 208 entry-method = "psci"; 209 210 cpu_ret_l: cpu-retention-l { 211 compatible = "arm,idle-state"; 212 arm,psci-suspend-param = <0x00010001>; 213 local-timer-stop; 214 entry-latency-us = <50>; 215 exit-latency-us = <100>; 216 min-residency-us = <1600>; 217 }; 218 219 cpu_ret_b: cpu-retention-b { 220 compatible = "arm,idle-state"; 221 arm,psci-suspend-param = <0x00010001>; 222 local-timer-stop; 223 entry-latency-us = <50>; 224 exit-latency-us = <100>; 225 min-residency-us = <1400>; 226 }; 227 228 cpu_off_l: cpu-off-l { 229 compatible = "arm,idle-state"; 230 arm,psci-suspend-param = <0x01010001>; 231 local-timer-stop; 232 entry-latency-us = <100>; 233 exit-latency-us = <250>; 234 min-residency-us = <2100>; 235 }; 236 237 cpu_off_b: cpu-off-b { 238 compatible = "arm,idle-state"; 239 arm,psci-suspend-param = <0x01010001>; 240 local-timer-stop; 241 entry-latency-us = <100>; 242 exit-latency-us = <250>; 243 min-residency-us = <1900>; 244 }; 245 }; 246 247 l2_0: l2-cache0 { 248 compatible = "cache"; 249 cache-level = <2>; 250 cache-size = <131072>; 251 cache-line-size = <64>; 252 cache-sets = <512>; 253 next-level-cache = <&l3_0>; 254 }; 255 256 l2_1: l2-cache1 { 257 compatible = "cache"; 258 cache-level = <2>; 259 cache-size = <262144>; 260 cache-line-size = <64>; 261 cache-sets = <512>; 262 next-level-cache = <&l3_0>; 263 }; 264 265 l3_0: l3-cache { 266 compatible = "cache"; 267 cache-level = <3>; 268 cache-size = <1048576>; 269 cache-line-size = <64>; 270 cache-sets = <1024>; 271 cache-unified; 272 }; 273 }; 274 275 clk13m: fixed-factor-clock-13m { 276 compatible = "fixed-factor-clock"; 277 #clock-cells = <0>; 278 clocks = <&clk26m>; 279 clock-div = <2>; 280 clock-mult = <1>; 281 clock-output-names = "clk13m"; 282 }; 283 284 clk26m: oscillator-26m { 285 compatible = "fixed-clock"; 286 #clock-cells = <0>; 287 clock-frequency = <26000000>; 288 clock-output-names = "clk26m"; 289 }; 290 291 clk32k: oscillator-32k { 292 compatible = "fixed-clock"; 293 #clock-cells = <0>; 294 clock-frequency = <32768>; 295 clock-output-names = "clk32k"; 296 }; 297 298 pmu-a55 { 299 compatible = "arm,cortex-a55-pmu"; 300 interrupt-parent = <&gic>; 301 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 302 }; 303 304 pmu-a76 { 305 compatible = "arm,cortex-a76-pmu"; 306 interrupt-parent = <&gic>; 307 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 308 }; 309 310 psci { 311 compatible = "arm,psci-1.0"; 312 method = "smc"; 313 }; 314 315 timer { 316 compatible = "arm,armv8-timer"; 317 interrupt-parent = <&gic>; 318 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 319 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 320 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 321 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 322 }; 323 324 soc { 325 #address-cells = <2>; 326 #size-cells = <2>; 327 compatible = "simple-bus"; 328 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 329 ranges; 330 331 gic: interrupt-controller@c000000 { 332 compatible = "arm,gic-v3"; 333 #interrupt-cells = <4>; 334 #redistributor-regions = <1>; 335 interrupt-parent = <&gic>; 336 interrupt-controller; 337 reg = <0 0x0c000000 0 0x40000>, 338 <0 0x0c040000 0 0x200000>; 339 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 340 341 ppi-partitions { 342 ppi_cluster0: interrupt-partition-0 { 343 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 344 }; 345 346 ppi_cluster1: interrupt-partition-1 { 347 affinity = <&cpu6 &cpu7>; 348 }; 349 }; 350 }; 351 352 mcusys: syscon@c53a000 { 353 compatible = "mediatek,mt8186-mcusys", "syscon"; 354 reg = <0 0xc53a000 0 0x1000>; 355 #clock-cells = <1>; 356 }; 357 358 topckgen: syscon@10000000 { 359 compatible = "mediatek,mt8186-topckgen", "syscon"; 360 reg = <0 0x10000000 0 0x1000>; 361 #clock-cells = <1>; 362 }; 363 364 infracfg_ao: syscon@10001000 { 365 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 366 reg = <0 0x10001000 0 0x1000>; 367 #clock-cells = <1>; 368 #reset-cells = <1>; 369 }; 370 371 pericfg: syscon@10003000 { 372 compatible = "mediatek,mt8186-pericfg", "syscon"; 373 reg = <0 0x10003000 0 0x1000>; 374 }; 375 376 pio: pinctrl@10005000 { 377 compatible = "mediatek,mt8186-pinctrl"; 378 reg = <0 0x10005000 0 0x1000>, 379 <0 0x10002000 0 0x0200>, 380 <0 0x10002200 0 0x0200>, 381 <0 0x10002400 0 0x0200>, 382 <0 0x10002600 0 0x0200>, 383 <0 0x10002a00 0 0x0200>, 384 <0 0x10002c00 0 0x0200>, 385 <0 0x1000b000 0 0x1000>; 386 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 387 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 388 gpio-controller; 389 #gpio-cells = <2>; 390 gpio-ranges = <&pio 0 0 185>; 391 interrupt-controller; 392 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 393 #interrupt-cells = <2>; 394 }; 395 396 scpsys: syscon@10006000 { 397 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 398 reg = <0 0x10006000 0 0x1000>; 399 400 /* System Power Manager */ 401 spm: power-controller { 402 compatible = "mediatek,mt8186-power-controller"; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 #power-domain-cells = <1>; 406 407 /* power domain of the SoC */ 408 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 409 reg = <MT8186_POWER_DOMAIN_MFG0>; 410 clocks = <&topckgen CLK_TOP_MFG>; 411 clock-names = "mfg00"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 #power-domain-cells = <1>; 415 416 power-domain@MT8186_POWER_DOMAIN_MFG1 { 417 reg = <MT8186_POWER_DOMAIN_MFG1>; 418 mediatek,infracfg = <&infracfg_ao>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 #power-domain-cells = <1>; 422 423 power-domain@MT8186_POWER_DOMAIN_MFG2 { 424 reg = <MT8186_POWER_DOMAIN_MFG2>; 425 #power-domain-cells = <0>; 426 }; 427 428 power-domain@MT8186_POWER_DOMAIN_MFG3 { 429 reg = <MT8186_POWER_DOMAIN_MFG3>; 430 #power-domain-cells = <0>; 431 }; 432 }; 433 }; 434 435 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 436 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 437 clocks = <&topckgen CLK_TOP_SENINF>, 438 <&topckgen CLK_TOP_SENINF1>; 439 clock-names = "csirx_top0", "csirx_top1"; 440 #power-domain-cells = <0>; 441 }; 442 443 power-domain@MT8186_POWER_DOMAIN_SSUSB { 444 reg = <MT8186_POWER_DOMAIN_SSUSB>; 445 #power-domain-cells = <0>; 446 }; 447 448 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 449 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 450 #power-domain-cells = <0>; 451 }; 452 453 power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 454 reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 455 clocks = <&topckgen CLK_TOP_AUDIODSP>, 456 <&topckgen CLK_TOP_ADSP_BUS>; 457 clock-names = "audioadsp", "adsp_bus"; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 #power-domain-cells = <1>; 461 462 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 463 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 #power-domain-cells = <1>; 467 468 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 469 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 470 mediatek,infracfg = <&infracfg_ao>; 471 #power-domain-cells = <0>; 472 }; 473 }; 474 }; 475 476 power-domain@MT8186_POWER_DOMAIN_CONN_ON { 477 reg = <MT8186_POWER_DOMAIN_CONN_ON>; 478 mediatek,infracfg = <&infracfg_ao>; 479 #power-domain-cells = <0>; 480 }; 481 482 power-domain@MT8186_POWER_DOMAIN_DIS { 483 reg = <MT8186_POWER_DOMAIN_DIS>; 484 clocks = <&topckgen CLK_TOP_DISP>, 485 <&topckgen CLK_TOP_MDP>, 486 <&mmsys CLK_MM_SMI_INFRA>, 487 <&mmsys CLK_MM_SMI_COMMON>, 488 <&mmsys CLK_MM_SMI_GALS>, 489 <&mmsys CLK_MM_SMI_IOMMU>; 490 clock-names = "disp", "mdp", "smi_infra", "smi_common", 491 "smi_gals", "smi_iommu"; 492 mediatek,infracfg = <&infracfg_ao>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 #power-domain-cells = <1>; 496 497 power-domain@MT8186_POWER_DOMAIN_VDEC { 498 reg = <MT8186_POWER_DOMAIN_VDEC>; 499 clocks = <&topckgen CLK_TOP_VDEC>, 500 <&vdecsys CLK_VDEC_LARB1_CKEN>; 501 clock-names = "vdec0", "larb"; 502 mediatek,infracfg = <&infracfg_ao>; 503 #power-domain-cells = <0>; 504 }; 505 506 power-domain@MT8186_POWER_DOMAIN_CAM { 507 reg = <MT8186_POWER_DOMAIN_CAM>; 508 clocks = <&topckgen CLK_TOP_CAM>, 509 <&topckgen CLK_TOP_SENINF>, 510 <&topckgen CLK_TOP_SENINF1>, 511 <&topckgen CLK_TOP_SENINF2>, 512 <&topckgen CLK_TOP_SENINF3>, 513 <&topckgen CLK_TOP_CAMTM>, 514 <&camsys CLK_CAM2MM_GALS>; 515 clock-names = "cam-top", "cam0", "cam1", "cam2", 516 "cam3", "cam-tm", "gals"; 517 mediatek,infracfg = <&infracfg_ao>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 #power-domain-cells = <1>; 521 522 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 523 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 524 #power-domain-cells = <0>; 525 }; 526 527 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 528 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 529 #power-domain-cells = <0>; 530 }; 531 }; 532 533 power-domain@MT8186_POWER_DOMAIN_IMG { 534 reg = <MT8186_POWER_DOMAIN_IMG>; 535 clocks = <&topckgen CLK_TOP_IMG1>, 536 <&imgsys1 CLK_IMG1_GALS_IMG1>; 537 clock-names = "img-top", "gals"; 538 mediatek,infracfg = <&infracfg_ao>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 #power-domain-cells = <1>; 542 543 power-domain@MT8186_POWER_DOMAIN_IMG2 { 544 reg = <MT8186_POWER_DOMAIN_IMG2>; 545 #power-domain-cells = <0>; 546 }; 547 }; 548 549 power-domain@MT8186_POWER_DOMAIN_IPE { 550 reg = <MT8186_POWER_DOMAIN_IPE>; 551 clocks = <&topckgen CLK_TOP_IPE>, 552 <&ipesys CLK_IPE_LARB19>, 553 <&ipesys CLK_IPE_LARB20>, 554 <&ipesys CLK_IPE_SMI_SUBCOM>, 555 <&ipesys CLK_IPE_GALS_IPE>; 556 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", 557 "ipe-smi", "ipe-gals"; 558 mediatek,infracfg = <&infracfg_ao>; 559 #power-domain-cells = <0>; 560 }; 561 562 power-domain@MT8186_POWER_DOMAIN_VENC { 563 reg = <MT8186_POWER_DOMAIN_VENC>; 564 clocks = <&topckgen CLK_TOP_VENC>, 565 <&vencsys CLK_VENC_CKE1_VENC>; 566 clock-names = "venc0", "larb"; 567 mediatek,infracfg = <&infracfg_ao>; 568 #power-domain-cells = <0>; 569 }; 570 571 power-domain@MT8186_POWER_DOMAIN_WPE { 572 reg = <MT8186_POWER_DOMAIN_WPE>; 573 clocks = <&topckgen CLK_TOP_WPE>, 574 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 575 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 576 clock-names = "wpe0", "larb-ck", "larb-pclk"; 577 mediatek,infracfg = <&infracfg_ao>; 578 #power-domain-cells = <0>; 579 }; 580 }; 581 }; 582 }; 583 584 watchdog: watchdog@10007000 { 585 compatible = "mediatek,mt8186-wdt"; 586 mediatek,disable-extrst; 587 reg = <0 0x10007000 0 0x1000>; 588 #reset-cells = <1>; 589 }; 590 591 apmixedsys: syscon@1000c000 { 592 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 593 reg = <0 0x1000c000 0 0x1000>; 594 #clock-cells = <1>; 595 }; 596 597 pwrap: pwrap@1000d000 { 598 compatible = "mediatek,mt8186-pwrap", "syscon"; 599 reg = <0 0x1000d000 0 0x1000>; 600 reg-names = "pwrap"; 601 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 602 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 603 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 604 clock-names = "spi", "wrap"; 605 }; 606 607 spmi: spmi@10015000 { 608 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; 609 reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; 610 reg-names = "pmif", "spmimst"; 611 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 612 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 613 <&topckgen CLK_TOP_SPMI_MST>; 614 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 615 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; 616 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 617 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>, 618 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>; 619 status = "disabled"; 620 }; 621 622 systimer: timer@10017000 { 623 compatible = "mediatek,mt8186-timer", 624 "mediatek,mt6765-timer"; 625 reg = <0 0x10017000 0 0x1000>; 626 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 627 clocks = <&clk13m>; 628 }; 629 630 gce: mailbox@1022c000 { 631 compatible = "mediatek,mt8186-gce"; 632 reg = <0 0X1022c000 0 0x4000>; 633 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 634 clock-names = "gce"; 635 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 636 #mbox-cells = <2>; 637 }; 638 639 scp: scp@10500000 { 640 compatible = "mediatek,mt8186-scp"; 641 reg = <0 0x10500000 0 0x40000>, 642 <0 0x105c0000 0 0x19080>; 643 reg-names = "sram", "cfg"; 644 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 645 }; 646 647 adsp: adsp@10680000 { 648 compatible = "mediatek,mt8186-dsp"; 649 reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, 650 <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; 651 reg-names = "cfg", "sram", "sec", "bus"; 652 clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; 653 clock-names = "audiodsp", "adsp_bus"; 654 assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, 655 <&topckgen CLK_TOP_ADSP_BUS>; 656 assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; 657 mbox-names = "rx", "tx"; 658 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 659 power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; 660 status = "disabled"; 661 }; 662 663 adsp_mailbox0: mailbox@10686000 { 664 compatible = "mediatek,mt8186-adsp-mbox"; 665 #mbox-cells = <0>; 666 reg = <0 0x10686100 0 0x1000>; 667 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 668 }; 669 670 adsp_mailbox1: mailbox@10687000 { 671 compatible = "mediatek,mt8186-adsp-mbox"; 672 #mbox-cells = <0>; 673 reg = <0 0x10687100 0 0x1000>; 674 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>; 675 }; 676 677 nor_flash: spi@11000000 { 678 compatible = "mediatek,mt8186-nor"; 679 reg = <0 0x11000000 0 0x1000>; 680 clocks = <&topckgen CLK_TOP_SPINOR>, 681 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 682 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 683 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 684 clock-names = "spi", "sf", "axi", "axi_s"; 685 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 686 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 687 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 688 status = "disabled"; 689 }; 690 691 auxadc: adc@11001000 { 692 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 693 reg = <0 0x11001000 0 0x1000>; 694 #io-channel-cells = <1>; 695 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 696 clock-names = "main"; 697 }; 698 699 uart0: serial@11002000 { 700 compatible = "mediatek,mt8186-uart", 701 "mediatek,mt6577-uart"; 702 reg = <0 0x11002000 0 0x1000>; 703 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 704 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 705 clock-names = "baud", "bus"; 706 status = "disabled"; 707 }; 708 709 uart1: serial@11003000 { 710 compatible = "mediatek,mt8186-uart", 711 "mediatek,mt6577-uart"; 712 reg = <0 0x11003000 0 0x1000>; 713 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 714 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 715 clock-names = "baud", "bus"; 716 status = "disabled"; 717 }; 718 719 i2c0: i2c@11007000 { 720 compatible = "mediatek,mt8186-i2c"; 721 reg = <0 0x11007000 0 0x1000>, 722 <0 0x10200100 0 0x100>; 723 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 724 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 725 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 726 clock-names = "main", "dma"; 727 clock-div = <1>; 728 #address-cells = <1>; 729 #size-cells = <0>; 730 status = "disabled"; 731 }; 732 733 i2c1: i2c@11008000 { 734 compatible = "mediatek,mt8186-i2c"; 735 reg = <0 0x11008000 0 0x1000>, 736 <0 0x10200200 0 0x100>; 737 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 738 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 739 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 740 clock-names = "main", "dma"; 741 clock-div = <1>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 status = "disabled"; 745 }; 746 747 i2c2: i2c@11009000 { 748 compatible = "mediatek,mt8186-i2c"; 749 reg = <0 0x11009000 0 0x1000>, 750 <0 0x10200300 0 0x180>; 751 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 752 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 753 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 754 clock-names = "main", "dma"; 755 clock-div = <1>; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 status = "disabled"; 759 }; 760 761 i2c3: i2c@1100f000 { 762 compatible = "mediatek,mt8186-i2c"; 763 reg = <0 0x1100f000 0 0x1000>, 764 <0 0x10200480 0 0x100>; 765 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 766 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 767 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 768 clock-names = "main", "dma"; 769 clock-div = <1>; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 status = "disabled"; 773 }; 774 775 i2c4: i2c@11011000 { 776 compatible = "mediatek,mt8186-i2c"; 777 reg = <0 0x11011000 0 0x1000>, 778 <0 0x10200580 0 0x180>; 779 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 780 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 781 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 782 clock-names = "main", "dma"; 783 clock-div = <1>; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 status = "disabled"; 787 }; 788 789 i2c5: i2c@11016000 { 790 compatible = "mediatek,mt8186-i2c"; 791 reg = <0 0x11016000 0 0x1000>, 792 <0 0x10200700 0 0x100>; 793 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 794 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 795 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 796 clock-names = "main", "dma"; 797 clock-div = <1>; 798 #address-cells = <1>; 799 #size-cells = <0>; 800 status = "disabled"; 801 }; 802 803 i2c6: i2c@1100d000 { 804 compatible = "mediatek,mt8186-i2c"; 805 reg = <0 0x1100d000 0 0x1000>, 806 <0 0x10200800 0 0x100>; 807 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 808 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 809 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 810 clock-names = "main", "dma"; 811 clock-div = <1>; 812 #address-cells = <1>; 813 #size-cells = <0>; 814 status = "disabled"; 815 }; 816 817 i2c7: i2c@11004000 { 818 compatible = "mediatek,mt8186-i2c"; 819 reg = <0 0x11004000 0 0x1000>, 820 <0 0x10200900 0 0x180>; 821 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 822 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 823 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 824 clock-names = "main", "dma"; 825 clock-div = <1>; 826 #address-cells = <1>; 827 #size-cells = <0>; 828 status = "disabled"; 829 }; 830 831 i2c8: i2c@11005000 { 832 compatible = "mediatek,mt8186-i2c"; 833 reg = <0 0x11005000 0 0x1000>, 834 <0 0x10200A80 0 0x180>; 835 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 836 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 837 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 838 clock-names = "main", "dma"; 839 clock-div = <1>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 status = "disabled"; 843 }; 844 845 spi0: spi@1100a000 { 846 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 reg = <0 0x1100a000 0 0x1000>; 850 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 851 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 852 <&topckgen CLK_TOP_SPI>, 853 <&infracfg_ao CLK_INFRA_AO_SPI0>; 854 clock-names = "parent-clk", "sel-clk", "spi-clk"; 855 status = "disabled"; 856 }; 857 858 pwm0: pwm@1100e000 { 859 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 860 reg = <0 0x1100e000 0 0x1000>; 861 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 862 #pwm-cells = <2>; 863 clocks = <&topckgen CLK_TOP_DISP_PWM>, 864 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 865 clock-names = "main", "mm"; 866 status = "disabled"; 867 }; 868 869 spi1: spi@11010000 { 870 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 reg = <0 0x11010000 0 0x1000>; 874 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 875 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 876 <&topckgen CLK_TOP_SPI>, 877 <&infracfg_ao CLK_INFRA_AO_SPI1>; 878 clock-names = "parent-clk", "sel-clk", "spi-clk"; 879 status = "disabled"; 880 }; 881 882 spi2: spi@11012000 { 883 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 reg = <0 0x11012000 0 0x1000>; 887 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 888 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 889 <&topckgen CLK_TOP_SPI>, 890 <&infracfg_ao CLK_INFRA_AO_SPI2>; 891 clock-names = "parent-clk", "sel-clk", "spi-clk"; 892 status = "disabled"; 893 }; 894 895 spi3: spi@11013000 { 896 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 897 #address-cells = <1>; 898 #size-cells = <0>; 899 reg = <0 0x11013000 0 0x1000>; 900 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 901 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 902 <&topckgen CLK_TOP_SPI>, 903 <&infracfg_ao CLK_INFRA_AO_SPI3>; 904 clock-names = "parent-clk", "sel-clk", "spi-clk"; 905 status = "disabled"; 906 }; 907 908 spi4: spi@11014000 { 909 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 reg = <0 0x11014000 0 0x1000>; 913 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 914 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 915 <&topckgen CLK_TOP_SPI>, 916 <&infracfg_ao CLK_INFRA_AO_SPI4>; 917 clock-names = "parent-clk", "sel-clk", "spi-clk"; 918 status = "disabled"; 919 }; 920 921 spi5: spi@11015000 { 922 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 reg = <0 0x11015000 0 0x1000>; 926 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 927 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 928 <&topckgen CLK_TOP_SPI>, 929 <&infracfg_ao CLK_INFRA_AO_SPI5>; 930 clock-names = "parent-clk", "sel-clk", "spi-clk"; 931 status = "disabled"; 932 }; 933 934 imp_iic_wrap: clock-controller@11017000 { 935 compatible = "mediatek,mt8186-imp_iic_wrap"; 936 reg = <0 0x11017000 0 0x1000>; 937 #clock-cells = <1>; 938 }; 939 940 uart2: serial@11018000 { 941 compatible = "mediatek,mt8186-uart", 942 "mediatek,mt6577-uart"; 943 reg = <0 0x11018000 0 0x1000>; 944 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 945 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 946 clock-names = "baud", "bus"; 947 status = "disabled"; 948 }; 949 950 i2c9: i2c@11019000 { 951 compatible = "mediatek,mt8186-i2c"; 952 reg = <0 0x11019000 0 0x1000>, 953 <0 0x10200c00 0 0x180>; 954 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 955 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 956 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 957 clock-names = "main", "dma"; 958 clock-div = <1>; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 status = "disabled"; 962 }; 963 964 afe: audio-controller@11210000 { 965 compatible = "mediatek,mt8186-sound"; 966 reg = <0 0x11210000 0 0x2000>; 967 clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, 968 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, 969 <&topckgen CLK_TOP_AUDIO>, 970 <&topckgen CLK_TOP_AUD_INTBUS>, 971 <&topckgen CLK_TOP_MAINPLL_D2_D4>, 972 <&topckgen CLK_TOP_AUD_1>, 973 <&apmixedsys CLK_APMIXED_APLL1>, 974 <&topckgen CLK_TOP_AUD_2>, 975 <&apmixedsys CLK_APMIXED_APLL2>, 976 <&topckgen CLK_TOP_AUD_ENGEN1>, 977 <&topckgen CLK_TOP_APLL1_D8>, 978 <&topckgen CLK_TOP_AUD_ENGEN2>, 979 <&topckgen CLK_TOP_APLL2_D8>, 980 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, 981 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, 982 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, 983 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, 984 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, 985 <&topckgen CLK_TOP_APLL12_CK_DIV0>, 986 <&topckgen CLK_TOP_APLL12_CK_DIV1>, 987 <&topckgen CLK_TOP_APLL12_CK_DIV2>, 988 <&topckgen CLK_TOP_APLL12_CK_DIV4>, 989 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, 990 <&topckgen CLK_TOP_AUDIO_H>, 991 <&clk26m>; 992 clock-names = "aud_infra_clk", 993 "mtkaif_26m_clk", 994 "top_mux_audio", 995 "top_mux_audio_int", 996 "top_mainpll_d2_d4", 997 "top_mux_aud_1", 998 "top_apll1_ck", 999 "top_mux_aud_2", 1000 "top_apll2_ck", 1001 "top_mux_aud_eng1", 1002 "top_apll1_d8", 1003 "top_mux_aud_eng2", 1004 "top_apll2_d8", 1005 "top_i2s0_m_sel", 1006 "top_i2s1_m_sel", 1007 "top_i2s2_m_sel", 1008 "top_i2s4_m_sel", 1009 "top_tdm_m_sel", 1010 "top_apll12_div0", 1011 "top_apll12_div1", 1012 "top_apll12_div2", 1013 "top_apll12_div4", 1014 "top_apll12_div_tdm", 1015 "top_mux_audio_h", 1016 "top_clk26m_clk"; 1017 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1018 mediatek,apmixedsys = <&apmixedsys>; 1019 mediatek,infracfg = <&infracfg_ao>; 1020 mediatek,topckgen = <&topckgen>; 1021 resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; 1022 reset-names = "audiosys"; 1023 status = "disabled"; 1024 }; 1025 1026 ssusb0: usb@11201000 { 1027 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1028 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1029 reg-names = "mac", "ippc"; 1030 clocks = <&topckgen CLK_TOP_USB_TOP>, 1031 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1032 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1033 <&infracfg_ao CLK_INFRA_AO_ICUSB>; 1034 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1035 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>; 1036 phys = <&u2port0 PHY_TYPE_USB2>; 1037 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; 1038 #address-cells = <2>; 1039 #size-cells = <2>; 1040 ranges; 1041 status = "disabled"; 1042 1043 usb_host0: usb@11200000 { 1044 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1045 reg = <0 0x11200000 0 0x1000>; 1046 reg-names = "mac"; 1047 clocks = <&topckgen CLK_TOP_USB_TOP>, 1048 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1049 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1050 <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1051 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1052 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1053 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 1054 mediatek,syscon-wakeup = <&pericfg 0x420 2>; 1055 wakeup-source; 1056 status = "disabled"; 1057 }; 1058 }; 1059 1060 mmc0: mmc@11230000 { 1061 compatible = "mediatek,mt8186-mmc", 1062 "mediatek,mt8183-mmc"; 1063 reg = <0 0x11230000 0 0x10000>, 1064 <0 0x11cd0000 0 0x1000>; 1065 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1066 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1067 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1068 <&infracfg_ao CLK_INFRA_AO_MSDCFDE>; 1069 clock-names = "source", "hclk", "source_cg", "crypto"; 1070 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 1071 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 1072 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 1073 status = "disabled"; 1074 }; 1075 1076 mmc1: mmc@11240000 { 1077 compatible = "mediatek,mt8186-mmc", 1078 "mediatek,mt8183-mmc"; 1079 reg = <0 0x11240000 0 0x1000>, 1080 <0 0x11c90000 0 0x1000>; 1081 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1082 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1083 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1084 clock-names = "source", "hclk", "source_cg"; 1085 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 1086 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1087 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1088 status = "disabled"; 1089 }; 1090 1091 ssusb1: usb@11281000 { 1092 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1093 reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; 1094 reg-names = "mac", "ippc"; 1095 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1096 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1097 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1098 <&clk26m>; 1099 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1100 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 1101 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1102 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; 1103 #address-cells = <2>; 1104 #size-cells = <2>; 1105 ranges; 1106 status = "disabled"; 1107 1108 usb_host1: usb@11280000 { 1109 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1110 reg = <0 0x11280000 0 0x1000>; 1111 reg-names = "mac"; 1112 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1113 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1114 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1115 <&clk26m>, 1116 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1117 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; 1118 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1119 mediatek,syscon-wakeup = <&pericfg 0x424 2>; 1120 wakeup-source; 1121 status = "disabled"; 1122 }; 1123 }; 1124 1125 u3phy0: t-phy@11c80000 { 1126 compatible = "mediatek,mt8186-tphy", 1127 "mediatek,generic-tphy-v2"; 1128 #address-cells = <1>; 1129 #size-cells = <1>; 1130 ranges = <0x0 0x0 0x11c80000 0x1000>; 1131 status = "disabled"; 1132 1133 u2port1: usb-phy@0 { 1134 reg = <0x0 0x700>; 1135 clocks = <&clk26m>; 1136 clock-names = "ref"; 1137 #phy-cells = <1>; 1138 }; 1139 1140 u3port1: usb-phy@700 { 1141 reg = <0x700 0x900>; 1142 clocks = <&clk26m>; 1143 clock-names = "ref"; 1144 #phy-cells = <1>; 1145 }; 1146 }; 1147 1148 u3phy1: t-phy@11ca0000 { 1149 compatible = "mediatek,mt8186-tphy", 1150 "mediatek,generic-tphy-v2"; 1151 #address-cells = <1>; 1152 #size-cells = <1>; 1153 ranges = <0x0 0x0 0x11ca0000 0x1000>; 1154 status = "disabled"; 1155 1156 u2port0: usb-phy@0 { 1157 reg = <0x0 0x700>; 1158 clocks = <&clk26m>; 1159 clock-names = "ref"; 1160 #phy-cells = <1>; 1161 mediatek,discth = <0x8>; 1162 }; 1163 }; 1164 1165 efuse: efuse@11cb0000 { 1166 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 1167 reg = <0 0x11cb0000 0 0x1000>; 1168 #address-cells = <1>; 1169 #size-cells = <1>; 1170 }; 1171 1172 mipi_tx0: dsi-phy@11cc0000 { 1173 compatible = "mediatek,mt8183-mipi-tx"; 1174 reg = <0 0x11cc0000 0 0x1000>; 1175 clocks = <&clk26m>; 1176 #clock-cells = <0>; 1177 #phy-cells = <0>; 1178 clock-output-names = "mipi_tx0_pll"; 1179 status = "disabled"; 1180 }; 1181 1182 mfgsys: clock-controller@13000000 { 1183 compatible = "mediatek,mt8186-mfgsys"; 1184 reg = <0 0x13000000 0 0x1000>; 1185 #clock-cells = <1>; 1186 }; 1187 1188 gpu: gpu@13040000 { 1189 compatible = "mediatek,mt8186-mali", 1190 "arm,mali-bifrost"; 1191 reg = <0 0x13040000 0 0x4000>; 1192 1193 clocks = <&mfgsys CLK_MFG_BG3D>; 1194 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>, 1195 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>, 1196 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 1197 interrupt-names = "job", "mmu", "gpu"; 1198 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>, 1199 <&spm MT8186_POWER_DOMAIN_MFG3>; 1200 power-domain-names = "core0", "core1"; 1201 #cooling-cells = <2>; 1202 status = "disabled"; 1203 }; 1204 1205 mmsys: syscon@14000000 { 1206 compatible = "mediatek,mt8186-mmsys", "syscon"; 1207 reg = <0 0x14000000 0 0x1000>; 1208 #clock-cells = <1>; 1209 #reset-cells = <1>; 1210 }; 1211 1212 smi_common: smi@14002000 { 1213 compatible = "mediatek,mt8186-smi-common"; 1214 reg = <0 0x14002000 0 0x1000>; 1215 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 1216 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 1217 clock-names = "apb", "smi", "gals0", "gals1"; 1218 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1219 }; 1220 1221 larb0: smi@14003000 { 1222 compatible = "mediatek,mt8186-smi-larb"; 1223 reg = <0 0x14003000 0 0x1000>; 1224 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1225 <&mmsys CLK_MM_SMI_COMMON>; 1226 clock-names = "apb", "smi"; 1227 mediatek,larb-id = <0>; 1228 mediatek,smi = <&smi_common>; 1229 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1230 }; 1231 1232 larb1: smi@14004000 { 1233 compatible = "mediatek,mt8186-smi-larb"; 1234 reg = <0 0x14004000 0 0x1000>; 1235 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1236 <&mmsys CLK_MM_SMI_COMMON>; 1237 clock-names = "apb", "smi"; 1238 mediatek,larb-id = <1>; 1239 mediatek,smi = <&smi_common>; 1240 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1241 }; 1242 1243 dpi: dpi@1400a000 { 1244 compatible = "mediatek,mt8186-dpi"; 1245 reg = <0 0x1400a000 0 0x1000>; 1246 clocks = <&topckgen CLK_TOP_DPI>, 1247 <&mmsys CLK_MM_DISP_DPI>, 1248 <&apmixedsys CLK_APMIXED_TVDPLL>; 1249 clock-names = "pixel", "engine", "pll"; 1250 assigned-clocks = <&topckgen CLK_TOP_DPI>; 1251 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; 1252 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; 1253 status = "disabled"; 1254 1255 port { 1256 dpi_out: endpoint { }; 1257 }; 1258 }; 1259 1260 dsi0: dsi@14013000 { 1261 compatible = "mediatek,mt8186-dsi"; 1262 reg = <0 0x14013000 0 0x1000>; 1263 clocks = <&mmsys CLK_MM_DSI0>, 1264 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 1265 <&mipi_tx0>; 1266 clock-names = "engine", "digital", "hs"; 1267 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 1268 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1269 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 1270 phys = <&mipi_tx0>; 1271 phy-names = "dphy"; 1272 status = "disabled"; 1273 1274 port { 1275 dsi_out: endpoint { }; 1276 }; 1277 }; 1278 1279 iommu_mm: iommu@14016000 { 1280 compatible = "mediatek,mt8186-iommu-mm"; 1281 reg = <0 0x14016000 0 0x1000>; 1282 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1283 clock-names = "bclk"; 1284 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1285 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1286 &larb7 &larb8 &larb9 &larb11 1287 &larb13 &larb14 &larb16 &larb17 1288 &larb19 &larb20>; 1289 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1290 #iommu-cells = <1>; 1291 }; 1292 1293 wpesys: clock-controller@14020000 { 1294 compatible = "mediatek,mt8186-wpesys"; 1295 reg = <0 0x14020000 0 0x1000>; 1296 #clock-cells = <1>; 1297 }; 1298 1299 larb8: smi@14023000 { 1300 compatible = "mediatek,mt8186-smi-larb"; 1301 reg = <0 0x14023000 0 0x1000>; 1302 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1303 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1304 clock-names = "apb", "smi"; 1305 mediatek,larb-id = <8>; 1306 mediatek,smi = <&smi_common>; 1307 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1308 }; 1309 1310 imgsys1: clock-controller@15020000 { 1311 compatible = "mediatek,mt8186-imgsys1"; 1312 reg = <0 0x15020000 0 0x1000>; 1313 #clock-cells = <1>; 1314 }; 1315 1316 larb9: smi@1502e000 { 1317 compatible = "mediatek,mt8186-smi-larb"; 1318 reg = <0 0x1502e000 0 0x1000>; 1319 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1320 <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1321 clock-names = "apb", "smi"; 1322 mediatek,larb-id = <9>; 1323 mediatek,smi = <&smi_common>; 1324 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 1325 }; 1326 1327 imgsys2: clock-controller@15820000 { 1328 compatible = "mediatek,mt8186-imgsys2"; 1329 reg = <0 0x15820000 0 0x1000>; 1330 #clock-cells = <1>; 1331 }; 1332 1333 larb11: smi@1582e000 { 1334 compatible = "mediatek,mt8186-smi-larb"; 1335 reg = <0 0x1582e000 0 0x1000>; 1336 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 1337 <&imgsys2 CLK_IMG2_LARB9_IMG2>; 1338 clock-names = "apb", "smi"; 1339 mediatek,larb-id = <11>; 1340 mediatek,smi = <&smi_common>; 1341 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 1342 }; 1343 1344 larb4: smi@1602e000 { 1345 compatible = "mediatek,mt8186-smi-larb"; 1346 reg = <0 0x1602e000 0 0x1000>; 1347 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 1348 <&vdecsys CLK_VDEC_LARB1_CKEN>; 1349 clock-names = "apb", "smi"; 1350 mediatek,larb-id = <4>; 1351 mediatek,smi = <&smi_common>; 1352 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 1353 }; 1354 1355 vdecsys: clock-controller@1602f000 { 1356 compatible = "mediatek,mt8186-vdecsys"; 1357 reg = <0 0x1602f000 0 0x1000>; 1358 #clock-cells = <1>; 1359 }; 1360 1361 vencsys: clock-controller@17000000 { 1362 compatible = "mediatek,mt8186-vencsys"; 1363 reg = <0 0x17000000 0 0x1000>; 1364 #clock-cells = <1>; 1365 }; 1366 1367 larb7: smi@17010000 { 1368 compatible = "mediatek,mt8186-smi-larb"; 1369 reg = <0 0x17010000 0 0x1000>; 1370 clocks = <&vencsys CLK_VENC_CKE1_VENC>, 1371 <&vencsys CLK_VENC_CKE1_VENC>; 1372 clock-names = "apb", "smi"; 1373 mediatek,larb-id = <7>; 1374 mediatek,smi = <&smi_common>; 1375 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 1376 }; 1377 1378 camsys: clock-controller@1a000000 { 1379 compatible = "mediatek,mt8186-camsys"; 1380 reg = <0 0x1a000000 0 0x1000>; 1381 #clock-cells = <1>; 1382 }; 1383 1384 larb13: smi@1a001000 { 1385 compatible = "mediatek,mt8186-smi-larb"; 1386 reg = <0 0x1a001000 0 0x1000>; 1387 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 1388 clock-names = "apb", "smi"; 1389 mediatek,larb-id = <13>; 1390 mediatek,smi = <&smi_common>; 1391 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1392 }; 1393 1394 larb14: smi@1a002000 { 1395 compatible = "mediatek,mt8186-smi-larb"; 1396 reg = <0 0x1a002000 0 0x1000>; 1397 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 1398 clock-names = "apb", "smi"; 1399 mediatek,larb-id = <14>; 1400 mediatek,smi = <&smi_common>; 1401 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1402 }; 1403 1404 larb16: smi@1a00f000 { 1405 compatible = "mediatek,mt8186-smi-larb"; 1406 reg = <0 0x1a00f000 0 0x1000>; 1407 clocks = <&camsys CLK_CAM_LARB14>, 1408 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 1409 clock-names = "apb", "smi"; 1410 mediatek,larb-id = <16>; 1411 mediatek,smi = <&smi_common>; 1412 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 1413 }; 1414 1415 larb17: smi@1a010000 { 1416 compatible = "mediatek,mt8186-smi-larb"; 1417 reg = <0 0x1a010000 0 0x1000>; 1418 clocks = <&camsys CLK_CAM_LARB13>, 1419 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 1420 clock-names = "apb", "smi"; 1421 mediatek,larb-id = <17>; 1422 mediatek,smi = <&smi_common>; 1423 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 1424 }; 1425 1426 camsys_rawa: clock-controller@1a04f000 { 1427 compatible = "mediatek,mt8186-camsys_rawa"; 1428 reg = <0 0x1a04f000 0 0x1000>; 1429 #clock-cells = <1>; 1430 }; 1431 1432 camsys_rawb: clock-controller@1a06f000 { 1433 compatible = "mediatek,mt8186-camsys_rawb"; 1434 reg = <0 0x1a06f000 0 0x1000>; 1435 #clock-cells = <1>; 1436 }; 1437 1438 mdpsys: clock-controller@1b000000 { 1439 compatible = "mediatek,mt8186-mdpsys"; 1440 reg = <0 0x1b000000 0 0x1000>; 1441 #clock-cells = <1>; 1442 }; 1443 1444 larb2: smi@1b002000 { 1445 compatible = "mediatek,mt8186-smi-larb"; 1446 reg = <0 0x1b002000 0 0x1000>; 1447 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 1448 clock-names = "apb", "smi"; 1449 mediatek,larb-id = <2>; 1450 mediatek,smi = <&smi_common>; 1451 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1452 }; 1453 1454 ipesys: clock-controller@1c000000 { 1455 compatible = "mediatek,mt8186-ipesys"; 1456 reg = <0 0x1c000000 0 0x1000>; 1457 #clock-cells = <1>; 1458 }; 1459 1460 larb20: smi@1c00f000 { 1461 compatible = "mediatek,mt8186-smi-larb"; 1462 reg = <0 0x1c00f000 0 0x1000>; 1463 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 1464 clock-names = "apb", "smi"; 1465 mediatek,larb-id = <20>; 1466 mediatek,smi = <&smi_common>; 1467 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1468 }; 1469 1470 larb19: smi@1c10f000 { 1471 compatible = "mediatek,mt8186-smi-larb"; 1472 reg = <0 0x1c10f000 0 0x1000>; 1473 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 1474 clock-names = "apb", "smi"; 1475 mediatek,larb-id = <19>; 1476 mediatek,smi = <&smi_common>; 1477 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1478 }; 1479 }; 1480}; 1481