1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/gce/mt8186-gce.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/memory/mt8186-memory-port.h> 12#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 13#include <dt-bindings/power/mt8186-power.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/reset/mt8186-resets.h> 16 17/ { 18 compatible = "mediatek,mt8186"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 ovl0 = &ovl0; 25 ovl_2l0 = &ovl_2l0; 26 rdma0 = &rdma0; 27 rdma1 = &rdma1; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu-map { 35 cluster0 { 36 core0 { 37 cpu = <&cpu0>; 38 }; 39 40 core1 { 41 cpu = <&cpu1>; 42 }; 43 44 core2 { 45 cpu = <&cpu2>; 46 }; 47 48 core3 { 49 cpu = <&cpu3>; 50 }; 51 52 core4 { 53 cpu = <&cpu4>; 54 }; 55 56 core5 { 57 cpu = <&cpu5>; 58 }; 59 60 core6 { 61 cpu = <&cpu6>; 62 }; 63 64 core7 { 65 cpu = <&cpu7>; 66 }; 67 }; 68 }; 69 70 cpu0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a55"; 73 reg = <0x000>; 74 enable-method = "psci"; 75 clock-frequency = <2000000000>; 76 capacity-dmips-mhz = <382>; 77 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 78 i-cache-size = <32768>; 79 i-cache-line-size = <64>; 80 i-cache-sets = <128>; 81 d-cache-size = <32768>; 82 d-cache-line-size = <64>; 83 d-cache-sets = <128>; 84 next-level-cache = <&l2_0>; 85 #cooling-cells = <2>; 86 }; 87 88 cpu1: cpu@100 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a55"; 91 reg = <0x100>; 92 enable-method = "psci"; 93 clock-frequency = <2000000000>; 94 capacity-dmips-mhz = <382>; 95 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 96 i-cache-size = <32768>; 97 i-cache-line-size = <64>; 98 i-cache-sets = <128>; 99 d-cache-size = <32768>; 100 d-cache-line-size = <64>; 101 d-cache-sets = <128>; 102 next-level-cache = <&l2_0>; 103 #cooling-cells = <2>; 104 }; 105 106 cpu2: cpu@200 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a55"; 109 reg = <0x200>; 110 enable-method = "psci"; 111 clock-frequency = <2000000000>; 112 capacity-dmips-mhz = <382>; 113 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 114 i-cache-size = <32768>; 115 i-cache-line-size = <64>; 116 i-cache-sets = <128>; 117 d-cache-size = <32768>; 118 d-cache-line-size = <64>; 119 d-cache-sets = <128>; 120 next-level-cache = <&l2_0>; 121 #cooling-cells = <2>; 122 }; 123 124 cpu3: cpu@300 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a55"; 127 reg = <0x300>; 128 enable-method = "psci"; 129 clock-frequency = <2000000000>; 130 capacity-dmips-mhz = <382>; 131 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 132 i-cache-size = <32768>; 133 i-cache-line-size = <64>; 134 i-cache-sets = <128>; 135 d-cache-size = <32768>; 136 d-cache-line-size = <64>; 137 d-cache-sets = <128>; 138 next-level-cache = <&l2_0>; 139 #cooling-cells = <2>; 140 }; 141 142 cpu4: cpu@400 { 143 device_type = "cpu"; 144 compatible = "arm,cortex-a55"; 145 reg = <0x400>; 146 enable-method = "psci"; 147 clock-frequency = <2000000000>; 148 capacity-dmips-mhz = <382>; 149 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 150 i-cache-size = <32768>; 151 i-cache-line-size = <64>; 152 i-cache-sets = <128>; 153 d-cache-size = <32768>; 154 d-cache-line-size = <64>; 155 d-cache-sets = <128>; 156 next-level-cache = <&l2_0>; 157 #cooling-cells = <2>; 158 }; 159 160 cpu5: cpu@500 { 161 device_type = "cpu"; 162 compatible = "arm,cortex-a55"; 163 reg = <0x500>; 164 enable-method = "psci"; 165 clock-frequency = <2000000000>; 166 capacity-dmips-mhz = <382>; 167 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 168 i-cache-size = <32768>; 169 i-cache-line-size = <64>; 170 i-cache-sets = <128>; 171 d-cache-size = <32768>; 172 d-cache-line-size = <64>; 173 d-cache-sets = <128>; 174 next-level-cache = <&l2_0>; 175 #cooling-cells = <2>; 176 }; 177 178 cpu6: cpu@600 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a76"; 181 reg = <0x600>; 182 enable-method = "psci"; 183 clock-frequency = <2050000000>; 184 capacity-dmips-mhz = <1024>; 185 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 186 i-cache-size = <65536>; 187 i-cache-line-size = <64>; 188 i-cache-sets = <256>; 189 d-cache-size = <65536>; 190 d-cache-line-size = <64>; 191 d-cache-sets = <256>; 192 next-level-cache = <&l2_1>; 193 #cooling-cells = <2>; 194 }; 195 196 cpu7: cpu@700 { 197 device_type = "cpu"; 198 compatible = "arm,cortex-a76"; 199 reg = <0x700>; 200 enable-method = "psci"; 201 clock-frequency = <2050000000>; 202 capacity-dmips-mhz = <1024>; 203 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 204 i-cache-size = <65536>; 205 i-cache-line-size = <64>; 206 i-cache-sets = <256>; 207 d-cache-size = <65536>; 208 d-cache-line-size = <64>; 209 d-cache-sets = <256>; 210 next-level-cache = <&l2_1>; 211 #cooling-cells = <2>; 212 }; 213 214 idle-states { 215 entry-method = "psci"; 216 217 cpu_ret_l: cpu-retention-l { 218 compatible = "arm,idle-state"; 219 arm,psci-suspend-param = <0x00010001>; 220 local-timer-stop; 221 entry-latency-us = <50>; 222 exit-latency-us = <100>; 223 min-residency-us = <1600>; 224 }; 225 226 cpu_ret_b: cpu-retention-b { 227 compatible = "arm,idle-state"; 228 arm,psci-suspend-param = <0x00010001>; 229 local-timer-stop; 230 entry-latency-us = <50>; 231 exit-latency-us = <100>; 232 min-residency-us = <1400>; 233 }; 234 235 cpu_off_l: cpu-off-l { 236 compatible = "arm,idle-state"; 237 arm,psci-suspend-param = <0x01010001>; 238 local-timer-stop; 239 entry-latency-us = <100>; 240 exit-latency-us = <250>; 241 min-residency-us = <2100>; 242 }; 243 244 cpu_off_b: cpu-off-b { 245 compatible = "arm,idle-state"; 246 arm,psci-suspend-param = <0x01010001>; 247 local-timer-stop; 248 entry-latency-us = <100>; 249 exit-latency-us = <250>; 250 min-residency-us = <1900>; 251 }; 252 }; 253 254 l2_0: l2-cache0 { 255 compatible = "cache"; 256 cache-level = <2>; 257 cache-size = <131072>; 258 cache-line-size = <64>; 259 cache-sets = <512>; 260 next-level-cache = <&l3_0>; 261 cache-unified; 262 }; 263 264 l2_1: l2-cache1 { 265 compatible = "cache"; 266 cache-level = <2>; 267 cache-size = <262144>; 268 cache-line-size = <64>; 269 cache-sets = <512>; 270 next-level-cache = <&l3_0>; 271 cache-unified; 272 }; 273 274 l3_0: l3-cache { 275 compatible = "cache"; 276 cache-level = <3>; 277 cache-size = <1048576>; 278 cache-line-size = <64>; 279 cache-sets = <1024>; 280 cache-unified; 281 }; 282 }; 283 284 clk13m: fixed-factor-clock-13m { 285 compatible = "fixed-factor-clock"; 286 #clock-cells = <0>; 287 clocks = <&clk26m>; 288 clock-div = <2>; 289 clock-mult = <1>; 290 clock-output-names = "clk13m"; 291 }; 292 293 clk26m: oscillator-26m { 294 compatible = "fixed-clock"; 295 #clock-cells = <0>; 296 clock-frequency = <26000000>; 297 clock-output-names = "clk26m"; 298 }; 299 300 clk32k: oscillator-32k { 301 compatible = "fixed-clock"; 302 #clock-cells = <0>; 303 clock-frequency = <32768>; 304 clock-output-names = "clk32k"; 305 }; 306 307 pmu-a55 { 308 compatible = "arm,cortex-a55-pmu"; 309 interrupt-parent = <&gic>; 310 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 311 }; 312 313 pmu-a76 { 314 compatible = "arm,cortex-a76-pmu"; 315 interrupt-parent = <&gic>; 316 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 317 }; 318 319 psci { 320 compatible = "arm,psci-1.0"; 321 method = "smc"; 322 }; 323 324 timer { 325 compatible = "arm,armv8-timer"; 326 interrupt-parent = <&gic>; 327 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 328 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 329 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 330 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 331 }; 332 333 soc { 334 #address-cells = <2>; 335 #size-cells = <2>; 336 compatible = "simple-bus"; 337 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 338 ranges; 339 340 gic: interrupt-controller@c000000 { 341 compatible = "arm,gic-v3"; 342 #interrupt-cells = <4>; 343 #redistributor-regions = <1>; 344 interrupt-parent = <&gic>; 345 interrupt-controller; 346 reg = <0 0x0c000000 0 0x40000>, 347 <0 0x0c040000 0 0x200000>; 348 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 349 350 ppi-partitions { 351 ppi_cluster0: interrupt-partition-0 { 352 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 353 }; 354 355 ppi_cluster1: interrupt-partition-1 { 356 affinity = <&cpu6 &cpu7>; 357 }; 358 }; 359 }; 360 361 mcusys: syscon@c53a000 { 362 compatible = "mediatek,mt8186-mcusys", "syscon"; 363 reg = <0 0xc53a000 0 0x1000>; 364 #clock-cells = <1>; 365 }; 366 367 topckgen: syscon@10000000 { 368 compatible = "mediatek,mt8186-topckgen", "syscon"; 369 reg = <0 0x10000000 0 0x1000>; 370 #clock-cells = <1>; 371 }; 372 373 infracfg_ao: syscon@10001000 { 374 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 375 reg = <0 0x10001000 0 0x1000>; 376 #clock-cells = <1>; 377 #reset-cells = <1>; 378 }; 379 380 pericfg: syscon@10003000 { 381 compatible = "mediatek,mt8186-pericfg", "syscon"; 382 reg = <0 0x10003000 0 0x1000>; 383 }; 384 385 pio: pinctrl@10005000 { 386 compatible = "mediatek,mt8186-pinctrl"; 387 reg = <0 0x10005000 0 0x1000>, 388 <0 0x10002000 0 0x0200>, 389 <0 0x10002200 0 0x0200>, 390 <0 0x10002400 0 0x0200>, 391 <0 0x10002600 0 0x0200>, 392 <0 0x10002a00 0 0x0200>, 393 <0 0x10002c00 0 0x0200>, 394 <0 0x1000b000 0 0x1000>; 395 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 396 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 397 gpio-controller; 398 #gpio-cells = <2>; 399 gpio-ranges = <&pio 0 0 185>; 400 interrupt-controller; 401 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 402 #interrupt-cells = <2>; 403 }; 404 405 scpsys: syscon@10006000 { 406 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 407 reg = <0 0x10006000 0 0x1000>; 408 409 /* System Power Manager */ 410 spm: power-controller { 411 compatible = "mediatek,mt8186-power-controller"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 #power-domain-cells = <1>; 415 416 /* power domain of the SoC */ 417 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 418 reg = <MT8186_POWER_DOMAIN_MFG0>; 419 clocks = <&topckgen CLK_TOP_MFG>; 420 clock-names = "mfg00"; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 #power-domain-cells = <1>; 424 425 power-domain@MT8186_POWER_DOMAIN_MFG1 { 426 reg = <MT8186_POWER_DOMAIN_MFG1>; 427 mediatek,infracfg = <&infracfg_ao>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 #power-domain-cells = <1>; 431 432 power-domain@MT8186_POWER_DOMAIN_MFG2 { 433 reg = <MT8186_POWER_DOMAIN_MFG2>; 434 #power-domain-cells = <0>; 435 }; 436 437 power-domain@MT8186_POWER_DOMAIN_MFG3 { 438 reg = <MT8186_POWER_DOMAIN_MFG3>; 439 #power-domain-cells = <0>; 440 }; 441 }; 442 }; 443 444 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 445 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 446 clocks = <&topckgen CLK_TOP_SENINF>, 447 <&topckgen CLK_TOP_SENINF1>; 448 clock-names = "csirx_top0", "csirx_top1"; 449 #power-domain-cells = <0>; 450 }; 451 452 power-domain@MT8186_POWER_DOMAIN_SSUSB { 453 reg = <MT8186_POWER_DOMAIN_SSUSB>; 454 #power-domain-cells = <0>; 455 }; 456 457 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 458 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 459 #power-domain-cells = <0>; 460 }; 461 462 power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 463 reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 464 clocks = <&topckgen CLK_TOP_AUDIODSP>, 465 <&topckgen CLK_TOP_ADSP_BUS>; 466 clock-names = "audioadsp", "adsp_bus"; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 #power-domain-cells = <1>; 470 471 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 472 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 #power-domain-cells = <1>; 476 477 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 478 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 479 mediatek,infracfg = <&infracfg_ao>; 480 #power-domain-cells = <0>; 481 }; 482 }; 483 }; 484 485 power-domain@MT8186_POWER_DOMAIN_CONN_ON { 486 reg = <MT8186_POWER_DOMAIN_CONN_ON>; 487 mediatek,infracfg = <&infracfg_ao>; 488 #power-domain-cells = <0>; 489 }; 490 491 power-domain@MT8186_POWER_DOMAIN_DIS { 492 reg = <MT8186_POWER_DOMAIN_DIS>; 493 clocks = <&topckgen CLK_TOP_DISP>, 494 <&topckgen CLK_TOP_MDP>, 495 <&mmsys CLK_MM_SMI_INFRA>, 496 <&mmsys CLK_MM_SMI_COMMON>, 497 <&mmsys CLK_MM_SMI_GALS>, 498 <&mmsys CLK_MM_SMI_IOMMU>; 499 clock-names = "disp", "mdp", "smi_infra", "smi_common", 500 "smi_gals", "smi_iommu"; 501 mediatek,infracfg = <&infracfg_ao>; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 #power-domain-cells = <1>; 505 506 power-domain@MT8186_POWER_DOMAIN_VDEC { 507 reg = <MT8186_POWER_DOMAIN_VDEC>; 508 clocks = <&topckgen CLK_TOP_VDEC>, 509 <&vdecsys CLK_VDEC_LARB1_CKEN>; 510 clock-names = "vdec0", "larb"; 511 mediatek,infracfg = <&infracfg_ao>; 512 #power-domain-cells = <0>; 513 }; 514 515 power-domain@MT8186_POWER_DOMAIN_CAM { 516 reg = <MT8186_POWER_DOMAIN_CAM>; 517 clocks = <&topckgen CLK_TOP_CAM>, 518 <&topckgen CLK_TOP_SENINF>, 519 <&topckgen CLK_TOP_SENINF1>, 520 <&topckgen CLK_TOP_SENINF2>, 521 <&topckgen CLK_TOP_SENINF3>, 522 <&topckgen CLK_TOP_CAMTM>, 523 <&camsys CLK_CAM2MM_GALS>; 524 clock-names = "cam-top", "cam0", "cam1", "cam2", 525 "cam3", "cam-tm", "gals"; 526 mediatek,infracfg = <&infracfg_ao>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 #power-domain-cells = <1>; 530 531 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 532 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 533 #power-domain-cells = <0>; 534 }; 535 536 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 537 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 538 #power-domain-cells = <0>; 539 }; 540 }; 541 542 power-domain@MT8186_POWER_DOMAIN_IMG { 543 reg = <MT8186_POWER_DOMAIN_IMG>; 544 clocks = <&topckgen CLK_TOP_IMG1>, 545 <&imgsys1 CLK_IMG1_GALS_IMG1>; 546 clock-names = "img-top", "gals"; 547 mediatek,infracfg = <&infracfg_ao>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 #power-domain-cells = <1>; 551 552 power-domain@MT8186_POWER_DOMAIN_IMG2 { 553 reg = <MT8186_POWER_DOMAIN_IMG2>; 554 #power-domain-cells = <0>; 555 }; 556 }; 557 558 power-domain@MT8186_POWER_DOMAIN_IPE { 559 reg = <MT8186_POWER_DOMAIN_IPE>; 560 clocks = <&topckgen CLK_TOP_IPE>, 561 <&ipesys CLK_IPE_LARB19>, 562 <&ipesys CLK_IPE_LARB20>, 563 <&ipesys CLK_IPE_SMI_SUBCOM>, 564 <&ipesys CLK_IPE_GALS_IPE>; 565 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", 566 "ipe-smi", "ipe-gals"; 567 mediatek,infracfg = <&infracfg_ao>; 568 #power-domain-cells = <0>; 569 }; 570 571 power-domain@MT8186_POWER_DOMAIN_VENC { 572 reg = <MT8186_POWER_DOMAIN_VENC>; 573 clocks = <&topckgen CLK_TOP_VENC>, 574 <&vencsys CLK_VENC_CKE1_VENC>; 575 clock-names = "venc0", "larb"; 576 mediatek,infracfg = <&infracfg_ao>; 577 #power-domain-cells = <0>; 578 }; 579 580 power-domain@MT8186_POWER_DOMAIN_WPE { 581 reg = <MT8186_POWER_DOMAIN_WPE>; 582 clocks = <&topckgen CLK_TOP_WPE>, 583 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 584 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 585 clock-names = "wpe0", "larb-ck", "larb-pclk"; 586 mediatek,infracfg = <&infracfg_ao>; 587 #power-domain-cells = <0>; 588 }; 589 }; 590 }; 591 }; 592 593 watchdog: watchdog@10007000 { 594 compatible = "mediatek,mt8186-wdt"; 595 mediatek,disable-extrst; 596 reg = <0 0x10007000 0 0x1000>; 597 #reset-cells = <1>; 598 }; 599 600 apmixedsys: syscon@1000c000 { 601 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 602 reg = <0 0x1000c000 0 0x1000>; 603 #clock-cells = <1>; 604 }; 605 606 pwrap: pwrap@1000d000 { 607 compatible = "mediatek,mt8186-pwrap", "syscon"; 608 reg = <0 0x1000d000 0 0x1000>; 609 reg-names = "pwrap"; 610 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 611 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 612 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 613 clock-names = "spi", "wrap"; 614 }; 615 616 spmi: spmi@10015000 { 617 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; 618 reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; 619 reg-names = "pmif", "spmimst"; 620 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 621 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 622 <&topckgen CLK_TOP_SPMI_MST>; 623 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; 624 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; 625 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 626 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>, 627 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>; 628 status = "disabled"; 629 }; 630 631 systimer: timer@10017000 { 632 compatible = "mediatek,mt8186-timer", 633 "mediatek,mt6765-timer"; 634 reg = <0 0x10017000 0 0x1000>; 635 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 636 clocks = <&clk13m>; 637 }; 638 639 gce: mailbox@1022c000 { 640 compatible = "mediatek,mt8186-gce"; 641 reg = <0 0X1022c000 0 0x4000>; 642 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 643 clock-names = "gce"; 644 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 645 #mbox-cells = <2>; 646 }; 647 648 scp: scp@10500000 { 649 compatible = "mediatek,mt8186-scp"; 650 reg = <0 0x10500000 0 0x40000>, 651 <0 0x105c0000 0 0x19080>; 652 reg-names = "sram", "cfg"; 653 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 654 }; 655 656 adsp: adsp@10680000 { 657 compatible = "mediatek,mt8186-dsp"; 658 reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, 659 <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; 660 reg-names = "cfg", "sram", "sec", "bus"; 661 clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; 662 clock-names = "audiodsp", "adsp_bus"; 663 assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, 664 <&topckgen CLK_TOP_ADSP_BUS>; 665 assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; 666 mbox-names = "rx", "tx"; 667 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 668 power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; 669 status = "disabled"; 670 }; 671 672 adsp_mailbox0: mailbox@10686000 { 673 compatible = "mediatek,mt8186-adsp-mbox"; 674 #mbox-cells = <0>; 675 reg = <0 0x10686100 0 0x1000>; 676 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 677 }; 678 679 adsp_mailbox1: mailbox@10687000 { 680 compatible = "mediatek,mt8186-adsp-mbox"; 681 #mbox-cells = <0>; 682 reg = <0 0x10687100 0 0x1000>; 683 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>; 684 }; 685 686 nor_flash: spi@11000000 { 687 compatible = "mediatek,mt8186-nor"; 688 reg = <0 0x11000000 0 0x1000>; 689 clocks = <&topckgen CLK_TOP_SPINOR>, 690 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 691 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 692 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 693 clock-names = "spi", "sf", "axi", "axi_s"; 694 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 695 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 696 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 697 status = "disabled"; 698 }; 699 700 auxadc: adc@11001000 { 701 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 702 reg = <0 0x11001000 0 0x1000>; 703 #io-channel-cells = <1>; 704 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 705 clock-names = "main"; 706 }; 707 708 uart0: serial@11002000 { 709 compatible = "mediatek,mt8186-uart", 710 "mediatek,mt6577-uart"; 711 reg = <0 0x11002000 0 0x1000>; 712 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 713 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 714 clock-names = "baud", "bus"; 715 status = "disabled"; 716 }; 717 718 uart1: serial@11003000 { 719 compatible = "mediatek,mt8186-uart", 720 "mediatek,mt6577-uart"; 721 reg = <0 0x11003000 0 0x1000>; 722 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 723 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 724 clock-names = "baud", "bus"; 725 status = "disabled"; 726 }; 727 728 i2c0: i2c@11007000 { 729 compatible = "mediatek,mt8186-i2c"; 730 reg = <0 0x11007000 0 0x1000>, 731 <0 0x10200100 0 0x100>; 732 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 733 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 734 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 735 clock-names = "main", "dma"; 736 clock-div = <1>; 737 #address-cells = <1>; 738 #size-cells = <0>; 739 status = "disabled"; 740 }; 741 742 i2c1: i2c@11008000 { 743 compatible = "mediatek,mt8186-i2c"; 744 reg = <0 0x11008000 0 0x1000>, 745 <0 0x10200200 0 0x100>; 746 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 747 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 748 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 749 clock-names = "main", "dma"; 750 clock-div = <1>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 status = "disabled"; 754 }; 755 756 i2c2: i2c@11009000 { 757 compatible = "mediatek,mt8186-i2c"; 758 reg = <0 0x11009000 0 0x1000>, 759 <0 0x10200300 0 0x180>; 760 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 761 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 762 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 763 clock-names = "main", "dma"; 764 clock-div = <1>; 765 #address-cells = <1>; 766 #size-cells = <0>; 767 status = "disabled"; 768 }; 769 770 i2c3: i2c@1100f000 { 771 compatible = "mediatek,mt8186-i2c"; 772 reg = <0 0x1100f000 0 0x1000>, 773 <0 0x10200480 0 0x100>; 774 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 775 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 776 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 777 clock-names = "main", "dma"; 778 clock-div = <1>; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 status = "disabled"; 782 }; 783 784 i2c4: i2c@11011000 { 785 compatible = "mediatek,mt8186-i2c"; 786 reg = <0 0x11011000 0 0x1000>, 787 <0 0x10200580 0 0x180>; 788 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 789 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 790 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 791 clock-names = "main", "dma"; 792 clock-div = <1>; 793 #address-cells = <1>; 794 #size-cells = <0>; 795 status = "disabled"; 796 }; 797 798 i2c5: i2c@11016000 { 799 compatible = "mediatek,mt8186-i2c"; 800 reg = <0 0x11016000 0 0x1000>, 801 <0 0x10200700 0 0x100>; 802 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 803 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 804 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 805 clock-names = "main", "dma"; 806 clock-div = <1>; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 status = "disabled"; 810 }; 811 812 i2c6: i2c@1100d000 { 813 compatible = "mediatek,mt8186-i2c"; 814 reg = <0 0x1100d000 0 0x1000>, 815 <0 0x10200800 0 0x100>; 816 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 817 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 818 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 819 clock-names = "main", "dma"; 820 clock-div = <1>; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 status = "disabled"; 824 }; 825 826 i2c7: i2c@11004000 { 827 compatible = "mediatek,mt8186-i2c"; 828 reg = <0 0x11004000 0 0x1000>, 829 <0 0x10200900 0 0x180>; 830 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 831 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 832 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 833 clock-names = "main", "dma"; 834 clock-div = <1>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 status = "disabled"; 838 }; 839 840 i2c8: i2c@11005000 { 841 compatible = "mediatek,mt8186-i2c"; 842 reg = <0 0x11005000 0 0x1000>, 843 <0 0x10200A80 0 0x180>; 844 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 845 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 846 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 847 clock-names = "main", "dma"; 848 clock-div = <1>; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 status = "disabled"; 852 }; 853 854 spi0: spi@1100a000 { 855 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 856 #address-cells = <1>; 857 #size-cells = <0>; 858 reg = <0 0x1100a000 0 0x1000>; 859 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 860 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 861 <&topckgen CLK_TOP_SPI>, 862 <&infracfg_ao CLK_INFRA_AO_SPI0>; 863 clock-names = "parent-clk", "sel-clk", "spi-clk"; 864 status = "disabled"; 865 }; 866 867 pwm0: pwm@1100e000 { 868 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 869 reg = <0 0x1100e000 0 0x1000>; 870 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 871 #pwm-cells = <2>; 872 clocks = <&topckgen CLK_TOP_DISP_PWM>, 873 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 874 clock-names = "main", "mm"; 875 status = "disabled"; 876 }; 877 878 spi1: spi@11010000 { 879 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 reg = <0 0x11010000 0 0x1000>; 883 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 884 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 885 <&topckgen CLK_TOP_SPI>, 886 <&infracfg_ao CLK_INFRA_AO_SPI1>; 887 clock-names = "parent-clk", "sel-clk", "spi-clk"; 888 status = "disabled"; 889 }; 890 891 spi2: spi@11012000 { 892 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 reg = <0 0x11012000 0 0x1000>; 896 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 897 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 898 <&topckgen CLK_TOP_SPI>, 899 <&infracfg_ao CLK_INFRA_AO_SPI2>; 900 clock-names = "parent-clk", "sel-clk", "spi-clk"; 901 status = "disabled"; 902 }; 903 904 spi3: spi@11013000 { 905 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 906 #address-cells = <1>; 907 #size-cells = <0>; 908 reg = <0 0x11013000 0 0x1000>; 909 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 910 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 911 <&topckgen CLK_TOP_SPI>, 912 <&infracfg_ao CLK_INFRA_AO_SPI3>; 913 clock-names = "parent-clk", "sel-clk", "spi-clk"; 914 status = "disabled"; 915 }; 916 917 spi4: spi@11014000 { 918 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 reg = <0 0x11014000 0 0x1000>; 922 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 923 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 924 <&topckgen CLK_TOP_SPI>, 925 <&infracfg_ao CLK_INFRA_AO_SPI4>; 926 clock-names = "parent-clk", "sel-clk", "spi-clk"; 927 status = "disabled"; 928 }; 929 930 spi5: spi@11015000 { 931 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 932 #address-cells = <1>; 933 #size-cells = <0>; 934 reg = <0 0x11015000 0 0x1000>; 935 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 936 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 937 <&topckgen CLK_TOP_SPI>, 938 <&infracfg_ao CLK_INFRA_AO_SPI5>; 939 clock-names = "parent-clk", "sel-clk", "spi-clk"; 940 status = "disabled"; 941 }; 942 943 imp_iic_wrap: clock-controller@11017000 { 944 compatible = "mediatek,mt8186-imp_iic_wrap"; 945 reg = <0 0x11017000 0 0x1000>; 946 #clock-cells = <1>; 947 }; 948 949 uart2: serial@11018000 { 950 compatible = "mediatek,mt8186-uart", 951 "mediatek,mt6577-uart"; 952 reg = <0 0x11018000 0 0x1000>; 953 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 954 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 955 clock-names = "baud", "bus"; 956 status = "disabled"; 957 }; 958 959 i2c9: i2c@11019000 { 960 compatible = "mediatek,mt8186-i2c"; 961 reg = <0 0x11019000 0 0x1000>, 962 <0 0x10200c00 0 0x180>; 963 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 964 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 965 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 966 clock-names = "main", "dma"; 967 clock-div = <1>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 status = "disabled"; 971 }; 972 973 afe: audio-controller@11210000 { 974 compatible = "mediatek,mt8186-sound"; 975 reg = <0 0x11210000 0 0x2000>; 976 clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, 977 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, 978 <&topckgen CLK_TOP_AUDIO>, 979 <&topckgen CLK_TOP_AUD_INTBUS>, 980 <&topckgen CLK_TOP_MAINPLL_D2_D4>, 981 <&topckgen CLK_TOP_AUD_1>, 982 <&apmixedsys CLK_APMIXED_APLL1>, 983 <&topckgen CLK_TOP_AUD_2>, 984 <&apmixedsys CLK_APMIXED_APLL2>, 985 <&topckgen CLK_TOP_AUD_ENGEN1>, 986 <&topckgen CLK_TOP_APLL1_D8>, 987 <&topckgen CLK_TOP_AUD_ENGEN2>, 988 <&topckgen CLK_TOP_APLL2_D8>, 989 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, 990 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, 991 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, 992 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, 993 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, 994 <&topckgen CLK_TOP_APLL12_CK_DIV0>, 995 <&topckgen CLK_TOP_APLL12_CK_DIV1>, 996 <&topckgen CLK_TOP_APLL12_CK_DIV2>, 997 <&topckgen CLK_TOP_APLL12_CK_DIV4>, 998 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, 999 <&topckgen CLK_TOP_AUDIO_H>, 1000 <&clk26m>; 1001 clock-names = "aud_infra_clk", 1002 "mtkaif_26m_clk", 1003 "top_mux_audio", 1004 "top_mux_audio_int", 1005 "top_mainpll_d2_d4", 1006 "top_mux_aud_1", 1007 "top_apll1_ck", 1008 "top_mux_aud_2", 1009 "top_apll2_ck", 1010 "top_mux_aud_eng1", 1011 "top_apll1_d8", 1012 "top_mux_aud_eng2", 1013 "top_apll2_d8", 1014 "top_i2s0_m_sel", 1015 "top_i2s1_m_sel", 1016 "top_i2s2_m_sel", 1017 "top_i2s4_m_sel", 1018 "top_tdm_m_sel", 1019 "top_apll12_div0", 1020 "top_apll12_div1", 1021 "top_apll12_div2", 1022 "top_apll12_div4", 1023 "top_apll12_div_tdm", 1024 "top_mux_audio_h", 1025 "top_clk26m_clk"; 1026 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1027 mediatek,apmixedsys = <&apmixedsys>; 1028 mediatek,infracfg = <&infracfg_ao>; 1029 mediatek,topckgen = <&topckgen>; 1030 resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; 1031 reset-names = "audiosys"; 1032 status = "disabled"; 1033 }; 1034 1035 ssusb0: usb@11201000 { 1036 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1037 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1038 reg-names = "mac", "ippc"; 1039 clocks = <&topckgen CLK_TOP_USB_TOP>, 1040 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1041 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1042 <&infracfg_ao CLK_INFRA_AO_ICUSB>; 1043 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1044 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>; 1045 phys = <&u2port0 PHY_TYPE_USB2>; 1046 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; 1047 #address-cells = <2>; 1048 #size-cells = <2>; 1049 ranges; 1050 status = "disabled"; 1051 1052 usb_host0: usb@11200000 { 1053 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1054 reg = <0 0x11200000 0 0x1000>; 1055 reg-names = "mac"; 1056 clocks = <&topckgen CLK_TOP_USB_TOP>, 1057 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, 1058 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, 1059 <&infracfg_ao CLK_INFRA_AO_ICUSB>, 1060 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; 1061 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1062 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 1063 mediatek,syscon-wakeup = <&pericfg 0x420 2>; 1064 wakeup-source; 1065 status = "disabled"; 1066 }; 1067 }; 1068 1069 mmc0: mmc@11230000 { 1070 compatible = "mediatek,mt8186-mmc", 1071 "mediatek,mt8183-mmc"; 1072 reg = <0 0x11230000 0 0x10000>, 1073 <0 0x11cd0000 0 0x1000>; 1074 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1075 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1076 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 1077 <&infracfg_ao CLK_INFRA_AO_MSDCFDE>; 1078 clock-names = "source", "hclk", "source_cg", "crypto"; 1079 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 1080 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 1081 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 1082 status = "disabled"; 1083 }; 1084 1085 mmc1: mmc@11240000 { 1086 compatible = "mediatek,mt8186-mmc", 1087 "mediatek,mt8183-mmc"; 1088 reg = <0 0x11240000 0 0x1000>, 1089 <0 0x11c90000 0 0x1000>; 1090 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1091 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1092 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1093 clock-names = "source", "hclk", "source_cg"; 1094 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 1095 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1096 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1097 status = "disabled"; 1098 }; 1099 1100 ssusb1: usb@11281000 { 1101 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; 1102 reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; 1103 reg-names = "mac", "ippc"; 1104 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1105 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1106 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1107 <&clk26m>; 1108 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 1109 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; 1110 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1111 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; 1112 #address-cells = <2>; 1113 #size-cells = <2>; 1114 ranges; 1115 status = "disabled"; 1116 1117 usb_host1: usb@11280000 { 1118 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; 1119 reg = <0 0x11280000 0 0x1000>; 1120 reg-names = "mac"; 1121 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, 1122 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, 1123 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, 1124 <&clk26m>, 1125 <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; 1126 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; 1127 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; 1128 mediatek,syscon-wakeup = <&pericfg 0x424 2>; 1129 wakeup-source; 1130 status = "disabled"; 1131 }; 1132 }; 1133 1134 u3phy0: t-phy@11c80000 { 1135 compatible = "mediatek,mt8186-tphy", 1136 "mediatek,generic-tphy-v2"; 1137 #address-cells = <1>; 1138 #size-cells = <1>; 1139 ranges = <0x0 0x0 0x11c80000 0x1000>; 1140 status = "disabled"; 1141 1142 u2port1: usb-phy@0 { 1143 reg = <0x0 0x700>; 1144 clocks = <&clk26m>; 1145 clock-names = "ref"; 1146 #phy-cells = <1>; 1147 }; 1148 1149 u3port1: usb-phy@700 { 1150 reg = <0x700 0x900>; 1151 clocks = <&clk26m>; 1152 clock-names = "ref"; 1153 #phy-cells = <1>; 1154 }; 1155 }; 1156 1157 u3phy1: t-phy@11ca0000 { 1158 compatible = "mediatek,mt8186-tphy", 1159 "mediatek,generic-tphy-v2"; 1160 #address-cells = <1>; 1161 #size-cells = <1>; 1162 ranges = <0x0 0x0 0x11ca0000 0x1000>; 1163 status = "disabled"; 1164 1165 u2port0: usb-phy@0 { 1166 reg = <0x0 0x700>; 1167 clocks = <&clk26m>; 1168 clock-names = "ref"; 1169 #phy-cells = <1>; 1170 mediatek,discth = <0x8>; 1171 }; 1172 }; 1173 1174 efuse: efuse@11cb0000 { 1175 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 1176 reg = <0 0x11cb0000 0 0x1000>; 1177 #address-cells = <1>; 1178 #size-cells = <1>; 1179 }; 1180 1181 mipi_tx0: dsi-phy@11cc0000 { 1182 compatible = "mediatek,mt8183-mipi-tx"; 1183 reg = <0 0x11cc0000 0 0x1000>; 1184 clocks = <&clk26m>; 1185 #clock-cells = <0>; 1186 #phy-cells = <0>; 1187 clock-output-names = "mipi_tx0_pll"; 1188 status = "disabled"; 1189 }; 1190 1191 mfgsys: clock-controller@13000000 { 1192 compatible = "mediatek,mt8186-mfgsys"; 1193 reg = <0 0x13000000 0 0x1000>; 1194 #clock-cells = <1>; 1195 }; 1196 1197 gpu: gpu@13040000 { 1198 compatible = "mediatek,mt8186-mali", 1199 "arm,mali-bifrost"; 1200 reg = <0 0x13040000 0 0x4000>; 1201 1202 clocks = <&mfgsys CLK_MFG_BG3D>; 1203 interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH 0>, 1204 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>, 1205 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 1206 interrupt-names = "job", "mmu", "gpu"; 1207 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>, 1208 <&spm MT8186_POWER_DOMAIN_MFG3>; 1209 power-domain-names = "core0", "core1"; 1210 #cooling-cells = <2>; 1211 status = "disabled"; 1212 }; 1213 1214 mmsys: syscon@14000000 { 1215 compatible = "mediatek,mt8186-mmsys", "syscon"; 1216 reg = <0 0x14000000 0 0x1000>; 1217 #clock-cells = <1>; 1218 #reset-cells = <1>; 1219 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1220 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1221 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1222 }; 1223 1224 mutex: mutex@14001000 { 1225 compatible = "mediatek,mt8186-disp-mutex"; 1226 reg = <0 0x14001000 0 0x1000>; 1227 clocks = <&mmsys CLK_MM_DISP_MUTEX0>; 1228 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>; 1229 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1230 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, 1231 <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; 1232 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1233 }; 1234 1235 smi_common: smi@14002000 { 1236 compatible = "mediatek,mt8186-smi-common"; 1237 reg = <0 0x14002000 0 0x1000>; 1238 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 1239 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 1240 clock-names = "apb", "smi", "gals0", "gals1"; 1241 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1242 }; 1243 1244 larb0: smi@14003000 { 1245 compatible = "mediatek,mt8186-smi-larb"; 1246 reg = <0 0x14003000 0 0x1000>; 1247 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1248 <&mmsys CLK_MM_SMI_COMMON>; 1249 clock-names = "apb", "smi"; 1250 mediatek,larb-id = <0>; 1251 mediatek,smi = <&smi_common>; 1252 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1253 }; 1254 1255 larb1: smi@14004000 { 1256 compatible = "mediatek,mt8186-smi-larb"; 1257 reg = <0 0x14004000 0 0x1000>; 1258 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1259 <&mmsys CLK_MM_SMI_COMMON>; 1260 clock-names = "apb", "smi"; 1261 mediatek,larb-id = <1>; 1262 mediatek,smi = <&smi_common>; 1263 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1264 }; 1265 1266 ovl0: ovl@14005000 { 1267 compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl"; 1268 reg = <0 0x14005000 0 0x1000>; 1269 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1270 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; 1271 iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; 1272 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1273 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1274 }; 1275 1276 ovl_2l0: ovl@14006000 { 1277 compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l"; 1278 reg = <0 0x14006000 0 0x1000>; 1279 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1280 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 1281 iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; 1282 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1283 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1284 }; 1285 1286 rdma0: rdma@14007000 { 1287 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1288 reg = <0 0x14007000 0 0x1000>; 1289 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1290 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>; 1291 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; 1292 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; 1293 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1294 }; 1295 1296 color: color@14009000 { 1297 compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color"; 1298 reg = <0 0x14009000 0 0x1000>; 1299 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1300 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>; 1301 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1302 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1303 }; 1304 1305 dpi: dpi@1400a000 { 1306 compatible = "mediatek,mt8186-dpi"; 1307 reg = <0 0x1400a000 0 0x1000>; 1308 clocks = <&topckgen CLK_TOP_DPI>, 1309 <&mmsys CLK_MM_DISP_DPI>, 1310 <&apmixedsys CLK_APMIXED_TVDPLL>; 1311 clock-names = "pixel", "engine", "pll"; 1312 assigned-clocks = <&topckgen CLK_TOP_DPI>; 1313 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; 1314 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; 1315 status = "disabled"; 1316 1317 port { 1318 dpi_out: endpoint { }; 1319 }; 1320 }; 1321 1322 ccorr: ccorr@1400b000 { 1323 compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 1324 reg = <0 0x1400b000 0 0x1000>; 1325 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1326 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH 0>; 1327 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1328 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1329 }; 1330 1331 aal: aal@1400c000 { 1332 compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal"; 1333 reg = <0 0x1400c000 0 0x1000>; 1334 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1335 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>; 1336 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1337 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1338 }; 1339 1340 gamma: gamma@1400d000 { 1341 compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma"; 1342 reg = <0 0x1400d000 0 0x1000>; 1343 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1344 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 1345 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1346 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1347 }; 1348 1349 postmask: postmask@1400e000 { 1350 compatible = "mediatek,mt8186-disp-postmask", 1351 "mediatek,mt8192-disp-postmask"; 1352 reg = <0 0x1400e000 0 0x1000>; 1353 clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; 1354 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 1355 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1356 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1357 }; 1358 1359 dither: dither@1400f000 { 1360 compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither"; 1361 reg = <0 0x1400f000 0 0x1000>; 1362 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 1363 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>; 1364 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1365 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1366 }; 1367 1368 dsi0: dsi@14013000 { 1369 compatible = "mediatek,mt8186-dsi"; 1370 reg = <0 0x14013000 0 0x1000>; 1371 clocks = <&mmsys CLK_MM_DSI0>, 1372 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 1373 <&mipi_tx0>; 1374 clock-names = "engine", "digital", "hs"; 1375 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 1376 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1377 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 1378 phys = <&mipi_tx0>; 1379 phy-names = "dphy"; 1380 status = "disabled"; 1381 1382 port { 1383 dsi_out: endpoint { }; 1384 }; 1385 }; 1386 1387 iommu_mm: iommu@14016000 { 1388 compatible = "mediatek,mt8186-iommu-mm"; 1389 reg = <0 0x14016000 0 0x1000>; 1390 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1391 clock-names = "bclk"; 1392 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1393 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1394 &larb7 &larb8 &larb9 &larb11 1395 &larb13 &larb14 &larb16 &larb17 1396 &larb19 &larb20>; 1397 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1398 #iommu-cells = <1>; 1399 }; 1400 1401 rdma1: rdma@1401f000 { 1402 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma"; 1403 reg = <0 0x1401f000 0 0x1000>; 1404 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1405 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 0>; 1406 iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; 1407 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>; 1408 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1409 }; 1410 1411 wpesys: clock-controller@14020000 { 1412 compatible = "mediatek,mt8186-wpesys"; 1413 reg = <0 0x14020000 0 0x1000>; 1414 #clock-cells = <1>; 1415 }; 1416 1417 larb8: smi@14023000 { 1418 compatible = "mediatek,mt8186-smi-larb"; 1419 reg = <0 0x14023000 0 0x1000>; 1420 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1421 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1422 clock-names = "apb", "smi"; 1423 mediatek,larb-id = <8>; 1424 mediatek,smi = <&smi_common>; 1425 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1426 }; 1427 1428 imgsys1: clock-controller@15020000 { 1429 compatible = "mediatek,mt8186-imgsys1"; 1430 reg = <0 0x15020000 0 0x1000>; 1431 #clock-cells = <1>; 1432 }; 1433 1434 larb9: smi@1502e000 { 1435 compatible = "mediatek,mt8186-smi-larb"; 1436 reg = <0 0x1502e000 0 0x1000>; 1437 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1438 <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1439 clock-names = "apb", "smi"; 1440 mediatek,larb-id = <9>; 1441 mediatek,smi = <&smi_common>; 1442 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 1443 }; 1444 1445 imgsys2: clock-controller@15820000 { 1446 compatible = "mediatek,mt8186-imgsys2"; 1447 reg = <0 0x15820000 0 0x1000>; 1448 #clock-cells = <1>; 1449 }; 1450 1451 larb11: smi@1582e000 { 1452 compatible = "mediatek,mt8186-smi-larb"; 1453 reg = <0 0x1582e000 0 0x1000>; 1454 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 1455 <&imgsys2 CLK_IMG2_LARB9_IMG2>; 1456 clock-names = "apb", "smi"; 1457 mediatek,larb-id = <11>; 1458 mediatek,smi = <&smi_common>; 1459 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 1460 }; 1461 1462 larb4: smi@1602e000 { 1463 compatible = "mediatek,mt8186-smi-larb"; 1464 reg = <0 0x1602e000 0 0x1000>; 1465 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 1466 <&vdecsys CLK_VDEC_LARB1_CKEN>; 1467 clock-names = "apb", "smi"; 1468 mediatek,larb-id = <4>; 1469 mediatek,smi = <&smi_common>; 1470 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 1471 }; 1472 1473 vdecsys: clock-controller@1602f000 { 1474 compatible = "mediatek,mt8186-vdecsys"; 1475 reg = <0 0x1602f000 0 0x1000>; 1476 #clock-cells = <1>; 1477 }; 1478 1479 vencsys: clock-controller@17000000 { 1480 compatible = "mediatek,mt8186-vencsys"; 1481 reg = <0 0x17000000 0 0x1000>; 1482 #clock-cells = <1>; 1483 }; 1484 1485 larb7: smi@17010000 { 1486 compatible = "mediatek,mt8186-smi-larb"; 1487 reg = <0 0x17010000 0 0x1000>; 1488 clocks = <&vencsys CLK_VENC_CKE1_VENC>, 1489 <&vencsys CLK_VENC_CKE1_VENC>; 1490 clock-names = "apb", "smi"; 1491 mediatek,larb-id = <7>; 1492 mediatek,smi = <&smi_common>; 1493 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 1494 }; 1495 1496 camsys: clock-controller@1a000000 { 1497 compatible = "mediatek,mt8186-camsys"; 1498 reg = <0 0x1a000000 0 0x1000>; 1499 #clock-cells = <1>; 1500 }; 1501 1502 larb13: smi@1a001000 { 1503 compatible = "mediatek,mt8186-smi-larb"; 1504 reg = <0 0x1a001000 0 0x1000>; 1505 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 1506 clock-names = "apb", "smi"; 1507 mediatek,larb-id = <13>; 1508 mediatek,smi = <&smi_common>; 1509 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1510 }; 1511 1512 larb14: smi@1a002000 { 1513 compatible = "mediatek,mt8186-smi-larb"; 1514 reg = <0 0x1a002000 0 0x1000>; 1515 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 1516 clock-names = "apb", "smi"; 1517 mediatek,larb-id = <14>; 1518 mediatek,smi = <&smi_common>; 1519 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1520 }; 1521 1522 larb16: smi@1a00f000 { 1523 compatible = "mediatek,mt8186-smi-larb"; 1524 reg = <0 0x1a00f000 0 0x1000>; 1525 clocks = <&camsys CLK_CAM_LARB14>, 1526 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 1527 clock-names = "apb", "smi"; 1528 mediatek,larb-id = <16>; 1529 mediatek,smi = <&smi_common>; 1530 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 1531 }; 1532 1533 larb17: smi@1a010000 { 1534 compatible = "mediatek,mt8186-smi-larb"; 1535 reg = <0 0x1a010000 0 0x1000>; 1536 clocks = <&camsys CLK_CAM_LARB13>, 1537 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 1538 clock-names = "apb", "smi"; 1539 mediatek,larb-id = <17>; 1540 mediatek,smi = <&smi_common>; 1541 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 1542 }; 1543 1544 camsys_rawa: clock-controller@1a04f000 { 1545 compatible = "mediatek,mt8186-camsys_rawa"; 1546 reg = <0 0x1a04f000 0 0x1000>; 1547 #clock-cells = <1>; 1548 }; 1549 1550 camsys_rawb: clock-controller@1a06f000 { 1551 compatible = "mediatek,mt8186-camsys_rawb"; 1552 reg = <0 0x1a06f000 0 0x1000>; 1553 #clock-cells = <1>; 1554 }; 1555 1556 mdpsys: clock-controller@1b000000 { 1557 compatible = "mediatek,mt8186-mdpsys"; 1558 reg = <0 0x1b000000 0 0x1000>; 1559 #clock-cells = <1>; 1560 }; 1561 1562 larb2: smi@1b002000 { 1563 compatible = "mediatek,mt8186-smi-larb"; 1564 reg = <0 0x1b002000 0 0x1000>; 1565 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 1566 clock-names = "apb", "smi"; 1567 mediatek,larb-id = <2>; 1568 mediatek,smi = <&smi_common>; 1569 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1570 }; 1571 1572 ipesys: clock-controller@1c000000 { 1573 compatible = "mediatek,mt8186-ipesys"; 1574 reg = <0 0x1c000000 0 0x1000>; 1575 #clock-cells = <1>; 1576 }; 1577 1578 larb20: smi@1c00f000 { 1579 compatible = "mediatek,mt8186-smi-larb"; 1580 reg = <0 0x1c00f000 0 0x1000>; 1581 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 1582 clock-names = "apb", "smi"; 1583 mediatek,larb-id = <20>; 1584 mediatek,smi = <&smi_common>; 1585 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1586 }; 1587 1588 larb19: smi@1c10f000 { 1589 compatible = "mediatek,mt8186-smi-larb"; 1590 reg = <0 0x1c10f000 0 0x1000>; 1591 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 1592 clock-names = "apb", "smi"; 1593 mediatek,larb-id = <19>; 1594 mediatek,smi = <&smi_common>; 1595 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1596 }; 1597 }; 1598}; 1599