1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Copyright (C) 2022 MediaTek Inc.
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
5 */
6/dts-v1/;
7#include <dt-bindings/clock/mt8186-clk.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/memory/mt8186-memory-port.h>
11#include <dt-bindings/pinctrl/mt8186-pinfunc.h>
12#include <dt-bindings/power/mt8186-power.h>
13#include <dt-bindings/phy/phy.h>
14#include <dt-bindings/reset/mt8186-resets.h>
15
16/ {
17	compatible = "mediatek,mt8186";
18	interrupt-parent = <&gic>;
19	#address-cells = <2>;
20	#size-cells = <2>;
21
22	cpus {
23		#address-cells = <1>;
24		#size-cells = <0>;
25
26		cpu-map {
27			cluster0 {
28				core0 {
29					cpu = <&cpu0>;
30				};
31
32				core1 {
33					cpu = <&cpu1>;
34				};
35
36				core2 {
37					cpu = <&cpu2>;
38				};
39
40				core3 {
41					cpu = <&cpu3>;
42				};
43
44				core4 {
45					cpu = <&cpu4>;
46				};
47
48				core5 {
49					cpu = <&cpu5>;
50				};
51
52				core6 {
53					cpu = <&cpu6>;
54				};
55
56				core7 {
57					cpu = <&cpu7>;
58				};
59			};
60		};
61
62		cpu0: cpu@0 {
63			device_type = "cpu";
64			compatible = "arm,cortex-a55";
65			reg = <0x000>;
66			enable-method = "psci";
67			clock-frequency = <2000000000>;
68			capacity-dmips-mhz = <382>;
69			cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
70			i-cache-size = <32768>;
71			i-cache-line-size = <64>;
72			i-cache-sets = <128>;
73			d-cache-size = <32768>;
74			d-cache-line-size = <64>;
75			d-cache-sets = <128>;
76			next-level-cache = <&l2_0>;
77			#cooling-cells = <2>;
78		};
79
80		cpu1: cpu@100 {
81			device_type = "cpu";
82			compatible = "arm,cortex-a55";
83			reg = <0x100>;
84			enable-method = "psci";
85			clock-frequency = <2000000000>;
86			capacity-dmips-mhz = <382>;
87			cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
88			i-cache-size = <32768>;
89			i-cache-line-size = <64>;
90			i-cache-sets = <128>;
91			d-cache-size = <32768>;
92			d-cache-line-size = <64>;
93			d-cache-sets = <128>;
94			next-level-cache = <&l2_0>;
95			#cooling-cells = <2>;
96		};
97
98		cpu2: cpu@200 {
99			device_type = "cpu";
100			compatible = "arm,cortex-a55";
101			reg = <0x200>;
102			enable-method = "psci";
103			clock-frequency = <2000000000>;
104			capacity-dmips-mhz = <382>;
105			cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
106			i-cache-size = <32768>;
107			i-cache-line-size = <64>;
108			i-cache-sets = <128>;
109			d-cache-size = <32768>;
110			d-cache-line-size = <64>;
111			d-cache-sets = <128>;
112			next-level-cache = <&l2_0>;
113			#cooling-cells = <2>;
114		};
115
116		cpu3: cpu@300 {
117			device_type = "cpu";
118			compatible = "arm,cortex-a55";
119			reg = <0x300>;
120			enable-method = "psci";
121			clock-frequency = <2000000000>;
122			capacity-dmips-mhz = <382>;
123			cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
124			i-cache-size = <32768>;
125			i-cache-line-size = <64>;
126			i-cache-sets = <128>;
127			d-cache-size = <32768>;
128			d-cache-line-size = <64>;
129			d-cache-sets = <128>;
130			next-level-cache = <&l2_0>;
131			#cooling-cells = <2>;
132		};
133
134		cpu4: cpu@400 {
135			device_type = "cpu";
136			compatible = "arm,cortex-a55";
137			reg = <0x400>;
138			enable-method = "psci";
139			clock-frequency = <2000000000>;
140			capacity-dmips-mhz = <382>;
141			cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
142			i-cache-size = <32768>;
143			i-cache-line-size = <64>;
144			i-cache-sets = <128>;
145			d-cache-size = <32768>;
146			d-cache-line-size = <64>;
147			d-cache-sets = <128>;
148			next-level-cache = <&l2_0>;
149			#cooling-cells = <2>;
150		};
151
152		cpu5: cpu@500 {
153			device_type = "cpu";
154			compatible = "arm,cortex-a55";
155			reg = <0x500>;
156			enable-method = "psci";
157			clock-frequency = <2000000000>;
158			capacity-dmips-mhz = <382>;
159			cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
160			i-cache-size = <32768>;
161			i-cache-line-size = <64>;
162			i-cache-sets = <128>;
163			d-cache-size = <32768>;
164			d-cache-line-size = <64>;
165			d-cache-sets = <128>;
166			next-level-cache = <&l2_0>;
167			#cooling-cells = <2>;
168		};
169
170		cpu6: cpu@600 {
171			device_type = "cpu";
172			compatible = "arm,cortex-a76";
173			reg = <0x600>;
174			enable-method = "psci";
175			clock-frequency = <2050000000>;
176			capacity-dmips-mhz = <1024>;
177			cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
178			i-cache-size = <65536>;
179			i-cache-line-size = <64>;
180			i-cache-sets = <256>;
181			d-cache-size = <65536>;
182			d-cache-line-size = <64>;
183			d-cache-sets = <256>;
184			next-level-cache = <&l2_1>;
185			#cooling-cells = <2>;
186		};
187
188		cpu7: cpu@700 {
189			device_type = "cpu";
190			compatible = "arm,cortex-a76";
191			reg = <0x700>;
192			enable-method = "psci";
193			clock-frequency = <2050000000>;
194			capacity-dmips-mhz = <1024>;
195			cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
196			i-cache-size = <65536>;
197			i-cache-line-size = <64>;
198			i-cache-sets = <256>;
199			d-cache-size = <65536>;
200			d-cache-line-size = <64>;
201			d-cache-sets = <256>;
202			next-level-cache = <&l2_1>;
203			#cooling-cells = <2>;
204		};
205
206		idle-states {
207			entry-method = "psci";
208
209			cpu_ret_l: cpu-retention-l {
210				compatible = "arm,idle-state";
211				arm,psci-suspend-param = <0x00010001>;
212				local-timer-stop;
213				entry-latency-us = <50>;
214				exit-latency-us = <100>;
215				min-residency-us = <1600>;
216			};
217
218			cpu_ret_b: cpu-retention-b {
219				compatible = "arm,idle-state";
220				arm,psci-suspend-param = <0x00010001>;
221				local-timer-stop;
222				entry-latency-us = <50>;
223				exit-latency-us = <100>;
224				min-residency-us = <1400>;
225			};
226
227			cpu_off_l: cpu-off-l {
228				compatible = "arm,idle-state";
229				arm,psci-suspend-param = <0x01010001>;
230				local-timer-stop;
231				entry-latency-us = <100>;
232				exit-latency-us = <250>;
233				min-residency-us = <2100>;
234			};
235
236			cpu_off_b: cpu-off-b {
237				compatible = "arm,idle-state";
238				arm,psci-suspend-param = <0x01010001>;
239				local-timer-stop;
240				entry-latency-us = <100>;
241				exit-latency-us = <250>;
242				min-residency-us = <1900>;
243			};
244		};
245
246		l2_0: l2-cache0 {
247			compatible = "cache";
248			cache-level = <2>;
249			cache-size = <131072>;
250			cache-line-size = <64>;
251			cache-sets = <512>;
252			next-level-cache = <&l3_0>;
253		};
254
255		l2_1: l2-cache1 {
256			compatible = "cache";
257			cache-level = <2>;
258			cache-size = <262144>;
259			cache-line-size = <64>;
260			cache-sets = <512>;
261			next-level-cache = <&l3_0>;
262		};
263
264		l3_0: l3-cache {
265			compatible = "cache";
266			cache-level = <3>;
267			cache-size = <1048576>;
268			cache-line-size = <64>;
269			cache-sets = <1024>;
270			cache-unified;
271		};
272	};
273
274	clk13m: fixed-factor-clock-13m {
275		compatible = "fixed-factor-clock";
276		#clock-cells = <0>;
277		clocks = <&clk26m>;
278		clock-div = <2>;
279		clock-mult = <1>;
280		clock-output-names = "clk13m";
281	};
282
283	clk26m: oscillator-26m {
284		compatible = "fixed-clock";
285		#clock-cells = <0>;
286		clock-frequency = <26000000>;
287		clock-output-names = "clk26m";
288	};
289
290	clk32k: oscillator-32k {
291		compatible = "fixed-clock";
292		#clock-cells = <0>;
293		clock-frequency = <32768>;
294		clock-output-names = "clk32k";
295	};
296
297	pmu-a55 {
298		compatible = "arm,cortex-a55-pmu";
299		interrupt-parent = <&gic>;
300		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
301	};
302
303	pmu-a76 {
304		compatible = "arm,cortex-a76-pmu";
305		interrupt-parent = <&gic>;
306		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
307	};
308
309	psci {
310		compatible = "arm,psci-1.0";
311		method = "smc";
312	};
313
314	timer {
315		compatible = "arm,armv8-timer";
316		interrupt-parent = <&gic>;
317		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
318			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
319			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
320			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
321	};
322
323	soc {
324		#address-cells = <2>;
325		#size-cells = <2>;
326		compatible = "simple-bus";
327		ranges;
328
329		gic: interrupt-controller@c000000 {
330			compatible = "arm,gic-v3";
331			#interrupt-cells = <4>;
332			#redistributor-regions = <1>;
333			interrupt-parent = <&gic>;
334			interrupt-controller;
335			reg = <0 0x0c000000 0 0x40000>,
336			      <0 0x0c040000 0 0x200000>;
337			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
338
339			ppi-partitions {
340				ppi_cluster0: interrupt-partition-0 {
341					affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>;
342				};
343
344				ppi_cluster1: interrupt-partition-1 {
345					affinity = <&cpu6 &cpu7>;
346				};
347			};
348		};
349
350		mcusys: syscon@c53a000 {
351			compatible = "mediatek,mt8186-mcusys", "syscon";
352			reg = <0 0xc53a000 0 0x1000>;
353			#clock-cells = <1>;
354		};
355
356		topckgen: syscon@10000000 {
357			compatible = "mediatek,mt8186-topckgen", "syscon";
358			reg = <0 0x10000000 0 0x1000>;
359			#clock-cells = <1>;
360		};
361
362		infracfg_ao: syscon@10001000 {
363			compatible = "mediatek,mt8186-infracfg_ao", "syscon";
364			reg = <0 0x10001000 0 0x1000>;
365			#clock-cells = <1>;
366			#reset-cells = <1>;
367		};
368
369		pericfg: syscon@10003000 {
370			compatible = "mediatek,mt8186-pericfg", "syscon";
371			reg = <0 0x10003000 0 0x1000>;
372		};
373
374		pio: pinctrl@10005000 {
375			compatible = "mediatek,mt8186-pinctrl";
376			reg = <0 0x10005000 0 0x1000>,
377			      <0 0x10002000 0 0x0200>,
378			      <0 0x10002200 0 0x0200>,
379			      <0 0x10002400 0 0x0200>,
380			      <0 0x10002600 0 0x0200>,
381			      <0 0x10002a00 0 0x0200>,
382			      <0 0x10002c00 0 0x0200>,
383			      <0 0x1000b000 0 0x1000>;
384			reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb",
385				    "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint";
386			gpio-controller;
387			#gpio-cells = <2>;
388			gpio-ranges = <&pio 0 0 185>;
389			interrupt-controller;
390			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
391			#interrupt-cells = <2>;
392		};
393
394		scpsys: syscon@10006000 {
395			compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd";
396			reg = <0 0x10006000 0 0x1000>;
397
398			/* System Power Manager */
399			spm: power-controller {
400				compatible = "mediatek,mt8186-power-controller";
401				#address-cells = <1>;
402				#size-cells = <0>;
403				#power-domain-cells = <1>;
404
405				/* power domain of the SoC */
406				mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {
407					reg = <MT8186_POWER_DOMAIN_MFG0>;
408					clocks = <&topckgen CLK_TOP_MFG>;
409					clock-names = "mfg00";
410					#address-cells = <1>;
411					#size-cells = <0>;
412					#power-domain-cells = <1>;
413
414					power-domain@MT8186_POWER_DOMAIN_MFG1 {
415						reg = <MT8186_POWER_DOMAIN_MFG1>;
416						mediatek,infracfg = <&infracfg_ao>;
417						#address-cells = <1>;
418						#size-cells = <0>;
419						#power-domain-cells = <1>;
420
421						power-domain@MT8186_POWER_DOMAIN_MFG2 {
422							reg = <MT8186_POWER_DOMAIN_MFG2>;
423							#power-domain-cells = <0>;
424						};
425
426						power-domain@MT8186_POWER_DOMAIN_MFG3 {
427							reg = <MT8186_POWER_DOMAIN_MFG3>;
428							#power-domain-cells = <0>;
429						};
430					};
431				};
432
433				power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP {
434					reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>;
435					clocks = <&topckgen CLK_TOP_SENINF>,
436						 <&topckgen CLK_TOP_SENINF1>;
437					clock-names = "csirx_top0", "csirx_top1";
438					#power-domain-cells = <0>;
439				};
440
441				power-domain@MT8186_POWER_DOMAIN_SSUSB {
442					reg = <MT8186_POWER_DOMAIN_SSUSB>;
443					#power-domain-cells = <0>;
444				};
445
446				power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 {
447					reg = <MT8186_POWER_DOMAIN_SSUSB_P1>;
448					#power-domain-cells = <0>;
449				};
450
451				power-domain@MT8186_POWER_DOMAIN_ADSP_AO {
452					reg = <MT8186_POWER_DOMAIN_ADSP_AO>;
453					clocks = <&topckgen CLK_TOP_AUDIODSP>,
454						 <&topckgen CLK_TOP_ADSP_BUS>;
455					clock-names = "audioadsp", "adsp_bus";
456					#address-cells = <1>;
457					#size-cells = <0>;
458					#power-domain-cells = <1>;
459
460					power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA {
461						reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>;
462						#address-cells = <1>;
463						#size-cells = <0>;
464						#power-domain-cells = <1>;
465
466						power-domain@MT8186_POWER_DOMAIN_ADSP_TOP {
467							reg = <MT8186_POWER_DOMAIN_ADSP_TOP>;
468							mediatek,infracfg = <&infracfg_ao>;
469							#power-domain-cells = <0>;
470						};
471					};
472				};
473
474				power-domain@MT8186_POWER_DOMAIN_CONN_ON {
475					reg = <MT8186_POWER_DOMAIN_CONN_ON>;
476					mediatek,infracfg = <&infracfg_ao>;
477					#power-domain-cells = <0>;
478				};
479
480				power-domain@MT8186_POWER_DOMAIN_DIS {
481					reg = <MT8186_POWER_DOMAIN_DIS>;
482					clocks = <&topckgen CLK_TOP_DISP>,
483						 <&topckgen CLK_TOP_MDP>,
484						 <&mmsys CLK_MM_SMI_INFRA>,
485						 <&mmsys CLK_MM_SMI_COMMON>,
486						 <&mmsys CLK_MM_SMI_GALS>,
487						 <&mmsys CLK_MM_SMI_IOMMU>;
488					clock-names = "disp", "mdp", "smi_infra", "smi_common",
489						     "smi_gals", "smi_iommu";
490					mediatek,infracfg = <&infracfg_ao>;
491					#address-cells = <1>;
492					#size-cells = <0>;
493					#power-domain-cells = <1>;
494
495					power-domain@MT8186_POWER_DOMAIN_VDEC {
496						reg = <MT8186_POWER_DOMAIN_VDEC>;
497						clocks = <&topckgen CLK_TOP_VDEC>,
498							 <&vdecsys CLK_VDEC_LARB1_CKEN>;
499						clock-names = "vdec0", "larb";
500						mediatek,infracfg = <&infracfg_ao>;
501						#power-domain-cells = <0>;
502					};
503
504					power-domain@MT8186_POWER_DOMAIN_CAM {
505						reg = <MT8186_POWER_DOMAIN_CAM>;
506						clocks = <&topckgen CLK_TOP_CAM>,
507							 <&topckgen CLK_TOP_SENINF>,
508							 <&topckgen CLK_TOP_SENINF1>,
509							 <&topckgen CLK_TOP_SENINF2>,
510							 <&topckgen CLK_TOP_SENINF3>,
511							 <&topckgen CLK_TOP_CAMTM>,
512							 <&camsys CLK_CAM2MM_GALS>;
513						clock-names = "cam-top", "cam0", "cam1", "cam2",
514							     "cam3", "cam-tm", "gals";
515						mediatek,infracfg = <&infracfg_ao>;
516						#address-cells = <1>;
517						#size-cells = <0>;
518						#power-domain-cells = <1>;
519
520						power-domain@MT8186_POWER_DOMAIN_CAM_RAWB {
521							reg = <MT8186_POWER_DOMAIN_CAM_RAWB>;
522							#power-domain-cells = <0>;
523						};
524
525						power-domain@MT8186_POWER_DOMAIN_CAM_RAWA {
526							reg = <MT8186_POWER_DOMAIN_CAM_RAWA>;
527							#power-domain-cells = <0>;
528						};
529					};
530
531					power-domain@MT8186_POWER_DOMAIN_IMG {
532						reg = <MT8186_POWER_DOMAIN_IMG>;
533						clocks = <&topckgen CLK_TOP_IMG1>,
534							 <&imgsys1 CLK_IMG1_GALS_IMG1>;
535						clock-names = "img-top", "gals";
536						mediatek,infracfg = <&infracfg_ao>;
537						#address-cells = <1>;
538						#size-cells = <0>;
539						#power-domain-cells = <1>;
540
541						power-domain@MT8186_POWER_DOMAIN_IMG2 {
542							reg = <MT8186_POWER_DOMAIN_IMG2>;
543							#power-domain-cells = <0>;
544						};
545					};
546
547					power-domain@MT8186_POWER_DOMAIN_IPE {
548						reg = <MT8186_POWER_DOMAIN_IPE>;
549						clocks = <&topckgen CLK_TOP_IPE>,
550							 <&ipesys CLK_IPE_LARB19>,
551							 <&ipesys CLK_IPE_LARB20>,
552							 <&ipesys CLK_IPE_SMI_SUBCOM>,
553							 <&ipesys CLK_IPE_GALS_IPE>;
554						clock-names = "ipe-top", "ipe-larb0", "ipe-larb1",
555							      "ipe-smi", "ipe-gals";
556						mediatek,infracfg = <&infracfg_ao>;
557						#power-domain-cells = <0>;
558					};
559
560					power-domain@MT8186_POWER_DOMAIN_VENC {
561						reg = <MT8186_POWER_DOMAIN_VENC>;
562						clocks = <&topckgen CLK_TOP_VENC>,
563							 <&vencsys CLK_VENC_CKE1_VENC>;
564						clock-names = "venc0", "larb";
565						mediatek,infracfg = <&infracfg_ao>;
566						#power-domain-cells = <0>;
567					};
568
569					power-domain@MT8186_POWER_DOMAIN_WPE {
570						reg = <MT8186_POWER_DOMAIN_WPE>;
571						clocks = <&topckgen CLK_TOP_WPE>,
572							 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
573							 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>;
574						clock-names = "wpe0", "larb-ck", "larb-pclk";
575						mediatek,infracfg = <&infracfg_ao>;
576						#power-domain-cells = <0>;
577					};
578				};
579			};
580		};
581
582		watchdog: watchdog@10007000 {
583			compatible = "mediatek,mt8186-wdt";
584			mediatek,disable-extrst;
585			reg = <0 0x10007000 0 0x1000>;
586			#reset-cells = <1>;
587		};
588
589		apmixedsys: syscon@1000c000 {
590			compatible = "mediatek,mt8186-apmixedsys", "syscon";
591			reg = <0 0x1000c000 0 0x1000>;
592			#clock-cells = <1>;
593		};
594
595		pwrap: pwrap@1000d000 {
596			compatible = "mediatek,mt8186-pwrap", "syscon";
597			reg = <0 0x1000d000 0 0x1000>;
598			reg-names = "pwrap";
599			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
600			clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
601				 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
602			clock-names = "spi", "wrap";
603		};
604
605		systimer: timer@10017000 {
606			compatible = "mediatek,mt8186-timer",
607				     "mediatek,mt6765-timer";
608			reg = <0 0x10017000 0 0x1000>;
609			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>;
610			clocks = <&clk13m>;
611		};
612
613		scp: scp@10500000 {
614			compatible = "mediatek,mt8186-scp";
615			reg = <0 0x10500000 0 0x40000>,
616			      <0 0x105c0000 0 0x19080>;
617			reg-names = "sram", "cfg";
618			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
619		};
620
621		adsp_mailbox0: mailbox@10686000 {
622			compatible = "mediatek,mt8186-adsp-mbox";
623			#mbox-cells = <0>;
624			reg = <0 0x10686100 0 0x1000>;
625			interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
626		};
627
628		adsp_mailbox1: mailbox@10687000 {
629			compatible = "mediatek,mt8186-adsp-mbox";
630			#mbox-cells = <0>;
631			reg = <0 0x10687100 0 0x1000>;
632			interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>;
633		};
634
635		nor_flash: spi@11000000 {
636			compatible = "mediatek,mt8186-nor";
637			reg = <0 0x11000000 0 0x1000>;
638			clocks = <&topckgen CLK_TOP_SPINOR>,
639				 <&infracfg_ao CLK_INFRA_AO_SPINOR>,
640				 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>,
641				 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>;
642			clock-names = "spi", "sf", "axi", "axi_s";
643			assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
644			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
645			interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>;
646			status = "disabled";
647		};
648
649		auxadc: adc@11001000 {
650			compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc";
651			reg = <0 0x11001000 0 0x1000>;
652			#io-channel-cells = <1>;
653			clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
654			clock-names = "main";
655		};
656
657		uart0: serial@11002000 {
658			compatible = "mediatek,mt8186-uart",
659				     "mediatek,mt6577-uart";
660			reg = <0 0x11002000 0 0x1000>;
661			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
662			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
663			clock-names = "baud", "bus";
664			status = "disabled";
665		};
666
667		uart1: serial@11003000 {
668			compatible = "mediatek,mt8186-uart",
669				     "mediatek,mt6577-uart";
670			reg = <0 0x11003000 0 0x1000>;
671			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
672			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
673			clock-names = "baud", "bus";
674			status = "disabled";
675		};
676
677		i2c0: i2c@11007000 {
678			compatible = "mediatek,mt8186-i2c";
679			reg = <0 0x11007000 0 0x1000>,
680			      <0 0x10200100 0 0x100>;
681			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
682			clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>,
683				 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
684			clock-names = "main", "dma";
685			clock-div = <1>;
686			#address-cells = <1>;
687			#size-cells = <0>;
688			status = "disabled";
689		};
690
691		i2c1: i2c@11008000 {
692			compatible = "mediatek,mt8186-i2c";
693			reg = <0 0x11008000 0 0x1000>,
694			      <0 0x10200200 0 0x100>;
695			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
696			clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>,
697				 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
698			clock-names = "main", "dma";
699			clock-div = <1>;
700			#address-cells = <1>;
701			#size-cells = <0>;
702			status = "disabled";
703		};
704
705		i2c2: i2c@11009000 {
706			compatible = "mediatek,mt8186-i2c";
707			reg = <0 0x11009000 0 0x1000>,
708			      <0 0x10200300 0 0x180>;
709			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>;
710			clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>,
711				 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
712			clock-names = "main", "dma";
713			clock-div = <1>;
714			#address-cells = <1>;
715			#size-cells = <0>;
716			status = "disabled";
717		};
718
719		i2c3: i2c@1100f000 {
720			compatible = "mediatek,mt8186-i2c";
721			reg = <0 0x1100f000 0 0x1000>,
722			      <0 0x10200480 0 0x100>;
723			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
724			clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>,
725				 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
726			clock-names = "main", "dma";
727			clock-div = <1>;
728			#address-cells = <1>;
729			#size-cells = <0>;
730			status = "disabled";
731		};
732
733		i2c4: i2c@11011000 {
734			compatible = "mediatek,mt8186-i2c";
735			reg = <0 0x11011000 0 0x1000>,
736			      <0 0x10200580 0 0x180>;
737			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
738			clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>,
739				 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
740			clock-names = "main", "dma";
741			clock-div = <1>;
742			#address-cells = <1>;
743			#size-cells = <0>;
744			status = "disabled";
745		};
746
747		i2c5: i2c@11016000 {
748			compatible = "mediatek,mt8186-i2c";
749			reg = <0 0x11016000 0 0x1000>,
750			      <0 0x10200700 0 0x100>;
751			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>;
752			clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>,
753				 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
754			clock-names = "main", "dma";
755			clock-div = <1>;
756			#address-cells = <1>;
757			#size-cells = <0>;
758			status = "disabled";
759		};
760
761		i2c6: i2c@1100d000 {
762			compatible = "mediatek,mt8186-i2c";
763			reg = <0 0x1100d000 0 0x1000>,
764			      <0 0x10200800 0 0x100>;
765			interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>;
766			clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>,
767				 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
768			clock-names = "main", "dma";
769			clock-div = <1>;
770			#address-cells = <1>;
771			#size-cells = <0>;
772			status = "disabled";
773		};
774
775		i2c7: i2c@11004000 {
776			compatible = "mediatek,mt8186-i2c";
777			reg = <0 0x11004000 0 0x1000>,
778			      <0 0x10200900 0 0x180>;
779			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
780			clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>,
781				 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
782			clock-names = "main", "dma";
783			clock-div = <1>;
784			#address-cells = <1>;
785			#size-cells = <0>;
786			status = "disabled";
787		};
788
789		i2c8: i2c@11005000 {
790			compatible = "mediatek,mt8186-i2c";
791			reg = <0 0x11005000 0 0x1000>,
792			      <0 0x10200A80 0 0x180>;
793			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
794			clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>,
795				 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
796			clock-names = "main", "dma";
797			clock-div = <1>;
798			#address-cells = <1>;
799			#size-cells = <0>;
800			status = "disabled";
801		};
802
803		spi0: spi@1100a000 {
804			compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
805			#address-cells = <1>;
806			#size-cells = <0>;
807			reg = <0 0x1100a000 0 0x1000>;
808			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>;
809			clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
810				 <&topckgen CLK_TOP_SPI>,
811				 <&infracfg_ao CLK_INFRA_AO_SPI0>;
812			clock-names = "parent-clk", "sel-clk", "spi-clk";
813			status = "disabled";
814		};
815
816		pwm0: pwm@1100e000 {
817			compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
818			reg = <0 0x1100e000 0 0x1000>;
819			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
820			#pwm-cells = <2>;
821			clocks = <&topckgen CLK_TOP_DISP_PWM>,
822				 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
823			clock-names = "main", "mm";
824			status = "disabled";
825		};
826
827		spi1: spi@11010000 {
828			compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
829			#address-cells = <1>;
830			#size-cells = <0>;
831			reg = <0 0x11010000 0 0x1000>;
832			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>;
833			clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
834				 <&topckgen CLK_TOP_SPI>,
835				 <&infracfg_ao CLK_INFRA_AO_SPI1>;
836			clock-names = "parent-clk", "sel-clk", "spi-clk";
837			status = "disabled";
838		};
839
840		spi2: spi@11012000 {
841			compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
842			#address-cells = <1>;
843			#size-cells = <0>;
844			reg = <0 0x11012000 0 0x1000>;
845			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>;
846			clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
847				 <&topckgen CLK_TOP_SPI>,
848				 <&infracfg_ao CLK_INFRA_AO_SPI2>;
849			clock-names = "parent-clk", "sel-clk", "spi-clk";
850			status = "disabled";
851		};
852
853		spi3: spi@11013000 {
854			compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
855			#address-cells = <1>;
856			#size-cells = <0>;
857			reg = <0 0x11013000 0 0x1000>;
858			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>;
859			clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
860				 <&topckgen CLK_TOP_SPI>,
861				 <&infracfg_ao CLK_INFRA_AO_SPI3>;
862			clock-names = "parent-clk", "sel-clk", "spi-clk";
863			status = "disabled";
864		};
865
866		spi4: spi@11014000 {
867			compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
868			#address-cells = <1>;
869			#size-cells = <0>;
870			reg = <0 0x11014000 0 0x1000>;
871			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
872			clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
873				 <&topckgen CLK_TOP_SPI>,
874				 <&infracfg_ao CLK_INFRA_AO_SPI4>;
875			clock-names = "parent-clk", "sel-clk", "spi-clk";
876			status = "disabled";
877		};
878
879		spi5: spi@11015000 {
880			compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
881			#address-cells = <1>;
882			#size-cells = <0>;
883			reg = <0 0x11015000 0 0x1000>;
884			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
885			clocks = <&topckgen CLK_TOP_MAINPLL_D5>,
886				 <&topckgen CLK_TOP_SPI>,
887				 <&infracfg_ao CLK_INFRA_AO_SPI5>;
888			clock-names = "parent-clk", "sel-clk", "spi-clk";
889			status = "disabled";
890		};
891
892		imp_iic_wrap: clock-controller@11017000 {
893			compatible = "mediatek,mt8186-imp_iic_wrap";
894			reg = <0 0x11017000 0 0x1000>;
895			#clock-cells = <1>;
896		};
897
898		uart2: serial@11018000 {
899			compatible = "mediatek,mt8186-uart",
900				     "mediatek,mt6577-uart";
901			reg = <0 0x11018000 0 0x1000>;
902			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>;
903			clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
904			clock-names = "baud", "bus";
905			status = "disabled";
906		};
907
908		i2c9: i2c@11019000 {
909			compatible = "mediatek,mt8186-i2c";
910			reg = <0 0x11019000 0 0x1000>,
911			      <0 0x10200c00 0 0x180>;
912			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>;
913			clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>,
914				 <&infracfg_ao CLK_INFRA_AO_AP_DMA>;
915			clock-names = "main", "dma";
916			clock-div = <1>;
917			#address-cells = <1>;
918			#size-cells = <0>;
919			status = "disabled";
920		};
921
922		afe: audio-controller@11210000 {
923			compatible = "mediatek,mt8186-sound";
924			reg = <0 0x11210000 0 0x2000>;
925			clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>,
926				 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>,
927				 <&topckgen CLK_TOP_AUDIO>,
928				 <&topckgen CLK_TOP_AUD_INTBUS>,
929				 <&topckgen CLK_TOP_MAINPLL_D2_D4>,
930				 <&topckgen CLK_TOP_AUD_1>,
931				 <&apmixedsys CLK_APMIXED_APLL1>,
932				 <&topckgen CLK_TOP_AUD_2>,
933				 <&apmixedsys CLK_APMIXED_APLL2>,
934				 <&topckgen CLK_TOP_AUD_ENGEN1>,
935				 <&topckgen CLK_TOP_APLL1_D8>,
936				 <&topckgen CLK_TOP_AUD_ENGEN2>,
937				 <&topckgen CLK_TOP_APLL2_D8>,
938				 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>,
939				 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>,
940				 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>,
941				 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>,
942				 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>,
943				 <&topckgen CLK_TOP_APLL12_CK_DIV0>,
944				 <&topckgen CLK_TOP_APLL12_CK_DIV1>,
945				 <&topckgen CLK_TOP_APLL12_CK_DIV2>,
946				 <&topckgen CLK_TOP_APLL12_CK_DIV4>,
947				 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>,
948				 <&topckgen CLK_TOP_AUDIO_H>,
949				 <&clk26m>;
950			clock-names = "aud_infra_clk",
951				      "mtkaif_26m_clk",
952				      "top_mux_audio",
953				      "top_mux_audio_int",
954				      "top_mainpll_d2_d4",
955				      "top_mux_aud_1",
956				      "top_apll1_ck",
957				      "top_mux_aud_2",
958				      "top_apll2_ck",
959				      "top_mux_aud_eng1",
960				      "top_apll1_d8",
961				      "top_mux_aud_eng2",
962				      "top_apll2_d8",
963				      "top_i2s0_m_sel",
964				      "top_i2s1_m_sel",
965				      "top_i2s2_m_sel",
966				      "top_i2s4_m_sel",
967				      "top_tdm_m_sel",
968				      "top_apll12_div0",
969				      "top_apll12_div1",
970				      "top_apll12_div2",
971				      "top_apll12_div4",
972				      "top_apll12_div_tdm",
973				      "top_mux_audio_h",
974				      "top_clk26m_clk";
975			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
976			mediatek,apmixedsys = <&apmixedsys>;
977			mediatek,infracfg = <&infracfg_ao>;
978			mediatek,topckgen = <&topckgen>;
979			resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>;
980			reset-names = "audiosys";
981			status = "disabled";
982		};
983
984		mmc0: mmc@11230000 {
985			compatible = "mediatek,mt8186-mmc",
986				     "mediatek,mt8183-mmc";
987			reg = <0 0x11230000 0 0x10000>,
988			      <0 0x11cd0000 0 0x1000>;
989			clocks = <&topckgen CLK_TOP_MSDC50_0>,
990				 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
991				 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>,
992				 <&infracfg_ao CLK_INFRA_AO_MSDCFDE>;
993			clock-names = "source", "hclk", "source_cg", "crypto";
994			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
995			assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
996			assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>;
997			status = "disabled";
998		};
999
1000		mmc1: mmc@11240000 {
1001			compatible = "mediatek,mt8186-mmc",
1002				     "mediatek,mt8183-mmc";
1003			reg = <0 0x11240000 0 0x1000>,
1004			      <0 0x11c90000 0 0x1000>;
1005			clocks = <&topckgen CLK_TOP_MSDC30_1>,
1006				 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
1007				 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
1008			clock-names = "source", "hclk", "source_cg";
1009			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
1010			assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1011			assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1012			status = "disabled";
1013		};
1014
1015		u3phy0: t-phy@11c80000 {
1016			compatible = "mediatek,mt8186-tphy",
1017				     "mediatek,generic-tphy-v2";
1018			#address-cells = <1>;
1019			#size-cells = <1>;
1020			ranges = <0x0 0x0 0x11c80000 0x1000>;
1021			status = "disabled";
1022
1023			u2port1: usb-phy@0 {
1024				reg = <0x0 0x700>;
1025				clocks = <&clk26m>;
1026				clock-names = "ref";
1027				#phy-cells = <1>;
1028			};
1029
1030			u3port1: usb-phy@700 {
1031				reg = <0x700 0x900>;
1032				clocks = <&clk26m>;
1033				clock-names = "ref";
1034				#phy-cells = <1>;
1035			};
1036		};
1037
1038		u3phy1: t-phy@11ca0000 {
1039			compatible = "mediatek,mt8186-tphy",
1040				     "mediatek,generic-tphy-v2";
1041			#address-cells = <1>;
1042			#size-cells = <1>;
1043			ranges = <0x0 0x0 0x11ca0000 0x1000>;
1044			status = "disabled";
1045
1046			u2port0: usb-phy@0 {
1047				reg = <0x0 0x700>;
1048				clocks = <&clk26m>;
1049				clock-names = "ref";
1050				#phy-cells = <1>;
1051				mediatek,discth = <0x8>;
1052			};
1053		};
1054
1055		efuse: efuse@11cb0000 {
1056			compatible = "mediatek,mt8186-efuse", "mediatek,efuse";
1057			reg = <0 0x11cb0000 0 0x1000>;
1058			#address-cells = <1>;
1059			#size-cells = <1>;
1060		};
1061
1062		mipi_tx0: dsi-phy@11cc0000 {
1063			compatible = "mediatek,mt8183-mipi-tx";
1064			reg = <0 0x11cc0000 0 0x1000>;
1065			clocks = <&clk26m>;
1066			#clock-cells = <0>;
1067			#phy-cells = <0>;
1068			clock-output-names = "mipi_tx0_pll";
1069			status = "disabled";
1070		};
1071
1072		mfgsys: clock-controller@13000000 {
1073			compatible = "mediatek,mt8186-mfgsys";
1074			reg = <0 0x13000000 0 0x1000>;
1075			#clock-cells = <1>;
1076		};
1077
1078		mmsys: syscon@14000000 {
1079			compatible = "mediatek,mt8186-mmsys", "syscon";
1080			reg = <0 0x14000000 0 0x1000>;
1081			#clock-cells = <1>;
1082			#reset-cells = <1>;
1083		};
1084
1085		smi_common: smi@14002000 {
1086			compatible = "mediatek,mt8186-smi-common";
1087			reg = <0 0x14002000 0 0x1000>;
1088			clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>,
1089				 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>;
1090			clock-names = "apb", "smi", "gals0", "gals1";
1091			power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1092		};
1093
1094		larb0: smi@14003000 {
1095			compatible = "mediatek,mt8186-smi-larb";
1096			reg = <0 0x14003000 0 0x1000>;
1097			clocks = <&mmsys CLK_MM_SMI_COMMON>,
1098				 <&mmsys CLK_MM_SMI_COMMON>;
1099			clock-names = "apb", "smi";
1100			mediatek,larb-id = <0>;
1101			mediatek,smi = <&smi_common>;
1102			power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1103		};
1104
1105		larb1: smi@14004000 {
1106			compatible = "mediatek,mt8186-smi-larb";
1107			reg = <0 0x14004000 0 0x1000>;
1108			clocks = <&mmsys CLK_MM_SMI_COMMON>,
1109				 <&mmsys CLK_MM_SMI_COMMON>;
1110			clock-names = "apb", "smi";
1111			mediatek,larb-id = <1>;
1112			mediatek,smi = <&smi_common>;
1113			power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1114		};
1115
1116		dpi: dpi@1400a000 {
1117			compatible = "mediatek,mt8186-dpi";
1118			reg = <0 0x1400a000 0 0x1000>;
1119			clocks = <&topckgen CLK_TOP_DPI>,
1120				 <&mmsys CLK_MM_DISP_DPI>,
1121				 <&apmixedsys CLK_APMIXED_TVDPLL>;
1122			clock-names = "pixel", "engine", "pll";
1123			assigned-clocks = <&topckgen CLK_TOP_DPI>;
1124			assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
1125			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>;
1126			status = "disabled";
1127
1128			port {
1129				dpi_out: endpoint { };
1130			};
1131		};
1132
1133		dsi0: dsi@14013000 {
1134			compatible = "mediatek,mt8186-dsi";
1135			reg = <0 0x14013000 0 0x1000>;
1136			clocks = <&mmsys CLK_MM_DSI0>,
1137				 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>,
1138				 <&mipi_tx0>;
1139			clock-names = "engine", "digital", "hs";
1140			interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>;
1141			power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1142			resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>;
1143			phys = <&mipi_tx0>;
1144			phy-names = "dphy";
1145			status = "disabled";
1146
1147			port {
1148				dsi_out: endpoint { };
1149			};
1150		};
1151
1152		iommu_mm: iommu@14016000 {
1153			compatible = "mediatek,mt8186-iommu-mm";
1154			reg = <0 0x14016000 0 0x1000>;
1155			clocks = <&mmsys CLK_MM_SMI_IOMMU>;
1156			clock-names = "bclk";
1157			interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>;
1158			mediatek,larbs = <&larb0 &larb1 &larb2 &larb4
1159					  &larb7 &larb8 &larb9 &larb11
1160					  &larb13 &larb14 &larb16 &larb17
1161					  &larb19 &larb20>;
1162			power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1163			#iommu-cells = <1>;
1164		};
1165
1166		wpesys: clock-controller@14020000 {
1167			compatible = "mediatek,mt8186-wpesys";
1168			reg = <0 0x14020000 0 0x1000>;
1169			#clock-cells = <1>;
1170		};
1171
1172		larb8: smi@14023000 {
1173			compatible = "mediatek,mt8186-smi-larb";
1174			reg = <0 0x14023000 0 0x1000>;
1175			clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>,
1176				 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>;
1177			clock-names = "apb", "smi";
1178			mediatek,larb-id = <8>;
1179			mediatek,smi = <&smi_common>;
1180			power-domains = <&spm MT8186_POWER_DOMAIN_WPE>;
1181		};
1182
1183		imgsys1: clock-controller@15020000 {
1184			compatible = "mediatek,mt8186-imgsys1";
1185			reg = <0 0x15020000 0 0x1000>;
1186			#clock-cells = <1>;
1187		};
1188
1189		larb9: smi@1502e000 {
1190			compatible = "mediatek,mt8186-smi-larb";
1191			reg = <0 0x1502e000 0 0x1000>;
1192			clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>,
1193				 <&imgsys1 CLK_IMG1_LARB9_IMG1>;
1194			clock-names = "apb", "smi";
1195			mediatek,larb-id = <9>;
1196			mediatek,smi = <&smi_common>;
1197			power-domains = <&spm MT8186_POWER_DOMAIN_IMG>;
1198		};
1199
1200		imgsys2: clock-controller@15820000 {
1201			compatible = "mediatek,mt8186-imgsys2";
1202			reg = <0 0x15820000 0 0x1000>;
1203			#clock-cells = <1>;
1204		};
1205
1206		larb11: smi@1582e000 {
1207			compatible = "mediatek,mt8186-smi-larb";
1208			reg = <0 0x1582e000 0 0x1000>;
1209			clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>,
1210				 <&imgsys2 CLK_IMG2_LARB9_IMG2>;
1211			clock-names = "apb", "smi";
1212			mediatek,larb-id = <11>;
1213			mediatek,smi = <&smi_common>;
1214			power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>;
1215		};
1216
1217		larb4: smi@1602e000 {
1218			compatible = "mediatek,mt8186-smi-larb";
1219			reg = <0 0x1602e000 0 0x1000>;
1220			clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>,
1221				 <&vdecsys CLK_VDEC_LARB1_CKEN>;
1222			clock-names = "apb", "smi";
1223			mediatek,larb-id = <4>;
1224			mediatek,smi = <&smi_common>;
1225			power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
1226		};
1227
1228		vdecsys: clock-controller@1602f000 {
1229			compatible = "mediatek,mt8186-vdecsys";
1230			reg = <0 0x1602f000 0 0x1000>;
1231			#clock-cells = <1>;
1232		};
1233
1234		vencsys: clock-controller@17000000 {
1235			compatible = "mediatek,mt8186-vencsys";
1236			reg = <0 0x17000000 0 0x1000>;
1237			#clock-cells = <1>;
1238		};
1239
1240		larb7: smi@17010000 {
1241			compatible = "mediatek,mt8186-smi-larb";
1242			reg = <0 0x17010000 0 0x1000>;
1243			clocks = <&vencsys CLK_VENC_CKE1_VENC>,
1244				 <&vencsys CLK_VENC_CKE1_VENC>;
1245			clock-names = "apb", "smi";
1246			mediatek,larb-id = <7>;
1247			mediatek,smi = <&smi_common>;
1248			power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
1249		};
1250
1251		camsys: clock-controller@1a000000 {
1252			compatible = "mediatek,mt8186-camsys";
1253			reg = <0 0x1a000000 0 0x1000>;
1254			#clock-cells = <1>;
1255		};
1256
1257		larb13: smi@1a001000 {
1258			compatible = "mediatek,mt8186-smi-larb";
1259			reg = <0 0x1a001000 0 0x1000>;
1260			clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>;
1261			clock-names = "apb", "smi";
1262			mediatek,larb-id = <13>;
1263			mediatek,smi = <&smi_common>;
1264			power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
1265		};
1266
1267		larb14: smi@1a002000 {
1268			compatible = "mediatek,mt8186-smi-larb";
1269			reg = <0 0x1a002000 0 0x1000>;
1270			clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>;
1271			clock-names = "apb", "smi";
1272			mediatek,larb-id = <14>;
1273			mediatek,smi = <&smi_common>;
1274			power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
1275		};
1276
1277		larb16: smi@1a00f000 {
1278			compatible = "mediatek,mt8186-smi-larb";
1279			reg = <0 0x1a00f000 0 0x1000>;
1280			clocks = <&camsys CLK_CAM_LARB14>,
1281				 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>;
1282			clock-names = "apb", "smi";
1283			mediatek,larb-id = <16>;
1284			mediatek,smi = <&smi_common>;
1285			power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>;
1286		};
1287
1288		larb17: smi@1a010000 {
1289			compatible = "mediatek,mt8186-smi-larb";
1290			reg = <0 0x1a010000 0 0x1000>;
1291			clocks = <&camsys CLK_CAM_LARB13>,
1292				 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>;
1293			clock-names = "apb", "smi";
1294			mediatek,larb-id = <17>;
1295			mediatek,smi = <&smi_common>;
1296			power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>;
1297		};
1298
1299		camsys_rawa: clock-controller@1a04f000 {
1300			compatible = "mediatek,mt8186-camsys_rawa";
1301			reg = <0 0x1a04f000 0 0x1000>;
1302			#clock-cells = <1>;
1303		};
1304
1305		camsys_rawb: clock-controller@1a06f000 {
1306			compatible = "mediatek,mt8186-camsys_rawb";
1307			reg = <0 0x1a06f000 0 0x1000>;
1308			#clock-cells = <1>;
1309		};
1310
1311		mdpsys: clock-controller@1b000000 {
1312			compatible = "mediatek,mt8186-mdpsys";
1313			reg = <0 0x1b000000 0 0x1000>;
1314			#clock-cells = <1>;
1315		};
1316
1317		larb2: smi@1b002000 {
1318			compatible = "mediatek,mt8186-smi-larb";
1319			reg = <0 0x1b002000 0 0x1000>;
1320			clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>;
1321			clock-names = "apb", "smi";
1322			mediatek,larb-id = <2>;
1323			mediatek,smi = <&smi_common>;
1324			power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1325		};
1326
1327		ipesys: clock-controller@1c000000 {
1328			compatible = "mediatek,mt8186-ipesys";
1329			reg = <0 0x1c000000 0 0x1000>;
1330			#clock-cells = <1>;
1331		};
1332
1333		larb20: smi@1c00f000 {
1334			compatible = "mediatek,mt8186-smi-larb";
1335			reg = <0 0x1c00f000 0 0x1000>;
1336			clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>;
1337			clock-names = "apb", "smi";
1338			mediatek,larb-id = <20>;
1339			mediatek,smi = <&smi_common>;
1340			power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
1341		};
1342
1343		larb19: smi@1c10f000 {
1344			compatible = "mediatek,mt8186-smi-larb";
1345			reg = <0 0x1c10f000 0 0x1000>;
1346			clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>;
1347			clock-names = "apb", "smi";
1348			mediatek,larb-id = <19>;
1349			mediatek,smi = <&smi_common>;
1350			power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
1351		};
1352	};
1353};
1354