1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Copyright (C) 2022 MediaTek Inc. 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 5 */ 6/dts-v1/; 7#include <dt-bindings/clock/mt8186-clk.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/memory/mt8186-memory-port.h> 11#include <dt-bindings/pinctrl/mt8186-pinfunc.h> 12#include <dt-bindings/power/mt8186-power.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/reset/mt8186-resets.h> 15 16/ { 17 compatible = "mediatek,mt8186"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu-map { 27 cluster0 { 28 core0 { 29 cpu = <&cpu0>; 30 }; 31 32 core1 { 33 cpu = <&cpu1>; 34 }; 35 36 core2 { 37 cpu = <&cpu2>; 38 }; 39 40 core3 { 41 cpu = <&cpu3>; 42 }; 43 44 core4 { 45 cpu = <&cpu4>; 46 }; 47 48 core5 { 49 cpu = <&cpu5>; 50 }; 51 }; 52 53 cluster1 { 54 core0 { 55 cpu = <&cpu6>; 56 }; 57 58 core1 { 59 cpu = <&cpu7>; 60 }; 61 }; 62 }; 63 64 cpu0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a55"; 67 reg = <0x000>; 68 enable-method = "psci"; 69 clock-frequency = <2000000000>; 70 capacity-dmips-mhz = <382>; 71 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 72 i-cache-size = <32768>; 73 i-cache-line-size = <64>; 74 i-cache-sets = <128>; 75 d-cache-size = <32768>; 76 d-cache-line-size = <64>; 77 d-cache-sets = <128>; 78 next-level-cache = <&l2_0>; 79 #cooling-cells = <2>; 80 }; 81 82 cpu1: cpu@100 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a55"; 85 reg = <0x100>; 86 enable-method = "psci"; 87 clock-frequency = <2000000000>; 88 capacity-dmips-mhz = <382>; 89 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 90 i-cache-size = <32768>; 91 i-cache-line-size = <64>; 92 i-cache-sets = <128>; 93 d-cache-size = <32768>; 94 d-cache-line-size = <64>; 95 d-cache-sets = <128>; 96 next-level-cache = <&l2_0>; 97 #cooling-cells = <2>; 98 }; 99 100 cpu2: cpu@200 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a55"; 103 reg = <0x200>; 104 enable-method = "psci"; 105 clock-frequency = <2000000000>; 106 capacity-dmips-mhz = <382>; 107 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 108 i-cache-size = <32768>; 109 i-cache-line-size = <64>; 110 i-cache-sets = <128>; 111 d-cache-size = <32768>; 112 d-cache-line-size = <64>; 113 d-cache-sets = <128>; 114 next-level-cache = <&l2_0>; 115 #cooling-cells = <2>; 116 }; 117 118 cpu3: cpu@300 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a55"; 121 reg = <0x300>; 122 enable-method = "psci"; 123 clock-frequency = <2000000000>; 124 capacity-dmips-mhz = <382>; 125 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 126 i-cache-size = <32768>; 127 i-cache-line-size = <64>; 128 i-cache-sets = <128>; 129 d-cache-size = <32768>; 130 d-cache-line-size = <64>; 131 d-cache-sets = <128>; 132 next-level-cache = <&l2_0>; 133 #cooling-cells = <2>; 134 }; 135 136 cpu4: cpu@400 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a55"; 139 reg = <0x400>; 140 enable-method = "psci"; 141 clock-frequency = <2000000000>; 142 capacity-dmips-mhz = <382>; 143 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 144 i-cache-size = <32768>; 145 i-cache-line-size = <64>; 146 i-cache-sets = <128>; 147 d-cache-size = <32768>; 148 d-cache-line-size = <64>; 149 d-cache-sets = <128>; 150 next-level-cache = <&l2_0>; 151 #cooling-cells = <2>; 152 }; 153 154 cpu5: cpu@500 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a55"; 157 reg = <0x500>; 158 enable-method = "psci"; 159 clock-frequency = <2000000000>; 160 capacity-dmips-mhz = <382>; 161 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 162 i-cache-size = <32768>; 163 i-cache-line-size = <64>; 164 i-cache-sets = <128>; 165 d-cache-size = <32768>; 166 d-cache-line-size = <64>; 167 d-cache-sets = <128>; 168 next-level-cache = <&l2_0>; 169 #cooling-cells = <2>; 170 }; 171 172 cpu6: cpu@600 { 173 device_type = "cpu"; 174 compatible = "arm,cortex-a76"; 175 reg = <0x600>; 176 enable-method = "psci"; 177 clock-frequency = <2050000000>; 178 capacity-dmips-mhz = <1024>; 179 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 180 i-cache-size = <65536>; 181 i-cache-line-size = <64>; 182 i-cache-sets = <256>; 183 d-cache-size = <65536>; 184 d-cache-line-size = <64>; 185 d-cache-sets = <256>; 186 next-level-cache = <&l2_1>; 187 #cooling-cells = <2>; 188 }; 189 190 cpu7: cpu@700 { 191 device_type = "cpu"; 192 compatible = "arm,cortex-a76"; 193 reg = <0x700>; 194 enable-method = "psci"; 195 clock-frequency = <2050000000>; 196 capacity-dmips-mhz = <1024>; 197 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 198 i-cache-size = <65536>; 199 i-cache-line-size = <64>; 200 i-cache-sets = <256>; 201 d-cache-size = <65536>; 202 d-cache-line-size = <64>; 203 d-cache-sets = <256>; 204 next-level-cache = <&l2_1>; 205 #cooling-cells = <2>; 206 }; 207 208 idle-states { 209 entry-method = "psci"; 210 211 cpu_off_l: cpu-off-l { 212 compatible = "arm,idle-state"; 213 arm,psci-suspend-param = <0x00010001>; 214 local-timer-stop; 215 entry-latency-us = <50>; 216 exit-latency-us = <100>; 217 min-residency-us = <1600>; 218 }; 219 220 cpu_off_b: cpu-off-b { 221 compatible = "arm,idle-state"; 222 arm,psci-suspend-param = <0x00010001>; 223 local-timer-stop; 224 entry-latency-us = <50>; 225 exit-latency-us = <100>; 226 min-residency-us = <1400>; 227 }; 228 229 cluster_off_l: cluster-off-l { 230 compatible = "arm,idle-state"; 231 arm,psci-suspend-param = <0x01010001>; 232 local-timer-stop; 233 entry-latency-us = <100>; 234 exit-latency-us = <250>; 235 min-residency-us = <2100>; 236 }; 237 238 cluster_off_b: cluster-off-b { 239 compatible = "arm,idle-state"; 240 arm,psci-suspend-param = <0x01010001>; 241 local-timer-stop; 242 entry-latency-us = <100>; 243 exit-latency-us = <250>; 244 min-residency-us = <1900>; 245 }; 246 }; 247 248 l2_0: l2-cache0 { 249 compatible = "cache"; 250 cache-level = <2>; 251 cache-size = <131072>; 252 cache-line-size = <64>; 253 cache-sets = <512>; 254 next-level-cache = <&l3_0>; 255 }; 256 257 l2_1: l2-cache1 { 258 compatible = "cache"; 259 cache-level = <2>; 260 cache-size = <262144>; 261 cache-line-size = <64>; 262 cache-sets = <512>; 263 next-level-cache = <&l3_0>; 264 }; 265 266 l3_0: l3-cache { 267 compatible = "cache"; 268 cache-level = <3>; 269 cache-size = <1048576>; 270 cache-line-size = <64>; 271 cache-sets = <1024>; 272 cache-unified; 273 }; 274 }; 275 276 clk13m: fixed-factor-clock-13m { 277 compatible = "fixed-factor-clock"; 278 #clock-cells = <0>; 279 clocks = <&clk26m>; 280 clock-div = <2>; 281 clock-mult = <1>; 282 clock-output-names = "clk13m"; 283 }; 284 285 clk26m: oscillator-26m { 286 compatible = "fixed-clock"; 287 #clock-cells = <0>; 288 clock-frequency = <26000000>; 289 clock-output-names = "clk26m"; 290 }; 291 292 clk32k: oscillator-32k { 293 compatible = "fixed-clock"; 294 #clock-cells = <0>; 295 clock-frequency = <32768>; 296 clock-output-names = "clk32k"; 297 }; 298 299 pmu-a55 { 300 compatible = "arm,cortex-a55-pmu"; 301 interrupt-parent = <&gic>; 302 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 303 }; 304 305 pmu-a76 { 306 compatible = "arm,cortex-a76-pmu"; 307 interrupt-parent = <&gic>; 308 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 309 }; 310 311 psci { 312 compatible = "arm,psci-1.0"; 313 method = "smc"; 314 }; 315 316 timer { 317 compatible = "arm,armv8-timer"; 318 interrupt-parent = <&gic>; 319 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 320 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 321 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 322 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 323 }; 324 325 soc { 326 #address-cells = <2>; 327 #size-cells = <2>; 328 compatible = "simple-bus"; 329 ranges; 330 331 gic: interrupt-controller@c000000 { 332 compatible = "arm,gic-v3"; 333 #interrupt-cells = <4>; 334 #redistributor-regions = <1>; 335 interrupt-parent = <&gic>; 336 interrupt-controller; 337 reg = <0 0x0c000000 0 0x40000>, 338 <0 0x0c040000 0 0x200000>; 339 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 340 341 ppi-partitions { 342 ppi_cluster0: interrupt-partition-0 { 343 affinity = <&cpu0 &cpu1 &cpu2 &cpu3 &cpu4 &cpu5>; 344 }; 345 346 ppi_cluster1: interrupt-partition-1 { 347 affinity = <&cpu6 &cpu7>; 348 }; 349 }; 350 }; 351 352 mcusys: syscon@c53a000 { 353 compatible = "mediatek,mt8186-mcusys", "syscon"; 354 reg = <0 0xc53a000 0 0x1000>; 355 #clock-cells = <1>; 356 }; 357 358 topckgen: syscon@10000000 { 359 compatible = "mediatek,mt8186-topckgen", "syscon"; 360 reg = <0 0x10000000 0 0x1000>; 361 #clock-cells = <1>; 362 }; 363 364 infracfg_ao: syscon@10001000 { 365 compatible = "mediatek,mt8186-infracfg_ao", "syscon"; 366 reg = <0 0x10001000 0 0x1000>; 367 #clock-cells = <1>; 368 #reset-cells = <1>; 369 }; 370 371 pericfg: syscon@10003000 { 372 compatible = "mediatek,mt8186-pericfg", "syscon"; 373 reg = <0 0x10003000 0 0x1000>; 374 }; 375 376 pio: pinctrl@10005000 { 377 compatible = "mediatek,mt8186-pinctrl"; 378 reg = <0 0x10005000 0 0x1000>, 379 <0 0x10002000 0 0x0200>, 380 <0 0x10002200 0 0x0200>, 381 <0 0x10002400 0 0x0200>, 382 <0 0x10002600 0 0x0200>, 383 <0 0x10002a00 0 0x0200>, 384 <0 0x10002c00 0 0x0200>, 385 <0 0x1000b000 0 0x1000>; 386 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", 387 "iocfg_bl", "iocfg_rb", "iocfg_rt", "eint"; 388 gpio-controller; 389 #gpio-cells = <2>; 390 gpio-ranges = <&pio 0 0 185>; 391 interrupt-controller; 392 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 393 #interrupt-cells = <2>; 394 }; 395 396 scpsys: syscon@10006000 { 397 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; 398 reg = <0 0x10006000 0 0x1000>; 399 400 /* System Power Manager */ 401 spm: power-controller { 402 compatible = "mediatek,mt8186-power-controller"; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 #power-domain-cells = <1>; 406 407 /* power domain of the SoC */ 408 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 { 409 reg = <MT8186_POWER_DOMAIN_MFG0>; 410 clocks = <&topckgen CLK_TOP_MFG>; 411 clock-names = "mfg00"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 #power-domain-cells = <1>; 415 416 power-domain@MT8186_POWER_DOMAIN_MFG1 { 417 reg = <MT8186_POWER_DOMAIN_MFG1>; 418 mediatek,infracfg = <&infracfg_ao>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 #power-domain-cells = <1>; 422 423 power-domain@MT8186_POWER_DOMAIN_MFG2 { 424 reg = <MT8186_POWER_DOMAIN_MFG2>; 425 #power-domain-cells = <0>; 426 }; 427 428 power-domain@MT8186_POWER_DOMAIN_MFG3 { 429 reg = <MT8186_POWER_DOMAIN_MFG3>; 430 #power-domain-cells = <0>; 431 }; 432 }; 433 }; 434 435 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP { 436 reg = <MT8186_POWER_DOMAIN_CSIRX_TOP>; 437 clocks = <&topckgen CLK_TOP_SENINF>, 438 <&topckgen CLK_TOP_SENINF1>; 439 clock-names = "csirx_top0", "csirx_top1"; 440 #power-domain-cells = <0>; 441 }; 442 443 power-domain@MT8186_POWER_DOMAIN_SSUSB { 444 reg = <MT8186_POWER_DOMAIN_SSUSB>; 445 #power-domain-cells = <0>; 446 }; 447 448 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 { 449 reg = <MT8186_POWER_DOMAIN_SSUSB_P1>; 450 #power-domain-cells = <0>; 451 }; 452 453 power-domain@MT8186_POWER_DOMAIN_ADSP_AO { 454 reg = <MT8186_POWER_DOMAIN_ADSP_AO>; 455 clocks = <&topckgen CLK_TOP_AUDIODSP>, 456 <&topckgen CLK_TOP_ADSP_BUS>; 457 clock-names = "audioadsp", "adsp_bus"; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 #power-domain-cells = <1>; 461 462 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA { 463 reg = <MT8186_POWER_DOMAIN_ADSP_INFRA>; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 #power-domain-cells = <1>; 467 468 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP { 469 reg = <MT8186_POWER_DOMAIN_ADSP_TOP>; 470 mediatek,infracfg = <&infracfg_ao>; 471 #power-domain-cells = <0>; 472 }; 473 }; 474 }; 475 476 power-domain@MT8186_POWER_DOMAIN_CONN_ON { 477 reg = <MT8186_POWER_DOMAIN_CONN_ON>; 478 mediatek,infracfg = <&infracfg_ao>; 479 #power-domain-cells = <0>; 480 }; 481 482 power-domain@MT8186_POWER_DOMAIN_DIS { 483 reg = <MT8186_POWER_DOMAIN_DIS>; 484 clocks = <&topckgen CLK_TOP_DISP>, 485 <&topckgen CLK_TOP_MDP>, 486 <&mmsys CLK_MM_SMI_INFRA>, 487 <&mmsys CLK_MM_SMI_COMMON>, 488 <&mmsys CLK_MM_SMI_GALS>, 489 <&mmsys CLK_MM_SMI_IOMMU>; 490 clock-names = "disp", "mdp", "smi_infra", "smi_common", 491 "smi_gals", "smi_iommu"; 492 mediatek,infracfg = <&infracfg_ao>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 #power-domain-cells = <1>; 496 497 power-domain@MT8186_POWER_DOMAIN_VDEC { 498 reg = <MT8186_POWER_DOMAIN_VDEC>; 499 clocks = <&topckgen CLK_TOP_VDEC>, 500 <&vdecsys CLK_VDEC_LARB1_CKEN>; 501 clock-names = "vdec0", "larb"; 502 mediatek,infracfg = <&infracfg_ao>; 503 #power-domain-cells = <0>; 504 }; 505 506 power-domain@MT8186_POWER_DOMAIN_CAM { 507 reg = <MT8186_POWER_DOMAIN_CAM>; 508 clocks = <&topckgen CLK_TOP_CAM>, 509 <&topckgen CLK_TOP_SENINF>, 510 <&topckgen CLK_TOP_SENINF1>, 511 <&topckgen CLK_TOP_SENINF2>, 512 <&topckgen CLK_TOP_SENINF3>, 513 <&topckgen CLK_TOP_CAMTM>, 514 <&camsys CLK_CAM2MM_GALS>; 515 clock-names = "cam-top", "cam0", "cam1", "cam2", 516 "cam3", "cam-tm", "gals"; 517 mediatek,infracfg = <&infracfg_ao>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 #power-domain-cells = <1>; 521 522 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { 523 reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; 524 #power-domain-cells = <0>; 525 }; 526 527 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { 528 reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; 529 #power-domain-cells = <0>; 530 }; 531 }; 532 533 power-domain@MT8186_POWER_DOMAIN_IMG { 534 reg = <MT8186_POWER_DOMAIN_IMG>; 535 clocks = <&topckgen CLK_TOP_IMG1>, 536 <&imgsys1 CLK_IMG1_GALS_IMG1>; 537 clock-names = "img-top", "gals"; 538 mediatek,infracfg = <&infracfg_ao>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 #power-domain-cells = <1>; 542 543 power-domain@MT8186_POWER_DOMAIN_IMG2 { 544 reg = <MT8186_POWER_DOMAIN_IMG2>; 545 #power-domain-cells = <0>; 546 }; 547 }; 548 549 power-domain@MT8186_POWER_DOMAIN_IPE { 550 reg = <MT8186_POWER_DOMAIN_IPE>; 551 clocks = <&topckgen CLK_TOP_IPE>, 552 <&ipesys CLK_IPE_LARB19>, 553 <&ipesys CLK_IPE_LARB20>, 554 <&ipesys CLK_IPE_SMI_SUBCOM>, 555 <&ipesys CLK_IPE_GALS_IPE>; 556 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1", 557 "ipe-smi", "ipe-gals"; 558 mediatek,infracfg = <&infracfg_ao>; 559 #power-domain-cells = <0>; 560 }; 561 562 power-domain@MT8186_POWER_DOMAIN_VENC { 563 reg = <MT8186_POWER_DOMAIN_VENC>; 564 clocks = <&topckgen CLK_TOP_VENC>, 565 <&vencsys CLK_VENC_CKE1_VENC>; 566 clock-names = "venc0", "larb"; 567 mediatek,infracfg = <&infracfg_ao>; 568 #power-domain-cells = <0>; 569 }; 570 571 power-domain@MT8186_POWER_DOMAIN_WPE { 572 reg = <MT8186_POWER_DOMAIN_WPE>; 573 clocks = <&topckgen CLK_TOP_WPE>, 574 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 575 <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; 576 clock-names = "wpe0", "larb-ck", "larb-pclk"; 577 mediatek,infracfg = <&infracfg_ao>; 578 #power-domain-cells = <0>; 579 }; 580 }; 581 }; 582 }; 583 584 watchdog: watchdog@10007000 { 585 compatible = "mediatek,mt8186-wdt", 586 "mediatek,mt6589-wdt"; 587 mediatek,disable-extrst; 588 reg = <0 0x10007000 0 0x1000>; 589 #reset-cells = <1>; 590 }; 591 592 apmixedsys: syscon@1000c000 { 593 compatible = "mediatek,mt8186-apmixedsys", "syscon"; 594 reg = <0 0x1000c000 0 0x1000>; 595 #clock-cells = <1>; 596 }; 597 598 pwrap: pwrap@1000d000 { 599 compatible = "mediatek,mt8186-pwrap", "syscon"; 600 reg = <0 0x1000d000 0 0x1000>; 601 reg-names = "pwrap"; 602 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 603 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 604 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 605 clock-names = "spi", "wrap"; 606 }; 607 608 systimer: timer@10017000 { 609 compatible = "mediatek,mt8186-timer", 610 "mediatek,mt6765-timer"; 611 reg = <0 0x10017000 0 0x1000>; 612 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>; 613 clocks = <&clk13m>; 614 }; 615 616 scp: scp@10500000 { 617 compatible = "mediatek,mt8186-scp"; 618 reg = <0 0x10500000 0 0x40000>, 619 <0 0x105c0000 0 0x19080>; 620 reg-names = "sram", "cfg"; 621 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; 622 }; 623 624 adsp_mailbox0: mailbox@10686000 { 625 compatible = "mediatek,mt8186-adsp-mbox"; 626 #mbox-cells = <0>; 627 reg = <0 0x10686100 0 0x1000>; 628 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 629 }; 630 631 adsp_mailbox1: mailbox@10687000 { 632 compatible = "mediatek,mt8186-adsp-mbox"; 633 #mbox-cells = <0>; 634 reg = <0 0x10687100 0 0x1000>; 635 interrupts = <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>; 636 }; 637 638 nor_flash: spi@11000000 { 639 compatible = "mediatek,mt8186-nor"; 640 reg = <0 0x11000000 0 0x1000>; 641 clocks = <&topckgen CLK_TOP_SPINOR>, 642 <&infracfg_ao CLK_INFRA_AO_SPINOR>, 643 <&infracfg_ao CLK_INFRA_AO_FLASHIF_133M>, 644 <&infracfg_ao CLK_INFRA_AO_FLASHIF_66M>; 645 clock-names = "spi", "sf", "axi", "axi_s"; 646 assigned-clocks = <&topckgen CLK_TOP_SPINOR>; 647 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>; 648 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 649 status = "disabled"; 650 }; 651 652 auxadc: adc@11001000 { 653 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc"; 654 reg = <0 0x11001000 0 0x1000>; 655 #io-channel-cells = <1>; 656 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 657 clock-names = "main"; 658 }; 659 660 uart0: serial@11002000 { 661 compatible = "mediatek,mt8186-uart", 662 "mediatek,mt6577-uart"; 663 reg = <0 0x11002000 0 0x1000>; 664 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 665 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 666 clock-names = "baud", "bus"; 667 status = "disabled"; 668 }; 669 670 uart1: serial@11003000 { 671 compatible = "mediatek,mt8186-uart", 672 "mediatek,mt6577-uart"; 673 reg = <0 0x11003000 0 0x1000>; 674 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 675 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 676 clock-names = "baud", "bus"; 677 status = "disabled"; 678 }; 679 680 i2c0: i2c@11007000 { 681 compatible = "mediatek,mt8186-i2c"; 682 reg = <0 0x11007000 0 0x1000>, 683 <0 0x10200100 0 0x100>; 684 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 685 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0>, 686 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 687 clock-names = "main", "dma"; 688 clock-div = <1>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 status = "disabled"; 692 }; 693 694 i2c1: i2c@11008000 { 695 compatible = "mediatek,mt8186-i2c"; 696 reg = <0 0x11008000 0 0x1000>, 697 <0 0x10200200 0 0x100>; 698 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 699 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1>, 700 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 701 clock-names = "main", "dma"; 702 clock-div = <1>; 703 #address-cells = <1>; 704 #size-cells = <0>; 705 status = "disabled"; 706 }; 707 708 i2c2: i2c@11009000 { 709 compatible = "mediatek,mt8186-i2c"; 710 reg = <0 0x11009000 0 0x1000>, 711 <0 0x10200300 0 0x180>; 712 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>; 713 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2>, 714 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 715 clock-names = "main", "dma"; 716 clock-div = <1>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 status = "disabled"; 720 }; 721 722 i2c3: i2c@1100f000 { 723 compatible = "mediatek,mt8186-i2c"; 724 reg = <0 0x1100f000 0 0x1000>, 725 <0 0x10200480 0 0x100>; 726 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; 727 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3>, 728 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 729 clock-names = "main", "dma"; 730 clock-div = <1>; 731 #address-cells = <1>; 732 #size-cells = <0>; 733 status = "disabled"; 734 }; 735 736 i2c4: i2c@11011000 { 737 compatible = "mediatek,mt8186-i2c"; 738 reg = <0 0x11011000 0 0x1000>, 739 <0 0x10200580 0 0x180>; 740 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 741 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4>, 742 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 743 clock-names = "main", "dma"; 744 clock-div = <1>; 745 #address-cells = <1>; 746 #size-cells = <0>; 747 status = "disabled"; 748 }; 749 750 i2c5: i2c@11016000 { 751 compatible = "mediatek,mt8186-i2c"; 752 reg = <0 0x11016000 0 0x1000>, 753 <0 0x10200700 0 0x100>; 754 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; 755 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5>, 756 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 757 clock-names = "main", "dma"; 758 clock-div = <1>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 status = "disabled"; 762 }; 763 764 i2c6: i2c@1100d000 { 765 compatible = "mediatek,mt8186-i2c"; 766 reg = <0 0x1100d000 0 0x1000>, 767 <0 0x10200800 0 0x100>; 768 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 769 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6>, 770 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 771 clock-names = "main", "dma"; 772 clock-div = <1>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 status = "disabled"; 776 }; 777 778 i2c7: i2c@11004000 { 779 compatible = "mediatek,mt8186-i2c"; 780 reg = <0 0x11004000 0 0x1000>, 781 <0 0x10200900 0 0x180>; 782 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 783 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7>, 784 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 785 clock-names = "main", "dma"; 786 clock-div = <1>; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 status = "disabled"; 790 }; 791 792 i2c8: i2c@11005000 { 793 compatible = "mediatek,mt8186-i2c"; 794 reg = <0 0x11005000 0 0x1000>, 795 <0 0x10200A80 0 0x180>; 796 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 797 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8>, 798 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 799 clock-names = "main", "dma"; 800 clock-div = <1>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 status = "disabled"; 804 }; 805 806 spi0: spi@1100a000 { 807 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 reg = <0 0x1100a000 0 0x1000>; 811 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH 0>; 812 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 813 <&topckgen CLK_TOP_SPI>, 814 <&infracfg_ao CLK_INFRA_AO_SPI0>; 815 clock-names = "parent-clk", "sel-clk", "spi-clk"; 816 status = "disabled"; 817 }; 818 819 pwm0: pwm@1100e000 { 820 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm"; 821 reg = <0 0x1100e000 0 0x1000>; 822 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 823 #pwm-cells = <2>; 824 clocks = <&topckgen CLK_TOP_DISP_PWM>, 825 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 826 clock-names = "main", "mm"; 827 status = "disabled"; 828 }; 829 830 spi1: spi@11010000 { 831 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 reg = <0 0x11010000 0 0x1000>; 835 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH 0>; 836 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 837 <&topckgen CLK_TOP_SPI>, 838 <&infracfg_ao CLK_INFRA_AO_SPI1>; 839 clock-names = "parent-clk", "sel-clk", "spi-clk"; 840 status = "disabled"; 841 }; 842 843 spi2: spi@11012000 { 844 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 reg = <0 0x11012000 0 0x1000>; 848 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 0>; 849 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 850 <&topckgen CLK_TOP_SPI>, 851 <&infracfg_ao CLK_INFRA_AO_SPI2>; 852 clock-names = "parent-clk", "sel-clk", "spi-clk"; 853 status = "disabled"; 854 }; 855 856 spi3: spi@11013000 { 857 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 reg = <0 0x11013000 0 0x1000>; 861 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>; 862 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 863 <&topckgen CLK_TOP_SPI>, 864 <&infracfg_ao CLK_INFRA_AO_SPI3>; 865 clock-names = "parent-clk", "sel-clk", "spi-clk"; 866 status = "disabled"; 867 }; 868 869 spi4: spi@11014000 { 870 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 reg = <0 0x11014000 0 0x1000>; 874 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 875 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 876 <&topckgen CLK_TOP_SPI>, 877 <&infracfg_ao CLK_INFRA_AO_SPI4>; 878 clock-names = "parent-clk", "sel-clk", "spi-clk"; 879 status = "disabled"; 880 }; 881 882 spi5: spi@11015000 { 883 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 reg = <0 0x11015000 0 0x1000>; 887 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 888 clocks = <&topckgen CLK_TOP_MAINPLL_D5>, 889 <&topckgen CLK_TOP_SPI>, 890 <&infracfg_ao CLK_INFRA_AO_SPI5>; 891 clock-names = "parent-clk", "sel-clk", "spi-clk"; 892 status = "disabled"; 893 }; 894 895 imp_iic_wrap: clock-controller@11017000 { 896 compatible = "mediatek,mt8186-imp_iic_wrap"; 897 reg = <0 0x11017000 0 0x1000>; 898 #clock-cells = <1>; 899 }; 900 901 uart2: serial@11018000 { 902 compatible = "mediatek,mt8186-uart", 903 "mediatek,mt6577-uart"; 904 reg = <0 0x11018000 0 0x1000>; 905 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>; 906 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 907 clock-names = "baud", "bus"; 908 status = "disabled"; 909 }; 910 911 i2c9: i2c@11019000 { 912 compatible = "mediatek,mt8186-i2c"; 913 reg = <0 0x11019000 0 0x1000>, 914 <0 0x10200c00 0 0x180>; 915 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH 0>; 916 clocks = <&imp_iic_wrap CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9>, 917 <&infracfg_ao CLK_INFRA_AO_AP_DMA>; 918 clock-names = "main", "dma"; 919 clock-div = <1>; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 status = "disabled"; 923 }; 924 925 afe: audio-controller@11210000 { 926 compatible = "mediatek,mt8186-sound"; 927 reg = <0 0x11210000 0 0x2000>; 928 clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, 929 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, 930 <&topckgen CLK_TOP_AUDIO>, 931 <&topckgen CLK_TOP_AUD_INTBUS>, 932 <&topckgen CLK_TOP_MAINPLL_D2_D4>, 933 <&topckgen CLK_TOP_AUD_1>, 934 <&apmixedsys CLK_APMIXED_APLL1>, 935 <&topckgen CLK_TOP_AUD_2>, 936 <&apmixedsys CLK_APMIXED_APLL2>, 937 <&topckgen CLK_TOP_AUD_ENGEN1>, 938 <&topckgen CLK_TOP_APLL1_D8>, 939 <&topckgen CLK_TOP_AUD_ENGEN2>, 940 <&topckgen CLK_TOP_APLL2_D8>, 941 <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, 942 <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, 943 <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, 944 <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, 945 <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, 946 <&topckgen CLK_TOP_APLL12_CK_DIV0>, 947 <&topckgen CLK_TOP_APLL12_CK_DIV1>, 948 <&topckgen CLK_TOP_APLL12_CK_DIV2>, 949 <&topckgen CLK_TOP_APLL12_CK_DIV4>, 950 <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, 951 <&topckgen CLK_TOP_AUDIO_H>, 952 <&clk26m>; 953 clock-names = "aud_infra_clk", 954 "mtkaif_26m_clk", 955 "top_mux_audio", 956 "top_mux_audio_int", 957 "top_mainpll_d2_d4", 958 "top_mux_aud_1", 959 "top_apll1_ck", 960 "top_mux_aud_2", 961 "top_apll2_ck", 962 "top_mux_aud_eng1", 963 "top_apll1_d8", 964 "top_mux_aud_eng2", 965 "top_apll2_d8", 966 "top_i2s0_m_sel", 967 "top_i2s1_m_sel", 968 "top_i2s2_m_sel", 969 "top_i2s4_m_sel", 970 "top_tdm_m_sel", 971 "top_apll12_div0", 972 "top_apll12_div1", 973 "top_apll12_div2", 974 "top_apll12_div4", 975 "top_apll12_div_tdm", 976 "top_mux_audio_h", 977 "top_clk26m_clk"; 978 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 979 mediatek,apmixedsys = <&apmixedsys>; 980 mediatek,infracfg = <&infracfg_ao>; 981 mediatek,topckgen = <&topckgen>; 982 resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; 983 reset-names = "audiosys"; 984 status = "disabled"; 985 }; 986 987 mmc0: mmc@11230000 { 988 compatible = "mediatek,mt8186-mmc", 989 "mediatek,mt8183-mmc"; 990 reg = <0 0x11230000 0 0x10000>, 991 <0 0x11cd0000 0 0x1000>; 992 clocks = <&topckgen CLK_TOP_MSDC50_0>, 993 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 994 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>, 995 <&infracfg_ao CLK_INFRA_AO_MSDCFDE>; 996 clock-names = "source", "hclk", "source_cg", "crypto"; 997 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 998 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>; 999 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>; 1000 status = "disabled"; 1001 }; 1002 1003 mmc1: mmc@11240000 { 1004 compatible = "mediatek,mt8186-mmc", 1005 "mediatek,mt8183-mmc"; 1006 reg = <0 0x11240000 0 0x1000>, 1007 <0 0x11c90000 0 0x1000>; 1008 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1009 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1010 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1011 clock-names = "source", "hclk", "source_cg"; 1012 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 1013 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1014 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1015 status = "disabled"; 1016 }; 1017 1018 u3phy0: t-phy@11c80000 { 1019 compatible = "mediatek,mt8186-tphy", 1020 "mediatek,generic-tphy-v2"; 1021 #address-cells = <1>; 1022 #size-cells = <1>; 1023 ranges = <0x0 0x0 0x11c80000 0x1000>; 1024 status = "disabled"; 1025 1026 u2port1: usb-phy@0 { 1027 reg = <0x0 0x700>; 1028 clocks = <&clk26m>; 1029 clock-names = "ref"; 1030 #phy-cells = <1>; 1031 }; 1032 1033 u3port1: usb-phy@700 { 1034 reg = <0x700 0x900>; 1035 clocks = <&clk26m>; 1036 clock-names = "ref"; 1037 #phy-cells = <1>; 1038 }; 1039 }; 1040 1041 u3phy1: t-phy@11ca0000 { 1042 compatible = "mediatek,mt8186-tphy", 1043 "mediatek,generic-tphy-v2"; 1044 #address-cells = <1>; 1045 #size-cells = <1>; 1046 ranges = <0x0 0x0 0x11ca0000 0x1000>; 1047 status = "disabled"; 1048 1049 u2port0: usb-phy@0 { 1050 reg = <0x0 0x700>; 1051 clocks = <&clk26m>; 1052 clock-names = "ref"; 1053 #phy-cells = <1>; 1054 mediatek,discth = <0x8>; 1055 }; 1056 }; 1057 1058 efuse: efuse@11cb0000 { 1059 compatible = "mediatek,mt8186-efuse", "mediatek,efuse"; 1060 reg = <0 0x11cb0000 0 0x1000>; 1061 #address-cells = <1>; 1062 #size-cells = <1>; 1063 }; 1064 1065 mipi_tx0: dsi-phy@11cc0000 { 1066 compatible = "mediatek,mt8183-mipi-tx"; 1067 reg = <0 0x11cc0000 0 0x1000>; 1068 clocks = <&clk26m>; 1069 #clock-cells = <0>; 1070 #phy-cells = <0>; 1071 clock-output-names = "mipi_tx0_pll"; 1072 status = "disabled"; 1073 }; 1074 1075 mfgsys: clock-controller@13000000 { 1076 compatible = "mediatek,mt8186-mfgsys"; 1077 reg = <0 0x13000000 0 0x1000>; 1078 #clock-cells = <1>; 1079 }; 1080 1081 mmsys: syscon@14000000 { 1082 compatible = "mediatek,mt8186-mmsys", "syscon"; 1083 reg = <0 0x14000000 0 0x1000>; 1084 #clock-cells = <1>; 1085 #reset-cells = <1>; 1086 }; 1087 1088 smi_common: smi@14002000 { 1089 compatible = "mediatek,mt8186-smi-common"; 1090 reg = <0 0x14002000 0 0x1000>; 1091 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_COMMON>, 1092 <&mmsys CLK_MM_SMI_GALS>, <&mmsys CLK_MM_SMI_GALS>; 1093 clock-names = "apb", "smi", "gals0", "gals1"; 1094 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1095 }; 1096 1097 larb0: smi@14003000 { 1098 compatible = "mediatek,mt8186-smi-larb"; 1099 reg = <0 0x14003000 0 0x1000>; 1100 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1101 <&mmsys CLK_MM_SMI_COMMON>; 1102 clock-names = "apb", "smi"; 1103 mediatek,larb-id = <0>; 1104 mediatek,smi = <&smi_common>; 1105 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1106 }; 1107 1108 larb1: smi@14004000 { 1109 compatible = "mediatek,mt8186-smi-larb"; 1110 reg = <0 0x14004000 0 0x1000>; 1111 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1112 <&mmsys CLK_MM_SMI_COMMON>; 1113 clock-names = "apb", "smi"; 1114 mediatek,larb-id = <1>; 1115 mediatek,smi = <&smi_common>; 1116 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1117 }; 1118 1119 dpi: dpi@1400a000 { 1120 compatible = "mediatek,mt8186-dpi"; 1121 reg = <0 0x1400a000 0 0x1000>; 1122 clocks = <&topckgen CLK_TOP_DPI>, 1123 <&mmsys CLK_MM_DISP_DPI>, 1124 <&apmixedsys CLK_APMIXED_TVDPLL>; 1125 clock-names = "pixel", "engine", "pll"; 1126 assigned-clocks = <&topckgen CLK_TOP_DPI>; 1127 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>; 1128 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_LOW 0>; 1129 status = "disabled"; 1130 1131 port { 1132 dpi_out: endpoint { }; 1133 }; 1134 }; 1135 1136 dsi0: dsi@14013000 { 1137 compatible = "mediatek,mt8186-dsi"; 1138 reg = <0 0x14013000 0 0x1000>; 1139 clocks = <&mmsys CLK_MM_DSI0>, 1140 <&mmsys CLK_MM_DSI0_DSI_CK_DOMAIN>, 1141 <&mipi_tx0>; 1142 clock-names = "engine", "digital", "hs"; 1143 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 0>; 1144 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1145 resets = <&mmsys MT8186_MMSYS_SW0_RST_B_DISP_DSI0>; 1146 phys = <&mipi_tx0>; 1147 phy-names = "dphy"; 1148 status = "disabled"; 1149 1150 port { 1151 dsi_out: endpoint { }; 1152 }; 1153 }; 1154 1155 iommu_mm: iommu@14016000 { 1156 compatible = "mediatek,mt8186-iommu-mm"; 1157 reg = <0 0x14016000 0 0x1000>; 1158 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1159 clock-names = "bclk"; 1160 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 0>; 1161 mediatek,larbs = <&larb0 &larb1 &larb2 &larb4 1162 &larb7 &larb8 &larb9 &larb11 1163 &larb13 &larb14 &larb16 &larb17 1164 &larb19 &larb20>; 1165 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1166 #iommu-cells = <1>; 1167 }; 1168 1169 wpesys: clock-controller@14020000 { 1170 compatible = "mediatek,mt8186-wpesys"; 1171 reg = <0 0x14020000 0 0x1000>; 1172 #clock-cells = <1>; 1173 }; 1174 1175 larb8: smi@14023000 { 1176 compatible = "mediatek,mt8186-smi-larb"; 1177 reg = <0 0x14023000 0 0x1000>; 1178 clocks = <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, 1179 <&wpesys CLK_WPE_SMI_LARB8_CK_EN>; 1180 clock-names = "apb", "smi"; 1181 mediatek,larb-id = <8>; 1182 mediatek,smi = <&smi_common>; 1183 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>; 1184 }; 1185 1186 imgsys1: clock-controller@15020000 { 1187 compatible = "mediatek,mt8186-imgsys1"; 1188 reg = <0 0x15020000 0 0x1000>; 1189 #clock-cells = <1>; 1190 }; 1191 1192 larb9: smi@1502e000 { 1193 compatible = "mediatek,mt8186-smi-larb"; 1194 reg = <0 0x1502e000 0 0x1000>; 1195 clocks = <&imgsys1 CLK_IMG1_GALS_IMG1>, 1196 <&imgsys1 CLK_IMG1_LARB9_IMG1>; 1197 clock-names = "apb", "smi"; 1198 mediatek,larb-id = <9>; 1199 mediatek,smi = <&smi_common>; 1200 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>; 1201 }; 1202 1203 imgsys2: clock-controller@15820000 { 1204 compatible = "mediatek,mt8186-imgsys2"; 1205 reg = <0 0x15820000 0 0x1000>; 1206 #clock-cells = <1>; 1207 }; 1208 1209 larb11: smi@1582e000 { 1210 compatible = "mediatek,mt8186-smi-larb"; 1211 reg = <0 0x1582e000 0 0x1000>; 1212 clocks = <&imgsys1 CLK_IMG1_LARB9_IMG1>, 1213 <&imgsys2 CLK_IMG2_LARB9_IMG2>; 1214 clock-names = "apb", "smi"; 1215 mediatek,larb-id = <11>; 1216 mediatek,smi = <&smi_common>; 1217 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>; 1218 }; 1219 1220 larb4: smi@1602e000 { 1221 compatible = "mediatek,mt8186-smi-larb"; 1222 reg = <0 0x1602e000 0 0x1000>; 1223 clocks = <&vdecsys CLK_VDEC_LARB1_CKEN>, 1224 <&vdecsys CLK_VDEC_LARB1_CKEN>; 1225 clock-names = "apb", "smi"; 1226 mediatek,larb-id = <4>; 1227 mediatek,smi = <&smi_common>; 1228 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>; 1229 }; 1230 1231 vdecsys: clock-controller@1602f000 { 1232 compatible = "mediatek,mt8186-vdecsys"; 1233 reg = <0 0x1602f000 0 0x1000>; 1234 #clock-cells = <1>; 1235 }; 1236 1237 vencsys: clock-controller@17000000 { 1238 compatible = "mediatek,mt8186-vencsys"; 1239 reg = <0 0x17000000 0 0x1000>; 1240 #clock-cells = <1>; 1241 }; 1242 1243 larb7: smi@17010000 { 1244 compatible = "mediatek,mt8186-smi-larb"; 1245 reg = <0 0x17010000 0 0x1000>; 1246 clocks = <&vencsys CLK_VENC_CKE1_VENC>, 1247 <&vencsys CLK_VENC_CKE1_VENC>; 1248 clock-names = "apb", "smi"; 1249 mediatek,larb-id = <7>; 1250 mediatek,smi = <&smi_common>; 1251 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>; 1252 }; 1253 1254 camsys: clock-controller@1a000000 { 1255 compatible = "mediatek,mt8186-camsys"; 1256 reg = <0 0x1a000000 0 0x1000>; 1257 #clock-cells = <1>; 1258 }; 1259 1260 larb13: smi@1a001000 { 1261 compatible = "mediatek,mt8186-smi-larb"; 1262 reg = <0 0x1a001000 0 0x1000>; 1263 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB13>; 1264 clock-names = "apb", "smi"; 1265 mediatek,larb-id = <13>; 1266 mediatek,smi = <&smi_common>; 1267 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1268 }; 1269 1270 larb14: smi@1a002000 { 1271 compatible = "mediatek,mt8186-smi-larb"; 1272 reg = <0 0x1a002000 0 0x1000>; 1273 clocks = <&camsys CLK_CAM2MM_GALS>, <&camsys CLK_CAM_LARB14>; 1274 clock-names = "apb", "smi"; 1275 mediatek,larb-id = <14>; 1276 mediatek,smi = <&smi_common>; 1277 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>; 1278 }; 1279 1280 larb16: smi@1a00f000 { 1281 compatible = "mediatek,mt8186-smi-larb"; 1282 reg = <0 0x1a00f000 0 0x1000>; 1283 clocks = <&camsys CLK_CAM_LARB14>, 1284 <&camsys_rawa CLK_CAM_RAWA_LARBX_RAWA>; 1285 clock-names = "apb", "smi"; 1286 mediatek,larb-id = <16>; 1287 mediatek,smi = <&smi_common>; 1288 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>; 1289 }; 1290 1291 larb17: smi@1a010000 { 1292 compatible = "mediatek,mt8186-smi-larb"; 1293 reg = <0 0x1a010000 0 0x1000>; 1294 clocks = <&camsys CLK_CAM_LARB13>, 1295 <&camsys_rawb CLK_CAM_RAWB_LARBX_RAWB>; 1296 clock-names = "apb", "smi"; 1297 mediatek,larb-id = <17>; 1298 mediatek,smi = <&smi_common>; 1299 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>; 1300 }; 1301 1302 camsys_rawa: clock-controller@1a04f000 { 1303 compatible = "mediatek,mt8186-camsys_rawa"; 1304 reg = <0 0x1a04f000 0 0x1000>; 1305 #clock-cells = <1>; 1306 }; 1307 1308 camsys_rawb: clock-controller@1a06f000 { 1309 compatible = "mediatek,mt8186-camsys_rawb"; 1310 reg = <0 0x1a06f000 0 0x1000>; 1311 #clock-cells = <1>; 1312 }; 1313 1314 mdpsys: clock-controller@1b000000 { 1315 compatible = "mediatek,mt8186-mdpsys"; 1316 reg = <0 0x1b000000 0 0x1000>; 1317 #clock-cells = <1>; 1318 }; 1319 1320 larb2: smi@1b002000 { 1321 compatible = "mediatek,mt8186-smi-larb"; 1322 reg = <0 0x1b002000 0 0x1000>; 1323 clocks = <&mdpsys CLK_MDP_SMI0>, <&mdpsys CLK_MDP_SMI0>; 1324 clock-names = "apb", "smi"; 1325 mediatek,larb-id = <2>; 1326 mediatek,smi = <&smi_common>; 1327 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; 1328 }; 1329 1330 ipesys: clock-controller@1c000000 { 1331 compatible = "mediatek,mt8186-ipesys"; 1332 reg = <0 0x1c000000 0 0x1000>; 1333 #clock-cells = <1>; 1334 }; 1335 1336 larb20: smi@1c00f000 { 1337 compatible = "mediatek,mt8186-smi-larb"; 1338 reg = <0 0x1c00f000 0 0x1000>; 1339 clocks = <&ipesys CLK_IPE_LARB20>, <&ipesys CLK_IPE_LARB20>; 1340 clock-names = "apb", "smi"; 1341 mediatek,larb-id = <20>; 1342 mediatek,smi = <&smi_common>; 1343 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1344 }; 1345 1346 larb19: smi@1c10f000 { 1347 compatible = "mediatek,mt8186-smi-larb"; 1348 reg = <0 0x1c10f000 0 0x1000>; 1349 clocks = <&ipesys CLK_IPE_LARB19>, <&ipesys CLK_IPE_LARB19>; 1350 clock-names = "apb", "smi"; 1351 mediatek,larb-id = <19>; 1352 mediatek,smi = <&smi_common>; 1353 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>; 1354 }; 1355 }; 1356}; 1357