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/openbmc/u-boot/arch/arm/dts/
H A Dkeystone-k2hk-clocks.dtsi13 #clock-cells = <0>;
17 reg = <0x02620370 4>;
22 #clock-cells = <0>;
25 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
30 #clock-cells = <0>;
34 reg = <0x02620358 4>;
39 #clock-cells = <0>;
43 reg = <0x02620360 4>;
48 #clock-cells = <0>;
52 reg = <0x02620368 4>;
[all …]
H A Dkeystone-k2l-clocks.dtsi13 #clock-cells = <0>;
17 reg = <0x02620370 4>;
22 #clock-cells = <0>;
25 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
30 #clock-cells = <0>;
34 reg = <0x02620358 4>;
39 #clock-cells = <0>;
43 reg = <0x02620360 4>;
48 #clock-cells = <0>;
53 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
[all …]
H A Dkeystone-clocks.dtsi17 #clock-cells = <0>;
20 reg = <0x02310108 4>;
27 #clock-cells = <0>;
36 #clock-cells = <0>;
45 #clock-cells = <0>;
48 reg = <0x02310120 4>;
49 bit-shift = <0>;
55 #clock-cells = <0>;
58 reg = <0x02310164 4>;
59 bit-shift = <0>;
[all …]
H A Dkeystone-k2e-clocks.dtsi13 #clock-cells = <0>;
16 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
21 #clock-cells = <0>;
25 reg = <0x02620358 4>;
30 #clock-cells = <0>;
34 reg = <0x02620360 4>;
39 #clock-cells = <0>;
43 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
45 domain-id = <0>;
49 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2hk-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
49 reg = <0x02620368 4>;
[all …]
H A Dkeystone-k2l-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x02620370 4>;
19 #clock-cells = <0>;
22 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
27 #clock-cells = <0>;
31 reg = <0x02620358 4>;
36 #clock-cells = <0>;
40 reg = <0x02620360 4>;
45 #clock-cells = <0>;
50 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
[all …]
H A Dkeystone-clocks.dtsi14 #clock-cells = <0>;
17 reg = <0x02310108 4>;
24 #clock-cells = <0>;
33 #clock-cells = <0>;
42 #clock-cells = <0>;
45 reg = <0x02310120 4>;
46 bit-shift = <0>;
52 #clock-cells = <0>;
55 reg = <0x02310164 4>;
56 bit-shift = <0>;
[all …]
H A Dkeystone-k2e-clocks.dtsi10 #clock-cells = <0>;
13 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
18 #clock-cells = <0>;
22 reg = <0x02620358 4>;
27 #clock-cells = <0>;
31 reg = <0x02620360 4>;
36 #clock-cells = <0>;
40 reg = <0x02350004 0xb00>, <0x02350000 0x400>;
42 domain-id = <0>;
46 #clock-cells = <0>;
[all …]
/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8127.c19 /* 0E4E8SR 4/8/12/16 */
21 /* 0E2E4SR 2/4/6/8 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
29 MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
30 MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
31 MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
32 MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
33 MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
34 MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
[all …]
H A Dpinctrl-mt6795.c11 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
12 _x_bits, 15, 0)
15 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
16 _x_bits, 16, 0)
19 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
23 PIN_FIELD16(0, 196, 0x0, 0x10, 0, 1),
27 PIN_FIELD16(0, 196, 0x100, 0x10, 0, 1),
31 PIN_FIELD16(0, 196, 0x200, 0x10, 0, 1),
35 PIN_FIELD16(0, 196, 0x400, 0x10, 0, 1),
39 PIN_FIELD16(0, 196, 0x500, 0x10, 0, 1),
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-audio.c15 #define CX18_AUDIO_ENABLE 0xc72014
16 #define CX18_AI1_MUX_MASK 0x30
17 #define CX18_AI1_MUX_I2S1 0x00
18 #define CX18_AI1_MUX_I2S2 0x10
19 #define CX18_AI1_MUX_843_I2S 0x20
37 (u32) in->muxer_input, 0, 0); in cx18_audio_set_io()
40 audio, s_routing, in->audio_input, 0, 0); in cx18_audio_set_io()
72 cx18_write_reg_expect(cx, u | 0xb00, CX18_AUDIO_ENABLE, in cx18_audio_set_io()
75 cx18_write_reg_expect(cx, v | 0xb00, CX18_AUDIO_ENABLE, in cx18_audio_set_io()
77 return 0; in cx18_audio_set_io()
H A Dcx18-av-firmware.c13 #define CX18_AUDIO_ENABLE 0xc72014
14 #define CX18_AI1_MUX_MASK 0x30
15 #define CX18_AI1_MUX_I2S1 0x00
16 #define CX18_AI1_MUX_I2S2 0x10
17 #define CX18_AI1_MUX_843_I2S 0x20
18 #define CX18_AI1_MUX_INVALID 0x30
25 int ret = 0; in cx18_av_verifyfw()
34 dl_control &= 0x00ffffff; in cx18_av_verifyfw()
35 dl_control |= 0x0f000000; in cx18_av_verifyfw()
38 } while ((dl_control & 0xff000000) != 0x0f000000); in cx18_av_verifyfw()
[all …]
/openbmc/linux/drivers/staging/rtl8723bs/include/
H A Dhal_phy_reg_8723b.h14 /* 4. Page9(0x900) */
16 #define rDPDT_control 0x92c
17 #define rfe_ctrl_anta_src 0x930
18 #define rS0S1_PathSwitch 0x948
19 #define AGC_table_select 0xb2c
22 /* PageB(0xB00) */
24 #define rPdp_AntA 0xb00
25 #define rPdp_AntA_4 0xb04
26 #define rPdp_AntA_8 0xb08
27 #define rPdp_AntA_C 0xb0c
[all …]
/openbmc/linux/arch/sh/include/cpu-sh4a/cpu/
H A Ddma.h9 #define DMTE0_IRQ evt2irq(0x800)
10 #define DMTE4_IRQ evt2irq(0xb80)
11 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
12 #define SH_DMAC_BASE0 0xFE008020
14 #define DMTE0_IRQ evt2irq(0x800)
15 #define DMTE4_IRQ evt2irq(0xb80)
16 #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
17 #define SH_DMAC_BASE0 0xFE008020
19 #define DMTE0_IRQ evt2irq(0x640)
20 #define DMTE4_IRQ evt2irq(0x780)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dkeystone-gate.txt11 - #clock-cells : from common clock binding; shall be set to 0.
22 #clock-cells = <0>;
26 reg = <0x02350008 0xb00>, <0x02350000 0x400>;
28 domain-id = <0>;
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dralink,mt7621-spi.yaml50 reg = <0xb00 0x100>;
57 #size-cells = <0>;
60 pinctrl-0 = <&spi_pins>;
/openbmc/linux/include/dt-bindings/clock/
H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/openbmc/u-boot/include/
H A Dfsl_sec_mon.h31 u8 reserved0[0x04];
32 u32 hp_com; /* 0x04 SEC_MON_HP Command Register */
33 u8 reserved2[0x0c];
34 u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */
37 #define HPCOMR_SW_SV 0x100 /* Security Violation bit */
38 #define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */
39 #define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */
40 #define HPCOMR_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */
41 #define HPCOMR_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */
42 #define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */
[all …]
/openbmc/linux/drivers/watchdog/
H A Dsp5100_tco.h15 #define SP5100_WDT_MEM_MAP_SIZE 0x08
16 #define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */
17 #define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */
19 #define SP5100_WDT_START_STOP_BIT BIT(0)
25 #define SP5100_PM_IOPORTS_SIZE 0x02
33 #define SP5100_IO_PM_INDEX_REG 0xCD6
34 #define SP5100_IO_PM_DATA_REG 0xCD7
37 #define SP5100_SB_RESOURCE_MMIO_BASE 0x9C
39 #define SP5100_PM_WATCHDOG_CONTROL 0x69
40 #define SP5100_PM_WATCHDOG_BASE 0x6C
[all …]
/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dpmc.txt61 reg = <0xb00 0x100 0xa00 0x100>;
/openbmc/linux/arch/sh/kernel/cpu/sh4/
H A Dsetup-sh7760.c17 UNUSED = 0,
44 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
45 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
46 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
47 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
48 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
49 INTC_VECT(DMAC, 0x6c0),
50 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
51 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
52 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
[all …]
H A Dsetup-sh7750.c19 [0] = {
20 .start = 0xffc80000,
21 .end = 0xffc80000 + 0x58 - 1,
26 .start = evt2irq(0x480),
43 DEFINE_RES_MEM(0xffe00000, 0x20),
44 DEFINE_RES_IRQ(evt2irq(0x4e0)),
49 .id = 0,
63 DEFINE_RES_MEM(0xffe80000, 0x100),
64 DEFINE_RES_IRQ(evt2irq(0x700)),
82 DEFINE_RES_MEM(0xffd80000, 0x30),
[all …]
/openbmc/linux/sound/soc/amd/raven/
H A Dacp3x.h10 #define I2S_SP_INSTANCE 0x01
11 #define I2S_BT_INSTANCE 0x02
14 #define TDM_DISABLE 0
17 #define ACP3x_PHY_BASE_ADDRESS 0x1240000
18 #define ACP3x_I2S_MODE 0
19 #define ACP3x_REG_START 0x1240000
20 #define ACP3x_REG_END 0x1250200
21 #define ACP3x_I2STDM_REG_START 0x1242400
22 #define ACP3x_I2STDM_REG_END 0x1242410
23 #define ACP3x_BT_TDM_REG_START 0x1242800
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dgrf_rk3328.h31 u32 reserved1[(0x100 - 0x54) / 4];
49 u32 reserved2[(0x200 - 0x140) / 4];
66 u32 reserved3[(0x300 - 0x240) / 4];
75 u32 reserved4[(0x380 - 0x320) / 4];
84 u32 reserved5[(0x400 - 0x3a0) / 4];
86 u32 reserved6[(0x480 - 0x42c) / 4];
88 u32 reserved7[(0x4c0 - 0x494) / 4];
90 u32 reserved8[(0x500 - 0x4c8) / 4];
92 u32 reserved9[(0x520 - 0x508) / 4];
94 u32 reserved10[(0x5c8 - 0x528) / 4];
[all …]
H A Dgrf_rk322x.h33 unsigned int reserved2[(0x100 - 0x50) / 4 - 1];
38 unsigned int reserved3[(0x200 - 0x13c) / 4 - 1];
43 unsigned int reserved4[(0x400 - 0x23c) / 4 - 1];
45 unsigned int reserved5[(0x480 - 0x418) / 4 - 1];
48 unsigned int reserved6[(0x500 - 0x48c) / 4 - 1];
52 unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1];
54 unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
56 unsigned int reserved10[(0x680 - 0x604) / 4 - 1];
58 unsigned int reserved11[(0x690 - 0x684) / 4 - 1];
60 unsigned int reserved12[(0x6a0 - 0x694) / 4 - 1];
[all …]

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