Lines Matching +full:0 +full:xb00

13 		#clock-cells = <0>;
17 		reg = <0x02620370 4>;
22 		#clock-cells = <0>;
25 		reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
30 		#clock-cells = <0>;
34 		reg = <0x02620358 4>;
39 		#clock-cells = <0>;
43 		reg = <0x02620360 4>;
48 		#clock-cells = <0>;
52 		reg = <0x02620368 4>;
57 		#clock-cells = <0>;
61 		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
63 		domain-id = <0>;
67 		#clock-cells = <0>;
71 		reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
77 		#clock-cells = <0>;
80 		clock-output-names = "hyperlink-0";
81 		reg = <0x02350030 0xb00>, <0x02350014 0x400>;
87 		#clock-cells = <0>;
91 		reg = <0x02350040 0xb00>, <0x02350024 0x400>;
97 		#clock-cells = <0>;
101 		reg = <0x02350044 0xb00>, <0x02350028 0x400>;
107 		#clock-cells = <0>;
111 		reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
117 		#clock-cells = <0>;
121 		reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
127 		#clock-cells = <0>;
131 		reg = <0x02350050 0xb00>, <0x02350034 0x400>;
137 		#clock-cells = <0>;
141 		reg = <0x02350054 0xb00>, <0x02350038 0x400>;
147 		#clock-cells = <0>;
151 		reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
157 		#clock-cells = <0>;
161 		reg = <0x02350060 0xb00>, <0x02350040 0x400>;
167 		#clock-cells = <0>;
171 		reg = <0x02350064 0xb00>, <0x02350044 0x400>;
177 		#clock-cells = <0>;
181 		reg = <0x02350068 0xb00>, <0x02350044 0x400>;
187 		#clock-cells = <0>;
191 		reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
197 		#clock-cells = <0>;
200 		clock-output-names = "fftc-0";
201 		reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
207 		#clock-cells = <0>;
211 		reg = <0x02350074 0xb00>, <0x0235004c 0x400>;
217 		#clock-cells = <0>;
221 		reg = <0x02350078 0xb00>, <0x02350050 0x400>;
227 		#clock-cells = <0>;
231 		reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
237 		#clock-cells = <0>;
241 		reg = <0x02350080 0xb00>, <0x02350050 0x400>;
247 		#clock-cells = <0>;
251 		reg = <0x02350084 0xb00>, <0x02350050 0x400>;
257 		#clock-cells = <0>;
261 		reg = <0x02350088 0xb00>, <0x02350054 0x400>;
267 		#clock-cells = <0>;
270 		clock-output-names = "tcp3d-0";
271 		reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
277 		#clock-cells = <0>;
281 		reg = <0x02350090 0xb00>, <0x02350058 0x400>;
287 		#clock-cells = <0>;
291 		reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
297 		#clock-cells = <0>;
301 		reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
307 		#clock-cells = <0>;
310 		clock-output-names = "vcp-0";
311 		reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
317 		#clock-cells = <0>;
321 		reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
327 		#clock-cells = <0>;
331 		reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
337 		#clock-cells = <0>;
341 		reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
347 		#clock-cells = <0>;
351 		reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
357 		#clock-cells = <0>;
361 		reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
367 		#clock-cells = <0>;
371 		reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
377 		#clock-cells = <0>;
381 		reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
387 		#clock-cells = <0>;
391 		reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
397 		#clock-cells = <0>;
401 		reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
407 		#clock-cells = <0>;
411 		reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
417 		#clock-cells = <0>;
421 		reg = <0x023500c8 0xb00>, <0x02350074 0x400>;