1d524dac9SGrant Likely* Power Management Controller 2d524dac9SGrant Likely 3d524dac9SGrant LikelyProperties: 4d524dac9SGrant Likely- compatible: "fsl,<chip>-pmc". 5d524dac9SGrant Likely 6d524dac9SGrant Likely "fsl,mpc8349-pmc" should be listed for any chip whose PMC is 7d524dac9SGrant Likely compatible. "fsl,mpc8313-pmc" should also be listed for any chip 8d524dac9SGrant Likely whose PMC is compatible, and implies deep-sleep capability. 9d524dac9SGrant Likely 10d524dac9SGrant Likely "fsl,mpc8548-pmc" should be listed for any chip whose PMC is 11d524dac9SGrant Likely compatible. "fsl,mpc8536-pmc" should also be listed for any chip 12d524dac9SGrant Likely whose PMC is compatible, and implies deep-sleep capability. 13d524dac9SGrant Likely 14d524dac9SGrant Likely "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is 15d524dac9SGrant Likely compatible; all statements below that apply to "fsl,mpc8548-pmc" also 16d524dac9SGrant Likely apply to "fsl,mpc8641d-pmc". 17d524dac9SGrant Likely 18d524dac9SGrant Likely Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these 19d524dac9SGrant Likely bit assignments are indicated via the sleep specifier in each device's 20d524dac9SGrant Likely sleep property. 21d524dac9SGrant Likely 22d524dac9SGrant Likely- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource 23d524dac9SGrant Likely is the PMC block, and the second resource is the Clock Configuration 24d524dac9SGrant Likely block. 25d524dac9SGrant Likely 26d524dac9SGrant Likely For devices compatible with "fsl,mpc8548-pmc", the first resource 27d524dac9SGrant Likely is a 32-byte block beginning with DEVDISR. 28d524dac9SGrant Likely 29d524dac9SGrant Likely- interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first 30d524dac9SGrant Likely resource is the PMC block interrupt. 31d524dac9SGrant Likely 32d524dac9SGrant Likely- fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices, 33d524dac9SGrant Likely this is a phandle to an "fsl,gtm" node on which timer 4 can be used as 34d524dac9SGrant Likely a wakeup source from deep sleep. 35d524dac9SGrant Likely 36d524dac9SGrant LikelySleep specifiers: 37d524dac9SGrant Likely 38d524dac9SGrant Likely fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit 39d524dac9SGrant Likely that is set in the cell, the corresponding bit in SCCR will be saved 40d524dac9SGrant Likely and cleared on suspend, and restored on resume. This sleep controller 41d524dac9SGrant Likely supports disabling and resuming devices at any time. 42d524dac9SGrant Likely 43d524dac9SGrant Likely fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of 44d524dac9SGrant Likely which will be ORed into PMCDR upon suspend, and cleared from PMCDR 45d524dac9SGrant Likely upon resume. The first two cells are as described for fsl,mpc8578-pmc. 46d524dac9SGrant Likely This sleep controller only supports disabling devices during system 47d524dac9SGrant Likely sleep, or permanently. 48d524dac9SGrant Likely 49d524dac9SGrant Likely fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the 50d524dac9SGrant Likely first of which will be ORed into DEVDISR (and the second into 51d524dac9SGrant Likely DEVDISR2, if present -- this cell should be zero or absent if the 52d524dac9SGrant Likely hardware does not have DEVDISR2) upon a request for permanent device 53d524dac9SGrant Likely disabling. This sleep controller does not support configuring devices 54d524dac9SGrant Likely to disable during system sleep (unless supported by another compatible 55d524dac9SGrant Likely match), or dynamically. 56d524dac9SGrant Likely 57d524dac9SGrant LikelyExample: 58d524dac9SGrant Likely 59d524dac9SGrant Likely power@b00 { 60d524dac9SGrant Likely compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; 61d524dac9SGrant Likely reg = <0xb00 0x100 0xa00 0x100>; 62d524dac9SGrant Likely interrupts = <80 8>; 63d524dac9SGrant Likely }; 64