Lines Matching +full:0 +full:xb00
17 UNUSED = 0,
44 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
45 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
46 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
47 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
48 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
49 INTC_VECT(DMAC, 0x6c0),
50 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
51 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
52 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
53 INTC_VECT(SSI0, 0x940), INTC_VECT(SSI1, 0x960),
54 INTC_VECT(HAC0, 0x980), INTC_VECT(HAC1, 0x9a0),
55 INTC_VECT(I2C0, 0x9c0), INTC_VECT(I2C1, 0x9e0),
56 INTC_VECT(USB, 0xa00), INTC_VECT(LCDC, 0xa20),
57 INTC_VECT(DMABRG0, 0xa80), INTC_VECT(DMABRG1, 0xaa0),
58 INTC_VECT(DMABRG2, 0xac0),
59 INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
60 INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
61 INTC_VECT(SCIF1_ERI, 0xb00), INTC_VECT(SCIF1_RXI, 0xb20),
62 INTC_VECT(SCIF1_BRI, 0xb40), INTC_VECT(SCIF1_TXI, 0xb60),
63 INTC_VECT(SCIF2_ERI, 0xb80), INTC_VECT(SCIF2_RXI, 0xba0),
64 INTC_VECT(SCIF2_BRI, 0xbc0), INTC_VECT(SCIF2_TXI, 0xbe0),
65 INTC_VECT(SIM_ERI, 0xc00), INTC_VECT(SIM_RXI, 0xc20),
66 INTC_VECT(SIM_TXI, 0xc40), INTC_VECT(SIM_TEI, 0xc60),
67 INTC_VECT(HSPI, 0xc80),
68 INTC_VECT(MMCIF0, 0xd00), INTC_VECT(MMCIF1, 0xd20),
69 INTC_VECT(MMCIF2, 0xd40), INTC_VECT(MMCIF3, 0xd60),
70 INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
71 INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
72 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
73 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
74 INTC_VECT(WDT, 0x560),
75 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
88 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
89 { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21,
91 0, DMABRG0, DMABRG1, DMABRG2,
95 { 0xfe080044, 0xfe080064, 32, /* INTMSK04 / INTMSKCLR04 */
96 { 0, 0, 0, 0, 0, 0, 0, 0,
99 MMCIF3, 0, 0, 0, 0, 0, 0, 0,
100 0, MFI, 0, 0, 0, 0, ADC, CMT, } },
104 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
105 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
106 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } },
107 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
108 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
109 { 0xfe080004, 0, 32, 4, /* INTPRI04 */ { HCAN20, HCAN21, SSI0, SSI1,
111 { 0xfe080008, 0, 32, 4, /* INTPRI08 */ { USB, LCDC, DMABRG, SCIF0,
113 { 0xfe08000c, 0, 32, 4, /* INTPRI0C */ { 0, 0, MMCIF, 0,
114 MFI, 0, ADC, CMT } },
121 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
122 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
135 DEFINE_RES_MEM(0xfe600000, 0x100),
136 DEFINE_RES_IRQ(evt2irq(0x880)),
137 DEFINE_RES_IRQ(evt2irq(0x8a0)),
138 DEFINE_RES_IRQ(evt2irq(0x8e0)),
139 DEFINE_RES_IRQ(evt2irq(0x8c0)),
144 .id = 0,
159 DEFINE_RES_MEM(0xfe610000, 0x100),
160 DEFINE_RES_IRQ(evt2irq(0xb00)),
161 DEFINE_RES_IRQ(evt2irq(0xb20)),
162 DEFINE_RES_IRQ(evt2irq(0xb60)),
163 DEFINE_RES_IRQ(evt2irq(0xb40)),
183 DEFINE_RES_MEM(0xfe620000, 0x100),
184 DEFINE_RES_IRQ(evt2irq(0xb80)),
185 DEFINE_RES_IRQ(evt2irq(0xba0)),
186 DEFINE_RES_IRQ(evt2irq(0xbe0)),
187 DEFINE_RES_IRQ(evt2irq(0xbc0)),
212 DEFINE_RES_MEM(0xfe480000, 0x10),
213 DEFINE_RES_IRQ(evt2irq(0xc00)),
214 DEFINE_RES_IRQ(evt2irq(0xc20)),
215 DEFINE_RES_IRQ(evt2irq(0xc40)),
233 DEFINE_RES_MEM(0xffd80000, 0x30),
234 DEFINE_RES_IRQ(evt2irq(0x400)),
235 DEFINE_RES_IRQ(evt2irq(0x420)),
236 DEFINE_RES_IRQ(evt2irq(0x440)),
241 .id = 0,
279 #define INTC_ICR 0xffd00000UL