1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Keystone 2 Kepler/Hawking SoC clock nodes 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/ 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herringclocks { 9*724ba675SRob Herring armpllclk: armpllclk@2620370 { 10*724ba675SRob Herring #clock-cells = <0>; 11*724ba675SRob Herring compatible = "ti,keystone,pll-clock"; 12*724ba675SRob Herring clocks = <&refclkarm>; 13*724ba675SRob Herring clock-output-names = "arm-pll-clk"; 14*724ba675SRob Herring reg = <0x02620370 4>; 15*724ba675SRob Herring reg-names = "control"; 16*724ba675SRob Herring }; 17*724ba675SRob Herring 18*724ba675SRob Herring mainpllclk: mainpllclk@2310110 { 19*724ba675SRob Herring #clock-cells = <0>; 20*724ba675SRob Herring compatible = "ti,keystone,main-pll-clock"; 21*724ba675SRob Herring clocks = <&refclksys>; 22*724ba675SRob Herring reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; 23*724ba675SRob Herring reg-names = "control", "multiplier", "post-divider"; 24*724ba675SRob Herring }; 25*724ba675SRob Herring 26*724ba675SRob Herring papllclk: papllclk@2620358 { 27*724ba675SRob Herring #clock-cells = <0>; 28*724ba675SRob Herring compatible = "ti,keystone,pll-clock"; 29*724ba675SRob Herring clocks = <&refclkpass>; 30*724ba675SRob Herring clock-output-names = "papllclk"; 31*724ba675SRob Herring reg = <0x02620358 4>; 32*724ba675SRob Herring reg-names = "control"; 33*724ba675SRob Herring }; 34*724ba675SRob Herring 35*724ba675SRob Herring ddr3apllclk: ddr3apllclk@2620360 { 36*724ba675SRob Herring #clock-cells = <0>; 37*724ba675SRob Herring compatible = "ti,keystone,pll-clock"; 38*724ba675SRob Herring clocks = <&refclkddr3a>; 39*724ba675SRob Herring clock-output-names = "ddr-3a-pll-clk"; 40*724ba675SRob Herring reg = <0x02620360 4>; 41*724ba675SRob Herring reg-names = "control"; 42*724ba675SRob Herring }; 43*724ba675SRob Herring 44*724ba675SRob Herring ddr3bpllclk: ddr3bpllclk@2620368 { 45*724ba675SRob Herring #clock-cells = <0>; 46*724ba675SRob Herring compatible = "ti,keystone,pll-clock"; 47*724ba675SRob Herring clocks = <&refclkddr3b>; 48*724ba675SRob Herring clock-output-names = "ddr-3b-pll-clk"; 49*724ba675SRob Herring reg = <0x02620368 4>; 50*724ba675SRob Herring reg-names = "control"; 51*724ba675SRob Herring }; 52*724ba675SRob Herring 53*724ba675SRob Herring clktsip: clktsip@2350000 { 54*724ba675SRob Herring #clock-cells = <0>; 55*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 56*724ba675SRob Herring clocks = <&chipclk16>; 57*724ba675SRob Herring clock-output-names = "tsip"; 58*724ba675SRob Herring reg = <0x02350000 0xb00>, <0x02350000 0x400>; 59*724ba675SRob Herring reg-names = "control", "domain"; 60*724ba675SRob Herring domain-id = <0>; 61*724ba675SRob Herring }; 62*724ba675SRob Herring 63*724ba675SRob Herring clksrio: clksrio@235002c { 64*724ba675SRob Herring #clock-cells = <0>; 65*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 66*724ba675SRob Herring clocks = <&chipclk1rstiso13>; 67*724ba675SRob Herring clock-output-names = "srio"; 68*724ba675SRob Herring reg = <0x0235002c 0xb00>, <0x02350010 0x400>; 69*724ba675SRob Herring reg-names = "control", "domain"; 70*724ba675SRob Herring domain-id = <4>; 71*724ba675SRob Herring }; 72*724ba675SRob Herring 73*724ba675SRob Herring clkhyperlink0: clkhyperlink0@2350030 { 74*724ba675SRob Herring #clock-cells = <0>; 75*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 76*724ba675SRob Herring clocks = <&chipclk12>; 77*724ba675SRob Herring clock-output-names = "hyperlink-0"; 78*724ba675SRob Herring reg = <0x02350030 0xb00>, <0x02350014 0x400>; 79*724ba675SRob Herring reg-names = "control", "domain"; 80*724ba675SRob Herring domain-id = <5>; 81*724ba675SRob Herring }; 82*724ba675SRob Herring 83*724ba675SRob Herring clkgem1: clkgem1@2350040 { 84*724ba675SRob Herring #clock-cells = <0>; 85*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 86*724ba675SRob Herring clocks = <&chipclk1>; 87*724ba675SRob Herring clock-output-names = "gem1"; 88*724ba675SRob Herring reg = <0x02350040 0xb00>, <0x02350024 0x400>; 89*724ba675SRob Herring reg-names = "control", "domain"; 90*724ba675SRob Herring domain-id = <9>; 91*724ba675SRob Herring }; 92*724ba675SRob Herring 93*724ba675SRob Herring clkgem2: clkgem2@2350044 { 94*724ba675SRob Herring #clock-cells = <0>; 95*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 96*724ba675SRob Herring clocks = <&chipclk1>; 97*724ba675SRob Herring clock-output-names = "gem2"; 98*724ba675SRob Herring reg = <0x02350044 0xb00>, <0x02350028 0x400>; 99*724ba675SRob Herring reg-names = "control", "domain"; 100*724ba675SRob Herring domain-id = <10>; 101*724ba675SRob Herring }; 102*724ba675SRob Herring 103*724ba675SRob Herring clkgem3: clkgem3@2350048 { 104*724ba675SRob Herring #clock-cells = <0>; 105*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 106*724ba675SRob Herring clocks = <&chipclk1>; 107*724ba675SRob Herring clock-output-names = "gem3"; 108*724ba675SRob Herring reg = <0x02350048 0xb00>, <0x0235002c 0x400>; 109*724ba675SRob Herring reg-names = "control", "domain"; 110*724ba675SRob Herring domain-id = <11>; 111*724ba675SRob Herring }; 112*724ba675SRob Herring 113*724ba675SRob Herring clkgem4: clkgem4@235004c { 114*724ba675SRob Herring #clock-cells = <0>; 115*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 116*724ba675SRob Herring clocks = <&chipclk1>; 117*724ba675SRob Herring clock-output-names = "gem4"; 118*724ba675SRob Herring reg = <0x0235004c 0xb00>, <0x02350030 0x400>; 119*724ba675SRob Herring reg-names = "control", "domain"; 120*724ba675SRob Herring domain-id = <12>; 121*724ba675SRob Herring }; 122*724ba675SRob Herring 123*724ba675SRob Herring clkgem5: clkgem5@2350050 { 124*724ba675SRob Herring #clock-cells = <0>; 125*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 126*724ba675SRob Herring clocks = <&chipclk1>; 127*724ba675SRob Herring clock-output-names = "gem5"; 128*724ba675SRob Herring reg = <0x02350050 0xb00>, <0x02350034 0x400>; 129*724ba675SRob Herring reg-names = "control", "domain"; 130*724ba675SRob Herring domain-id = <13>; 131*724ba675SRob Herring }; 132*724ba675SRob Herring 133*724ba675SRob Herring clkgem6: clkgem6@2350054 { 134*724ba675SRob Herring #clock-cells = <0>; 135*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 136*724ba675SRob Herring clocks = <&chipclk1>; 137*724ba675SRob Herring clock-output-names = "gem6"; 138*724ba675SRob Herring reg = <0x02350054 0xb00>, <0x02350038 0x400>; 139*724ba675SRob Herring reg-names = "control", "domain"; 140*724ba675SRob Herring domain-id = <14>; 141*724ba675SRob Herring }; 142*724ba675SRob Herring 143*724ba675SRob Herring clkgem7: clkgem7@2350058 { 144*724ba675SRob Herring #clock-cells = <0>; 145*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 146*724ba675SRob Herring clocks = <&chipclk1>; 147*724ba675SRob Herring clock-output-names = "gem7"; 148*724ba675SRob Herring reg = <0x02350058 0xb00>, <0x0235003c 0x400>; 149*724ba675SRob Herring reg-names = "control", "domain"; 150*724ba675SRob Herring domain-id = <15>; 151*724ba675SRob Herring }; 152*724ba675SRob Herring 153*724ba675SRob Herring clkddr31: clkddr31@2350060 { 154*724ba675SRob Herring #clock-cells = <0>; 155*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 156*724ba675SRob Herring clocks = <&chipclk13>; 157*724ba675SRob Herring clock-output-names = "ddr3-1"; 158*724ba675SRob Herring reg = <0x02350060 0xb00>, <0x02350040 0x400>; 159*724ba675SRob Herring reg-names = "control", "domain"; 160*724ba675SRob Herring domain-id = <16>; 161*724ba675SRob Herring }; 162*724ba675SRob Herring 163*724ba675SRob Herring clktac: clktac@2350064 { 164*724ba675SRob Herring #clock-cells = <0>; 165*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 166*724ba675SRob Herring clocks = <&chipclk13>; 167*724ba675SRob Herring clock-output-names = "tac"; 168*724ba675SRob Herring reg = <0x02350064 0xb00>, <0x02350044 0x400>; 169*724ba675SRob Herring reg-names = "control", "domain"; 170*724ba675SRob Herring domain-id = <17>; 171*724ba675SRob Herring }; 172*724ba675SRob Herring 173*724ba675SRob Herring clkrac01: clkrac01@2350068 { 174*724ba675SRob Herring #clock-cells = <0>; 175*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 176*724ba675SRob Herring clocks = <&chipclk13>; 177*724ba675SRob Herring clock-output-names = "rac-01"; 178*724ba675SRob Herring reg = <0x02350068 0xb00>, <0x02350044 0x400>; 179*724ba675SRob Herring reg-names = "control", "domain"; 180*724ba675SRob Herring domain-id = <17>; 181*724ba675SRob Herring }; 182*724ba675SRob Herring 183*724ba675SRob Herring clkrac23: clkrac23@235006c { 184*724ba675SRob Herring #clock-cells = <0>; 185*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 186*724ba675SRob Herring clocks = <&chipclk13>; 187*724ba675SRob Herring clock-output-names = "rac-23"; 188*724ba675SRob Herring reg = <0x0235006c 0xb00>, <0x02350048 0x400>; 189*724ba675SRob Herring reg-names = "control", "domain"; 190*724ba675SRob Herring domain-id = <18>; 191*724ba675SRob Herring }; 192*724ba675SRob Herring 193*724ba675SRob Herring clkfftc0: clkfftc0@2350070 { 194*724ba675SRob Herring #clock-cells = <0>; 195*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 196*724ba675SRob Herring clocks = <&chipclk13>; 197*724ba675SRob Herring clock-output-names = "fftc-0"; 198*724ba675SRob Herring reg = <0x02350070 0xb00>, <0x0235004c 0x400>; 199*724ba675SRob Herring reg-names = "control", "domain"; 200*724ba675SRob Herring domain-id = <19>; 201*724ba675SRob Herring }; 202*724ba675SRob Herring 203*724ba675SRob Herring clkfftc1: clkfftc1@2350074 { 204*724ba675SRob Herring #clock-cells = <0>; 205*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 206*724ba675SRob Herring clocks = <&chipclk13>; 207*724ba675SRob Herring clock-output-names = "fftc-1"; 208*724ba675SRob Herring reg = <0x02350074 0xb00>, <0x0235004c 0x400>; 209*724ba675SRob Herring reg-names = "control", "domain"; 210*724ba675SRob Herring domain-id = <19>; 211*724ba675SRob Herring }; 212*724ba675SRob Herring 213*724ba675SRob Herring clkfftc2: clkfftc2@2350078 { 214*724ba675SRob Herring #clock-cells = <0>; 215*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 216*724ba675SRob Herring clocks = <&chipclk13>; 217*724ba675SRob Herring clock-output-names = "fftc-2"; 218*724ba675SRob Herring reg = <0x02350078 0xb00>, <0x02350050 0x400>; 219*724ba675SRob Herring reg-names = "control", "domain"; 220*724ba675SRob Herring domain-id = <20>; 221*724ba675SRob Herring }; 222*724ba675SRob Herring 223*724ba675SRob Herring clkfftc3: clkfftc3@235007c { 224*724ba675SRob Herring #clock-cells = <0>; 225*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 226*724ba675SRob Herring clocks = <&chipclk13>; 227*724ba675SRob Herring clock-output-names = "fftc-3"; 228*724ba675SRob Herring reg = <0x0235007c 0xb00>, <0x02350050 0x400>; 229*724ba675SRob Herring reg-names = "control", "domain"; 230*724ba675SRob Herring domain-id = <20>; 231*724ba675SRob Herring }; 232*724ba675SRob Herring 233*724ba675SRob Herring clkfftc4: clkfftc4@2350080 { 234*724ba675SRob Herring #clock-cells = <0>; 235*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 236*724ba675SRob Herring clocks = <&chipclk13>; 237*724ba675SRob Herring clock-output-names = "fftc-4"; 238*724ba675SRob Herring reg = <0x02350080 0xb00>, <0x02350050 0x400>; 239*724ba675SRob Herring reg-names = "control", "domain"; 240*724ba675SRob Herring domain-id = <20>; 241*724ba675SRob Herring }; 242*724ba675SRob Herring 243*724ba675SRob Herring clkfftc5: clkfftc5@2350084 { 244*724ba675SRob Herring #clock-cells = <0>; 245*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 246*724ba675SRob Herring clocks = <&chipclk13>; 247*724ba675SRob Herring clock-output-names = "fftc-5"; 248*724ba675SRob Herring reg = <0x02350084 0xb00>, <0x02350050 0x400>; 249*724ba675SRob Herring reg-names = "control", "domain"; 250*724ba675SRob Herring domain-id = <20>; 251*724ba675SRob Herring }; 252*724ba675SRob Herring 253*724ba675SRob Herring clkaif: clkaif@2350088 { 254*724ba675SRob Herring #clock-cells = <0>; 255*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 256*724ba675SRob Herring clocks = <&chipclk13>; 257*724ba675SRob Herring clock-output-names = "aif"; 258*724ba675SRob Herring reg = <0x02350088 0xb00>, <0x02350054 0x400>; 259*724ba675SRob Herring reg-names = "control", "domain"; 260*724ba675SRob Herring domain-id = <21>; 261*724ba675SRob Herring }; 262*724ba675SRob Herring 263*724ba675SRob Herring clktcp3d0: clktcp3d0@235008c { 264*724ba675SRob Herring #clock-cells = <0>; 265*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 266*724ba675SRob Herring clocks = <&chipclk13>; 267*724ba675SRob Herring clock-output-names = "tcp3d-0"; 268*724ba675SRob Herring reg = <0x0235008c 0xb00>, <0x02350058 0x400>; 269*724ba675SRob Herring reg-names = "control", "domain"; 270*724ba675SRob Herring domain-id = <22>; 271*724ba675SRob Herring }; 272*724ba675SRob Herring 273*724ba675SRob Herring clktcp3d1: clktcp3d1@2350090 { 274*724ba675SRob Herring #clock-cells = <0>; 275*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 276*724ba675SRob Herring clocks = <&chipclk13>; 277*724ba675SRob Herring clock-output-names = "tcp3d-1"; 278*724ba675SRob Herring reg = <0x02350090 0xb00>, <0x02350058 0x400>; 279*724ba675SRob Herring reg-names = "control", "domain"; 280*724ba675SRob Herring domain-id = <22>; 281*724ba675SRob Herring }; 282*724ba675SRob Herring 283*724ba675SRob Herring clktcp3d2: clktcp3d2@2350094 { 284*724ba675SRob Herring #clock-cells = <0>; 285*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 286*724ba675SRob Herring clocks = <&chipclk13>; 287*724ba675SRob Herring clock-output-names = "tcp3d-2"; 288*724ba675SRob Herring reg = <0x02350094 0xb00>, <0x0235005c 0x400>; 289*724ba675SRob Herring reg-names = "control", "domain"; 290*724ba675SRob Herring domain-id = <23>; 291*724ba675SRob Herring }; 292*724ba675SRob Herring 293*724ba675SRob Herring clktcp3d3: clktcp3d3@2350098 { 294*724ba675SRob Herring #clock-cells = <0>; 295*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 296*724ba675SRob Herring clocks = <&chipclk13>; 297*724ba675SRob Herring clock-output-names = "tcp3d-3"; 298*724ba675SRob Herring reg = <0x02350098 0xb00>, <0x0235005c 0x400>; 299*724ba675SRob Herring reg-names = "control", "domain"; 300*724ba675SRob Herring domain-id = <23>; 301*724ba675SRob Herring }; 302*724ba675SRob Herring 303*724ba675SRob Herring clkvcp0: clkvcp0@235009c { 304*724ba675SRob Herring #clock-cells = <0>; 305*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 306*724ba675SRob Herring clocks = <&chipclk13>; 307*724ba675SRob Herring clock-output-names = "vcp-0"; 308*724ba675SRob Herring reg = <0x0235009c 0xb00>, <0x02350060 0x400>; 309*724ba675SRob Herring reg-names = "control", "domain"; 310*724ba675SRob Herring domain-id = <24>; 311*724ba675SRob Herring }; 312*724ba675SRob Herring 313*724ba675SRob Herring clkvcp1: clkvcp1@23500a0 { 314*724ba675SRob Herring #clock-cells = <0>; 315*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 316*724ba675SRob Herring clocks = <&chipclk13>; 317*724ba675SRob Herring clock-output-names = "vcp-1"; 318*724ba675SRob Herring reg = <0x023500a0 0xb00>, <0x02350060 0x400>; 319*724ba675SRob Herring reg-names = "control", "domain"; 320*724ba675SRob Herring domain-id = <24>; 321*724ba675SRob Herring }; 322*724ba675SRob Herring 323*724ba675SRob Herring clkvcp2: clkvcp2@23500a4 { 324*724ba675SRob Herring #clock-cells = <0>; 325*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 326*724ba675SRob Herring clocks = <&chipclk13>; 327*724ba675SRob Herring clock-output-names = "vcp-2"; 328*724ba675SRob Herring reg = <0x023500a4 0xb00>, <0x02350060 0x400>; 329*724ba675SRob Herring reg-names = "control", "domain"; 330*724ba675SRob Herring domain-id = <24>; 331*724ba675SRob Herring }; 332*724ba675SRob Herring 333*724ba675SRob Herring clkvcp3: clkvcp3@23500a8 { 334*724ba675SRob Herring #clock-cells = <0>; 335*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 336*724ba675SRob Herring clocks = <&chipclk13>; 337*724ba675SRob Herring clock-output-names = "vcp-3"; 338*724ba675SRob Herring reg = <0x023500a8 0xb00>, <0x02350060 0x400>; 339*724ba675SRob Herring reg-names = "control", "domain"; 340*724ba675SRob Herring domain-id = <24>; 341*724ba675SRob Herring }; 342*724ba675SRob Herring 343*724ba675SRob Herring clkvcp4: clkvcp4@23500ac { 344*724ba675SRob Herring #clock-cells = <0>; 345*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 346*724ba675SRob Herring clocks = <&chipclk13>; 347*724ba675SRob Herring clock-output-names = "vcp-4"; 348*724ba675SRob Herring reg = <0x023500ac 0xb00>, <0x02350064 0x400>; 349*724ba675SRob Herring reg-names = "control", "domain"; 350*724ba675SRob Herring domain-id = <25>; 351*724ba675SRob Herring }; 352*724ba675SRob Herring 353*724ba675SRob Herring clkvcp5: clkvcp5@23500b0 { 354*724ba675SRob Herring #clock-cells = <0>; 355*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 356*724ba675SRob Herring clocks = <&chipclk13>; 357*724ba675SRob Herring clock-output-names = "vcp-5"; 358*724ba675SRob Herring reg = <0x023500b0 0xb00>, <0x02350064 0x400>; 359*724ba675SRob Herring reg-names = "control", "domain"; 360*724ba675SRob Herring domain-id = <25>; 361*724ba675SRob Herring }; 362*724ba675SRob Herring 363*724ba675SRob Herring clkvcp6: clkvcp6@23500b4 { 364*724ba675SRob Herring #clock-cells = <0>; 365*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 366*724ba675SRob Herring clocks = <&chipclk13>; 367*724ba675SRob Herring clock-output-names = "vcp-6"; 368*724ba675SRob Herring reg = <0x023500b4 0xb00>, <0x02350064 0x400>; 369*724ba675SRob Herring reg-names = "control", "domain"; 370*724ba675SRob Herring domain-id = <25>; 371*724ba675SRob Herring }; 372*724ba675SRob Herring 373*724ba675SRob Herring clkvcp7: clkvcp7@23500b8 { 374*724ba675SRob Herring #clock-cells = <0>; 375*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 376*724ba675SRob Herring clocks = <&chipclk13>; 377*724ba675SRob Herring clock-output-names = "vcp-7"; 378*724ba675SRob Herring reg = <0x023500b8 0xb00>, <0x02350064 0x400>; 379*724ba675SRob Herring reg-names = "control", "domain"; 380*724ba675SRob Herring domain-id = <25>; 381*724ba675SRob Herring }; 382*724ba675SRob Herring 383*724ba675SRob Herring clkbcp: clkbcp@23500bc { 384*724ba675SRob Herring #clock-cells = <0>; 385*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 386*724ba675SRob Herring clocks = <&chipclk13>; 387*724ba675SRob Herring clock-output-names = "bcp"; 388*724ba675SRob Herring reg = <0x023500bc 0xb00>, <0x02350068 0x400>; 389*724ba675SRob Herring reg-names = "control", "domain"; 390*724ba675SRob Herring domain-id = <26>; 391*724ba675SRob Herring }; 392*724ba675SRob Herring 393*724ba675SRob Herring clkdxb: clkdxb@23500c0 { 394*724ba675SRob Herring #clock-cells = <0>; 395*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 396*724ba675SRob Herring clocks = <&chipclk13>; 397*724ba675SRob Herring clock-output-names = "dxb"; 398*724ba675SRob Herring reg = <0x023500c0 0xb00>, <0x0235006c 0x400>; 399*724ba675SRob Herring reg-names = "control", "domain"; 400*724ba675SRob Herring domain-id = <27>; 401*724ba675SRob Herring }; 402*724ba675SRob Herring 403*724ba675SRob Herring clkhyperlink1: clkhyperlink1@23500c4 { 404*724ba675SRob Herring #clock-cells = <0>; 405*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 406*724ba675SRob Herring clocks = <&chipclk12>; 407*724ba675SRob Herring clock-output-names = "hyperlink-1"; 408*724ba675SRob Herring reg = <0x023500c4 0xb00>, <0x02350070 0x400>; 409*724ba675SRob Herring reg-names = "control", "domain"; 410*724ba675SRob Herring domain-id = <28>; 411*724ba675SRob Herring }; 412*724ba675SRob Herring 413*724ba675SRob Herring clkxge: clkxge@23500c8 { 414*724ba675SRob Herring #clock-cells = <0>; 415*724ba675SRob Herring compatible = "ti,keystone,psc-clock"; 416*724ba675SRob Herring clocks = <&chipclk13>; 417*724ba675SRob Herring clock-output-names = "xge"; 418*724ba675SRob Herring reg = <0x023500c8 0xb00>, <0x02350074 0x400>; 419*724ba675SRob Herring reg-names = "control", "domain"; 420*724ba675SRob Herring domain-id = <29>; 421*724ba675SRob Herring }; 422*724ba675SRob Herring}; 423