1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0
2*724ba675SRob Herring/*
3*724ba675SRob Herring * Keystone 2 Edison SoC specific device tree
4*724ba675SRob Herring *
5*724ba675SRob Herring * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
6*724ba675SRob Herring */
7*724ba675SRob Herring
8*724ba675SRob Herringclocks {
9*724ba675SRob Herring	mainpllclk: mainpllclk@2310110 {
10*724ba675SRob Herring		#clock-cells = <0>;
11*724ba675SRob Herring		compatible = "ti,keystone,main-pll-clock";
12*724ba675SRob Herring		clocks = <&refclksys>;
13*724ba675SRob Herring		reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
14*724ba675SRob Herring		reg-names = "control", "multiplier", "post-divider";
15*724ba675SRob Herring	};
16*724ba675SRob Herring
17*724ba675SRob Herring	papllclk: papllclk@2620358 {
18*724ba675SRob Herring		#clock-cells = <0>;
19*724ba675SRob Herring		compatible = "ti,keystone,pll-clock";
20*724ba675SRob Herring		clocks = <&refclkpass>;
21*724ba675SRob Herring		clock-output-names = "papllclk";
22*724ba675SRob Herring		reg = <0x02620358 4>;
23*724ba675SRob Herring		reg-names = "control";
24*724ba675SRob Herring	};
25*724ba675SRob Herring
26*724ba675SRob Herring	ddr3apllclk: ddr3apllclk@2620360 {
27*724ba675SRob Herring		#clock-cells = <0>;
28*724ba675SRob Herring		compatible = "ti,keystone,pll-clock";
29*724ba675SRob Herring		clocks = <&refclkddr3a>;
30*724ba675SRob Herring		clock-output-names = "ddr-3a-pll-clk";
31*724ba675SRob Herring		reg = <0x02620360 4>;
32*724ba675SRob Herring		reg-names = "control";
33*724ba675SRob Herring	};
34*724ba675SRob Herring
35*724ba675SRob Herring	clkusb1: clkusb1@2350004 {
36*724ba675SRob Herring		#clock-cells = <0>;
37*724ba675SRob Herring		compatible = "ti,keystone,psc-clock";
38*724ba675SRob Herring		clocks = <&chipclk16>;
39*724ba675SRob Herring		clock-output-names = "usb1";
40*724ba675SRob Herring		reg = <0x02350004 0xb00>, <0x02350000 0x400>;
41*724ba675SRob Herring		reg-names = "control", "domain";
42*724ba675SRob Herring		domain-id = <0>;
43*724ba675SRob Herring	};
44*724ba675SRob Herring
45*724ba675SRob Herring	clkhyperlink0: clkhyperlink0@2350030 {
46*724ba675SRob Herring		#clock-cells = <0>;
47*724ba675SRob Herring		compatible = "ti,keystone,psc-clock";
48*724ba675SRob Herring		clocks = <&chipclk12>;
49*724ba675SRob Herring		clock-output-names = "hyperlink-0";
50*724ba675SRob Herring		reg = <0x02350030 0xb00>, <0x02350014 0x400>;
51*724ba675SRob Herring		reg-names = "control", "domain";
52*724ba675SRob Herring		domain-id = <5>;
53*724ba675SRob Herring	};
54*724ba675SRob Herring
55*724ba675SRob Herring	clkpcie1: clkpcie1@235006c {
56*724ba675SRob Herring		#clock-cells = <0>;
57*724ba675SRob Herring		compatible = "ti,keystone,psc-clock";
58*724ba675SRob Herring		clocks = <&chipclk12>;
59*724ba675SRob Herring		clock-output-names = "pcie1";
60*724ba675SRob Herring		reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
61*724ba675SRob Herring		reg-names = "control", "domain";
62*724ba675SRob Herring		domain-id = <18>;
63*724ba675SRob Herring	};
64*724ba675SRob Herring
65*724ba675SRob Herring	clkxge: clkxge@23500c8 {
66*724ba675SRob Herring		#clock-cells = <0>;
67*724ba675SRob Herring		compatible = "ti,keystone,psc-clock";
68*724ba675SRob Herring		clocks = <&chipclk13>;
69*724ba675SRob Herring		clock-output-names = "xge";
70*724ba675SRob Herring		reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
71*724ba675SRob Herring		reg-names = "control", "domain";
72*724ba675SRob Herring		domain-id = <29>;
73*724ba675SRob Herring	};
74*724ba675SRob Herring
75*724ba675SRob Herring	/*
76*724ba675SRob Herring	 * Below are set of fixed, input clocks definitions,
77*724ba675SRob Herring	 * for which real frequencies have to be defined in board files.
78*724ba675SRob Herring	 * Those clocks can be used as reference clocks for some HW modules
79*724ba675SRob Herring	 * (as cpts, for example) by configuring corresponding clock muxes.
80*724ba675SRob Herring	 */
81*724ba675SRob Herring	tsipclka: tsipclka {
82*724ba675SRob Herring		#clock-cells = <0>;
83*724ba675SRob Herring		compatible = "fixed-clock";
84*724ba675SRob Herring		clock-frequency = <0>;
85*724ba675SRob Herring		clock-output-names = "tsipclka";
86*724ba675SRob Herring	};
87*724ba675SRob Herring
88*724ba675SRob Herring	tsipclkb: tsipclkb {
89*724ba675SRob Herring		#clock-cells = <0>;
90*724ba675SRob Herring		compatible = "fixed-clock";
91*724ba675SRob Herring		clock-frequency = <0>;
92*724ba675SRob Herring		clock-output-names = "tsipclkb";
93*724ba675SRob Herring	};
94*724ba675SRob Herring};
95