1*351f9690SLokesh Vutla/*
2*351f9690SLokesh Vutla * Device Tree Source for Keystone 2 clock tree
3*351f9690SLokesh Vutla *
4*351f9690SLokesh Vutla * Copyright (C) 2013 Texas Instruments, Inc.
5*351f9690SLokesh Vutla *
6*351f9690SLokesh Vutla * This program is free software; you can redistribute it and/or modify
7*351f9690SLokesh Vutla * it under the terms of the GNU General Public License version 2 as
8*351f9690SLokesh Vutla * published by the Free Software Foundation.
9*351f9690SLokesh Vutla */
10*351f9690SLokesh Vutla
11*351f9690SLokesh Vutlaclocks {
12*351f9690SLokesh Vutla	#address-cells = <1>;
13*351f9690SLokesh Vutla	#size-cells = <1>;
14*351f9690SLokesh Vutla	ranges;
15*351f9690SLokesh Vutla
16*351f9690SLokesh Vutla	mainmuxclk: mainmuxclk@2310108 {
17*351f9690SLokesh Vutla		#clock-cells = <0>;
18*351f9690SLokesh Vutla		compatible = "ti,keystone,pll-mux-clock";
19*351f9690SLokesh Vutla		clocks = <&mainpllclk>, <&refclksys>;
20*351f9690SLokesh Vutla		reg = <0x02310108 4>;
21*351f9690SLokesh Vutla		bit-shift = <23>;
22*351f9690SLokesh Vutla		bit-mask = <1>;
23*351f9690SLokesh Vutla		clock-output-names = "mainmuxclk";
24*351f9690SLokesh Vutla	};
25*351f9690SLokesh Vutla
26*351f9690SLokesh Vutla	chipclk1: chipclk1 {
27*351f9690SLokesh Vutla		#clock-cells = <0>;
28*351f9690SLokesh Vutla		compatible = "fixed-factor-clock";
29*351f9690SLokesh Vutla		clocks = <&mainmuxclk>;
30*351f9690SLokesh Vutla		clock-div = <1>;
31*351f9690SLokesh Vutla		clock-mult = <1>;
32*351f9690SLokesh Vutla		clock-output-names = "chipclk1";
33*351f9690SLokesh Vutla	};
34*351f9690SLokesh Vutla
35*351f9690SLokesh Vutla	chipclk1rstiso: chipclk1rstiso {
36*351f9690SLokesh Vutla		#clock-cells = <0>;
37*351f9690SLokesh Vutla		compatible = "fixed-factor-clock";
38*351f9690SLokesh Vutla		clocks = <&mainmuxclk>;
39*351f9690SLokesh Vutla		clock-div = <1>;
40*351f9690SLokesh Vutla		clock-mult = <1>;
41*351f9690SLokesh Vutla		clock-output-names = "chipclk1rstiso";
42*351f9690SLokesh Vutla	};
43*351f9690SLokesh Vutla
44*351f9690SLokesh Vutla	gemtraceclk: gemtraceclk@2310120 {
45*351f9690SLokesh Vutla		#clock-cells = <0>;
46*351f9690SLokesh Vutla		compatible = "ti,keystone,pll-divider-clock";
47*351f9690SLokesh Vutla		clocks = <&mainmuxclk>;
48*351f9690SLokesh Vutla		reg = <0x02310120 4>;
49*351f9690SLokesh Vutla		bit-shift = <0>;
50*351f9690SLokesh Vutla		bit-mask = <8>;
51*351f9690SLokesh Vutla		clock-output-names = "gemtraceclk";
52*351f9690SLokesh Vutla	};
53*351f9690SLokesh Vutla
54*351f9690SLokesh Vutla	chipstmxptclk: chipstmxptclk {
55*351f9690SLokesh Vutla		#clock-cells = <0>;
56*351f9690SLokesh Vutla		compatible = "ti,keystone,pll-divider-clock";
57*351f9690SLokesh Vutla		clocks = <&mainmuxclk>;
58*351f9690SLokesh Vutla		reg = <0x02310164 4>;
59*351f9690SLokesh Vutla		bit-shift = <0>;
60*351f9690SLokesh Vutla		bit-mask = <8>;
61*351f9690SLokesh Vutla		clock-output-names = "chipstmxptclk";
62*351f9690SLokesh Vutla	};
63*351f9690SLokesh Vutla
64*351f9690SLokesh Vutla	chipclk12: chipclk12 {
65*351f9690SLokesh Vutla		#clock-cells = <0>;
66*351f9690SLokesh Vutla		compatible = "fixed-factor-clock";
67*351f9690SLokesh Vutla		clocks = <&chipclk1>;
68*351f9690SLokesh Vutla		clock-div = <2>;
69*351f9690SLokesh Vutla		clock-mult = <1>;
70*351f9690SLokesh Vutla		clock-output-names = "chipclk12";
71*351f9690SLokesh Vutla	};
72*351f9690SLokesh Vutla
73*351f9690SLokesh Vutla	chipclk13: chipclk13 {
74*351f9690SLokesh Vutla		#clock-cells = <0>;
75*351f9690SLokesh Vutla		compatible = "fixed-factor-clock";
76*351f9690SLokesh Vutla		clocks = <&chipclk1>;
77*351f9690SLokesh Vutla		clock-div = <3>;
78*351f9690SLokesh Vutla		clock-mult = <1>;
79*351f9690SLokesh Vutla		clock-output-names = "chipclk13";
80*351f9690SLokesh Vutla	};
81*351f9690SLokesh Vutla
82*351f9690SLokesh Vutla	paclk13: paclk13 {
83*351f9690SLokesh Vutla		#clock-cells = <0>;
84*351f9690SLokesh Vutla		compatible = "fixed-factor-clock";
85*351f9690SLokesh Vutla		clocks = <&papllclk>;
86*351f9690SLokesh Vutla		clock-div = <3>;
87*351f9690SLokesh Vutla		clock-mult = <1>;
88*351f9690SLokesh Vutla		clock-output-names = "paclk13";
89*351f9690SLokesh Vutla	};
90*351f9690SLokesh Vutla
91*351f9690SLokesh Vutla	chipclk14: chipclk14 {
92*351f9690SLokesh Vutla		#clock-cells = <0>;
93*351f9690SLokesh Vutla		compatible = "fixed-factor-clock";
94*351f9690SLokesh Vutla		clocks = <&chipclk1>;
95*351f9690SLokesh Vutla		clock-div = <4>;
96*351f9690SLokesh Vutla		clock-mult = <1>;
97*351f9690SLokesh Vutla		clock-output-names = "chipclk14";
98*351f9690SLokesh Vutla	};
99*351f9690SLokesh Vutla
100*351f9690SLokesh Vutla	chipclk16: chipclk16 {
101*351f9690SLokesh Vutla		#clock-cells = <0>;
102*351f9690SLokesh Vutla		compatible = "fixed-factor-clock";
103*351f9690SLokesh Vutla		clocks = <&chipclk1>;
104*351f9690SLokesh Vutla		clock-div = <6>;
105*351f9690SLokesh Vutla		clock-mult = <1>;
106*351f9690SLokesh Vutla		clock-output-names = "chipclk16";
107*351f9690SLokesh Vutla	};
108*351f9690SLokesh Vutla
109*351f9690SLokesh Vutla	chipclk112: chipclk112 {
110*351f9690SLokesh Vutla		#clock-cells = <0>;
111*351f9690SLokesh Vutla		compatible = "fixed-factor-clock";
112*351f9690SLokesh Vutla		clocks = <&chipclk1>;
113*351f9690SLokesh Vutla		clock-div = <12>;
114*351f9690SLokesh Vutla		clock-mult = <1>;
115*351f9690SLokesh Vutla		clock-output-names = "chipclk112";
116*351f9690SLokesh Vutla	};
117*351f9690SLokesh Vutla
118*351f9690SLokesh Vutla	chipclk124: chipclk124 {
119*351f9690SLokesh Vutla		#clock-cells = <0>;
120*351f9690SLokesh Vutla		compatible = "fixed-factor-clock";
121*351f9690SLokesh Vutla		clocks = <&chipclk1>;
122*351f9690SLokesh Vutla		clock-div = <24>;
123*351f9690SLokesh Vutla		clock-mult = <1>;
124*351f9690SLokesh Vutla		clock-output-names = "chipclk114";
125*351f9690SLokesh Vutla	};
126*351f9690SLokesh Vutla
127*351f9690SLokesh Vutla	chipclk1rstiso13: chipclk1rstiso13 {
128*351f9690SLokesh Vutla		#clock-cells = <0>;
129*351f9690SLokesh Vutla		compatible = "fixed-factor-clock";
130*351f9690SLokesh Vutla		clocks = <&chipclk1rstiso>;
131*351f9690SLokesh Vutla		clock-div = <3>;
132*351f9690SLokesh Vutla		clock-mult = <1>;
133*351f9690SLokesh Vutla		clock-output-names = "chipclk1rstiso13";
134*351f9690SLokesh Vutla	};
135*351f9690SLokesh Vutla
136*351f9690SLokesh Vutla	chipclk1rstiso14: chipclk1rstiso14 {
137*351f9690SLokesh Vutla		#clock-cells = <0>;
138*351f9690SLokesh Vutla		compatible = "fixed-factor-clock";
139*351f9690SLokesh Vutla		clocks = <&chipclk1rstiso>;
140*351f9690SLokesh Vutla		clock-div = <4>;
141*351f9690SLokesh Vutla		clock-mult = <1>;
142*351f9690SLokesh Vutla		clock-output-names = "chipclk1rstiso14";
143*351f9690SLokesh Vutla	};
144*351f9690SLokesh Vutla
145*351f9690SLokesh Vutla	chipclk1rstiso16: chipclk1rstiso16 {
146*351f9690SLokesh Vutla		#clock-cells = <0>;
147*351f9690SLokesh Vutla		compatible = "fixed-factor-clock";
148*351f9690SLokesh Vutla		clocks = <&chipclk1rstiso>;
149*351f9690SLokesh Vutla		clock-div = <6>;
150*351f9690SLokesh Vutla		clock-mult = <1>;
151*351f9690SLokesh Vutla		clock-output-names = "chipclk1rstiso16";
152*351f9690SLokesh Vutla	};
153*351f9690SLokesh Vutla
154*351f9690SLokesh Vutla	chipclk1rstiso112: chipclk1rstiso112 {
155*351f9690SLokesh Vutla		#clock-cells = <0>;
156*351f9690SLokesh Vutla		compatible = "fixed-factor-clock";
157*351f9690SLokesh Vutla		clocks = <&chipclk1rstiso>;
158*351f9690SLokesh Vutla		clock-div = <12>;
159*351f9690SLokesh Vutla		clock-mult = <1>;
160*351f9690SLokesh Vutla		clock-output-names = "chipclk1rstiso112";
161*351f9690SLokesh Vutla	};
162*351f9690SLokesh Vutla
163*351f9690SLokesh Vutla	clkmodrst0: clkmodrst0 {
164*351f9690SLokesh Vutla		#clock-cells = <0>;
165*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
166*351f9690SLokesh Vutla		clocks = <&chipclk16>;
167*351f9690SLokesh Vutla		clock-output-names = "modrst0";
168*351f9690SLokesh Vutla		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
169*351f9690SLokesh Vutla		reg-names = "control", "domain";
170*351f9690SLokesh Vutla		domain-id = <0>;
171*351f9690SLokesh Vutla	};
172*351f9690SLokesh Vutla
173*351f9690SLokesh Vutla
174*351f9690SLokesh Vutla	clkusb: clkusb {
175*351f9690SLokesh Vutla		#clock-cells = <0>;
176*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
177*351f9690SLokesh Vutla		clocks = <&chipclk16>;
178*351f9690SLokesh Vutla		clock-output-names = "usb";
179*351f9690SLokesh Vutla		reg = <0x02350008 0xb00>, <0x02350000 0x400>;
180*351f9690SLokesh Vutla		reg-names = "control", "domain";
181*351f9690SLokesh Vutla		domain-id = <0>;
182*351f9690SLokesh Vutla	};
183*351f9690SLokesh Vutla
184*351f9690SLokesh Vutla	clkaemifspi: clkaemifspi {
185*351f9690SLokesh Vutla		#clock-cells = <0>;
186*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
187*351f9690SLokesh Vutla		clocks = <&chipclk16>;
188*351f9690SLokesh Vutla		clock-output-names = "aemif-spi";
189*351f9690SLokesh Vutla		reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
190*351f9690SLokesh Vutla		reg-names = "control", "domain";
191*351f9690SLokesh Vutla		domain-id = <0>;
192*351f9690SLokesh Vutla	};
193*351f9690SLokesh Vutla
194*351f9690SLokesh Vutla
195*351f9690SLokesh Vutla	clkdebugsstrc: clkdebugsstrc {
196*351f9690SLokesh Vutla		#clock-cells = <0>;
197*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
198*351f9690SLokesh Vutla		clocks = <&chipclk13>;
199*351f9690SLokesh Vutla		clock-output-names = "debugss-trc";
200*351f9690SLokesh Vutla		reg = <0x02350014 0xb00>, <0x02350000 0x400>;
201*351f9690SLokesh Vutla		reg-names = "control", "domain";
202*351f9690SLokesh Vutla		domain-id = <1>;
203*351f9690SLokesh Vutla	};
204*351f9690SLokesh Vutla
205*351f9690SLokesh Vutla	clktetbtrc: clktetbtrc {
206*351f9690SLokesh Vutla		#clock-cells = <0>;
207*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
208*351f9690SLokesh Vutla		clocks = <&chipclk13>;
209*351f9690SLokesh Vutla		clock-output-names = "tetb-trc";
210*351f9690SLokesh Vutla		reg = <0x02350018 0xb00>, <0x02350004 0x400>;
211*351f9690SLokesh Vutla		reg-names = "control", "domain";
212*351f9690SLokesh Vutla		domain-id = <1>;
213*351f9690SLokesh Vutla	};
214*351f9690SLokesh Vutla
215*351f9690SLokesh Vutla	clkpa: clkpa {
216*351f9690SLokesh Vutla		#clock-cells = <0>;
217*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
218*351f9690SLokesh Vutla		clocks = <&paclk13>;
219*351f9690SLokesh Vutla		clock-output-names = "pa";
220*351f9690SLokesh Vutla		reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
221*351f9690SLokesh Vutla		reg-names = "control", "domain";
222*351f9690SLokesh Vutla		domain-id = <2>;
223*351f9690SLokesh Vutla	};
224*351f9690SLokesh Vutla
225*351f9690SLokesh Vutla	clkcpgmac: clkcpgmac {
226*351f9690SLokesh Vutla		#clock-cells = <0>;
227*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
228*351f9690SLokesh Vutla		clocks = <&clkpa>;
229*351f9690SLokesh Vutla		clock-output-names = "cpgmac";
230*351f9690SLokesh Vutla		reg = <0x02350020 0xb00>, <0x02350008 0x400>;
231*351f9690SLokesh Vutla		reg-names = "control", "domain";
232*351f9690SLokesh Vutla		domain-id = <2>;
233*351f9690SLokesh Vutla	};
234*351f9690SLokesh Vutla
235*351f9690SLokesh Vutla	clksa: clksa {
236*351f9690SLokesh Vutla		#clock-cells = <0>;
237*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
238*351f9690SLokesh Vutla		clocks = <&clkpa>;
239*351f9690SLokesh Vutla		clock-output-names = "sa";
240*351f9690SLokesh Vutla		reg = <0x02350024 0xb00>, <0x02350008 0x400>;
241*351f9690SLokesh Vutla		reg-names = "control", "domain";
242*351f9690SLokesh Vutla		domain-id = <2>;
243*351f9690SLokesh Vutla	};
244*351f9690SLokesh Vutla
245*351f9690SLokesh Vutla	clkpcie: clkpcie {
246*351f9690SLokesh Vutla		#clock-cells = <0>;
247*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
248*351f9690SLokesh Vutla		clocks = <&chipclk12>;
249*351f9690SLokesh Vutla		clock-output-names = "pcie";
250*351f9690SLokesh Vutla		reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
251*351f9690SLokesh Vutla		reg-names = "control", "domain";
252*351f9690SLokesh Vutla		domain-id = <3>;
253*351f9690SLokesh Vutla	};
254*351f9690SLokesh Vutla
255*351f9690SLokesh Vutla	clksr: clksr {
256*351f9690SLokesh Vutla		#clock-cells = <0>;
257*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
258*351f9690SLokesh Vutla		clocks = <&chipclk1rstiso112>;
259*351f9690SLokesh Vutla		clock-output-names = "sr";
260*351f9690SLokesh Vutla		reg = <0x02350034 0xb00>, <0x02350018 0x400>;
261*351f9690SLokesh Vutla		reg-names = "control", "domain";
262*351f9690SLokesh Vutla		domain-id = <6>;
263*351f9690SLokesh Vutla	};
264*351f9690SLokesh Vutla
265*351f9690SLokesh Vutla	clkgem0: clkgem0 {
266*351f9690SLokesh Vutla		#clock-cells = <0>;
267*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
268*351f9690SLokesh Vutla		clocks = <&chipclk1>;
269*351f9690SLokesh Vutla		clock-output-names = "gem0";
270*351f9690SLokesh Vutla		reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
271*351f9690SLokesh Vutla		reg-names = "control", "domain";
272*351f9690SLokesh Vutla		domain-id = <8>;
273*351f9690SLokesh Vutla	};
274*351f9690SLokesh Vutla
275*351f9690SLokesh Vutla	clkddr30: clkddr30 {
276*351f9690SLokesh Vutla		#clock-cells = <0>;
277*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
278*351f9690SLokesh Vutla		clocks = <&chipclk12>;
279*351f9690SLokesh Vutla		clock-output-names = "ddr3-0";
280*351f9690SLokesh Vutla		reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
281*351f9690SLokesh Vutla		reg-names = "control", "domain";
282*351f9690SLokesh Vutla		domain-id = <16>;
283*351f9690SLokesh Vutla	};
284*351f9690SLokesh Vutla
285*351f9690SLokesh Vutla	clkwdtimer0: clkwdtimer0 {
286*351f9690SLokesh Vutla		#clock-cells = <0>;
287*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
288*351f9690SLokesh Vutla		clocks = <&clkmodrst0>;
289*351f9690SLokesh Vutla		clock-output-names = "timer0";
290*351f9690SLokesh Vutla		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
291*351f9690SLokesh Vutla		reg-names = "control", "domain";
292*351f9690SLokesh Vutla		domain-id = <0>;
293*351f9690SLokesh Vutla	};
294*351f9690SLokesh Vutla
295*351f9690SLokesh Vutla	clkwdtimer1: clkwdtimer1 {
296*351f9690SLokesh Vutla		#clock-cells = <0>;
297*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
298*351f9690SLokesh Vutla		clocks = <&clkmodrst0>;
299*351f9690SLokesh Vutla		clock-output-names = "timer1";
300*351f9690SLokesh Vutla		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
301*351f9690SLokesh Vutla		reg-names = "control", "domain";
302*351f9690SLokesh Vutla		domain-id = <0>;
303*351f9690SLokesh Vutla	};
304*351f9690SLokesh Vutla
305*351f9690SLokesh Vutla	clkwdtimer2: clkwdtimer2 {
306*351f9690SLokesh Vutla		#clock-cells = <0>;
307*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
308*351f9690SLokesh Vutla		clocks = <&clkmodrst0>;
309*351f9690SLokesh Vutla		clock-output-names = "timer2";
310*351f9690SLokesh Vutla		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
311*351f9690SLokesh Vutla		reg-names = "control", "domain";
312*351f9690SLokesh Vutla		domain-id = <0>;
313*351f9690SLokesh Vutla	};
314*351f9690SLokesh Vutla
315*351f9690SLokesh Vutla	clkwdtimer3: clkwdtimer3 {
316*351f9690SLokesh Vutla		#clock-cells = <0>;
317*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
318*351f9690SLokesh Vutla		clocks = <&clkmodrst0>;
319*351f9690SLokesh Vutla		clock-output-names = "timer3";
320*351f9690SLokesh Vutla		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
321*351f9690SLokesh Vutla		reg-names = "control", "domain";
322*351f9690SLokesh Vutla		domain-id = <0>;
323*351f9690SLokesh Vutla	};
324*351f9690SLokesh Vutla
325*351f9690SLokesh Vutla	clktimer15: clktimer15 {
326*351f9690SLokesh Vutla		#clock-cells = <0>;
327*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
328*351f9690SLokesh Vutla		clocks = <&clkmodrst0>;
329*351f9690SLokesh Vutla		clock-output-names = "timer15";
330*351f9690SLokesh Vutla		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
331*351f9690SLokesh Vutla		reg-names = "control", "domain";
332*351f9690SLokesh Vutla		domain-id = <0>;
333*351f9690SLokesh Vutla	};
334*351f9690SLokesh Vutla
335*351f9690SLokesh Vutla	clkuart0: clkuart0 {
336*351f9690SLokesh Vutla		#clock-cells = <0>;
337*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
338*351f9690SLokesh Vutla		clocks = <&clkmodrst0>;
339*351f9690SLokesh Vutla		clock-output-names = "uart0";
340*351f9690SLokesh Vutla		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
341*351f9690SLokesh Vutla		reg-names = "control", "domain";
342*351f9690SLokesh Vutla		domain-id = <0>;
343*351f9690SLokesh Vutla	};
344*351f9690SLokesh Vutla
345*351f9690SLokesh Vutla	clkuart1: clkuart1 {
346*351f9690SLokesh Vutla		#clock-cells = <0>;
347*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
348*351f9690SLokesh Vutla		clocks = <&clkmodrst0>;
349*351f9690SLokesh Vutla		clock-output-names = "uart1";
350*351f9690SLokesh Vutla		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
351*351f9690SLokesh Vutla		reg-names = "control", "domain";
352*351f9690SLokesh Vutla		domain-id = <0>;
353*351f9690SLokesh Vutla	};
354*351f9690SLokesh Vutla
355*351f9690SLokesh Vutla	clkaemif: clkaemif {
356*351f9690SLokesh Vutla		#clock-cells = <0>;
357*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
358*351f9690SLokesh Vutla		clocks = <&clkaemifspi>;
359*351f9690SLokesh Vutla		clock-output-names = "aemif";
360*351f9690SLokesh Vutla		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
361*351f9690SLokesh Vutla		reg-names = "control", "domain";
362*351f9690SLokesh Vutla		domain-id = <0>;
363*351f9690SLokesh Vutla	};
364*351f9690SLokesh Vutla
365*351f9690SLokesh Vutla	clkusim: clkusim {
366*351f9690SLokesh Vutla		#clock-cells = <0>;
367*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
368*351f9690SLokesh Vutla		clocks = <&clkmodrst0>;
369*351f9690SLokesh Vutla		clock-output-names = "usim";
370*351f9690SLokesh Vutla		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
371*351f9690SLokesh Vutla		reg-names = "control", "domain";
372*351f9690SLokesh Vutla		domain-id = <0>;
373*351f9690SLokesh Vutla	};
374*351f9690SLokesh Vutla
375*351f9690SLokesh Vutla	clki2c: clki2c {
376*351f9690SLokesh Vutla		#clock-cells = <0>;
377*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
378*351f9690SLokesh Vutla		clocks = <&clkmodrst0>;
379*351f9690SLokesh Vutla		clock-output-names = "i2c";
380*351f9690SLokesh Vutla		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
381*351f9690SLokesh Vutla		reg-names = "control", "domain";
382*351f9690SLokesh Vutla		domain-id = <0>;
383*351f9690SLokesh Vutla	};
384*351f9690SLokesh Vutla
385*351f9690SLokesh Vutla	clkspi: clkspi {
386*351f9690SLokesh Vutla		#clock-cells = <0>;
387*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
388*351f9690SLokesh Vutla		clocks = <&clkaemifspi>;
389*351f9690SLokesh Vutla		clock-output-names = "spi";
390*351f9690SLokesh Vutla		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
391*351f9690SLokesh Vutla		reg-names = "control", "domain";
392*351f9690SLokesh Vutla		domain-id = <0>;
393*351f9690SLokesh Vutla	};
394*351f9690SLokesh Vutla
395*351f9690SLokesh Vutla	clkgpio: clkgpio {
396*351f9690SLokesh Vutla		#clock-cells = <0>;
397*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
398*351f9690SLokesh Vutla		clocks = <&clkmodrst0>;
399*351f9690SLokesh Vutla		clock-output-names = "gpio";
400*351f9690SLokesh Vutla		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
401*351f9690SLokesh Vutla		reg-names = "control", "domain";
402*351f9690SLokesh Vutla		domain-id = <0>;
403*351f9690SLokesh Vutla	};
404*351f9690SLokesh Vutla
405*351f9690SLokesh Vutla	clkkeymgr: clkkeymgr {
406*351f9690SLokesh Vutla		#clock-cells = <0>;
407*351f9690SLokesh Vutla		compatible = "ti,keystone,psc-clock";
408*351f9690SLokesh Vutla		clocks = <&clkmodrst0>;
409*351f9690SLokesh Vutla		clock-output-names = "keymgr";
410*351f9690SLokesh Vutla		reg = <0x02350000 0xb00>, <0x02350000 0x400>;
411*351f9690SLokesh Vutla		reg-names = "control", "domain";
412*351f9690SLokesh Vutla		domain-id = <0>;
413*351f9690SLokesh Vutla	};
414*351f9690SLokesh Vutla};
415