| /openbmc/linux/arch/alpha/lib/ |
| H A D | fpreg.c | 14 #define STT(reg,val) asm volatile ("ftoit $f"#reg",%0" : "=r"(val)); argument
16 #define STT(reg,val) asm volatile ("stt $f"#reg",%0" : "=m"(val)); argument
22 unsigned long val; in alpha_read_fp_reg() local
28 val = current_thread_info()->fp[reg]; in alpha_read_fp_reg()
30 case 0: STT( 0, val); break; in alpha_read_fp_reg()
31 case 1: STT( 1, val); break; in alpha_read_fp_reg()
32 case 2: STT( 2, val); break; in alpha_read_fp_reg()
33 case 3: STT( 3, val); break; in alpha_read_fp_reg()
34 case 4: STT( 4, val); break; in alpha_read_fp_reg()
35 case 5: STT( 5, val); break; in alpha_read_fp_reg()
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| /openbmc/linux/arch/arm/include/asm/hardware/ |
| H A D | cp14.h | 12 #define dbg_write(val, reg) WCP14_##reg(val) argument
14 #define etm_write(val, reg) WCP14_##reg(val) argument
19 u32 val; \
20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
21 val; \
24 #define MCR14(val, op1, crn, crm, op2) \ argument
26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
152 #define WCP14_DBGDTRTXint(val) MCR14(val, 0, c0, c5, 0) argument
153 #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0) argument
154 #define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0) argument
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| /openbmc/linux/drivers/hwtracing/coresight/ |
| H A D | coresight-etm-cp14.c | 15 int etm_readl_cp14(u32 reg, unsigned int *val) in etm_readl_cp14() argument
19 *val = etm_read(ETMCR); in etm_readl_cp14()
22 *val = etm_read(ETMCCR); in etm_readl_cp14()
25 *val = etm_read(ETMTRIGGER); in etm_readl_cp14()
28 *val = etm_read(ETMSR); in etm_readl_cp14()
31 *val = etm_read(ETMSCR); in etm_readl_cp14()
34 *val = etm_read(ETMTSSCR); in etm_readl_cp14()
37 *val = etm_read(ETMTEEVR); in etm_readl_cp14()
40 *val = etm_read(ETMTECR1); in etm_readl_cp14()
43 *val = etm_read(ETMFFLR); in etm_readl_cp14()
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| /openbmc/u-boot/include/bedbug/ |
| H A D | regs.h | 169 #define SET_REGISTER( str, val ) \ argument
170 ({ unsigned long __value = (val); \
180 #define SET_CR(val) SET_REGISTER( "mtcr %0", val ) argument
182 #define SET_MSR(val) SET_REGISTER( "mtmsr %0", val ) argument
184 #define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val ) argument
186 #define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val ) argument
188 #define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val ) argument
190 #define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val ) argument
192 #define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val ) argument
194 #define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val ) argument
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| /openbmc/linux/drivers/media/tuners/ |
| H A D | tda18271-maps.c | 19 u8 val; member
190 { .rfmax = 62000, .val = 0x00 },
191 { .rfmax = 84000, .val = 0x01 },
192 { .rfmax = 100000, .val = 0x02 },
193 { .rfmax = 140000, .val = 0x03 },
194 { .rfmax = 170000, .val = 0x04 },
195 { .rfmax = 180000, .val = 0x05 },
196 { .rfmax = 865000, .val = 0x06 },
197 { .rfmax = 0, .val = 0x00 }, /* end */
201 { .rfmax = 61100, .val = 0x74 },
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| /openbmc/linux/drivers/gpu/drm/msm/adreno/ |
| H A D | a6xx.xml.h | 1123 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_MRB_START() argument
1125 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_ST… in A6XX_CP_ROQ_THRESHOLDS_1_MRB_START()
1129 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_VSD_START() argument
1131 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_ST… in A6XX_CP_ROQ_THRESHOLDS_1_VSD_START()
1135 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START() argument
1137 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_ST… in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START()
1141 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START() argument
1143 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_ST… in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START()
1149 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START() argument
1151 …return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_ST… in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START()
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| H A D | adreno_pm4.xml.h | 526 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF() argument
528 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; in CP_LOAD_STATE_0_DST_OFF()
532 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC() argument
534 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; in CP_LOAD_STATE_0_STATE_SRC()
538 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK() argument
540 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; in CP_LOAD_STATE_0_STATE_BLOCK()
544 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT() argument
546 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; in CP_LOAD_STATE_0_NUM_UNIT()
552 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE() argument
554 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; in CP_LOAD_STATE_1_STATE_TYPE()
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| H A D | a3xx.xml.h | 947 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES() argument
949 …return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_… in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES()
955 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ() argument
957 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
961 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT() argument
963 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT()
969 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) in A3XX_GRAS_CL_VPORT_XOFFSET() argument
971 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; in A3XX_GRAS_CL_VPORT_XOFFSET()
977 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) in A3XX_GRAS_CL_VPORT_XSCALE() argument
979 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; in A3XX_GRAS_CL_VPORT_XSCALE()
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| H A D | a4xx.xml.h | 845 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) in A4XX_CGC_HLSQ_EARLY_CYC() argument
847 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; in A4XX_CGC_HLSQ_EARLY_CYC()
902 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH() argument
904 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WID… in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
908 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT() argument
910 …return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HE… in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
924 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) in A4XX_RB_MODE_CONTROL_WIDTH() argument
926 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; in A4XX_RB_MODE_CONTROL_WIDTH()
930 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) in A4XX_RB_MODE_CONTROL_HEIGHT() argument
932 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; in A4XX_RB_MODE_CONTROL_HEIGHT()
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| H A D | a5xx.xml.h | 1043 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A5XX_CP_PROTECT_REG_BASE_ADDR() argument
1045 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK; in A5XX_CP_PROTECT_REG_BASE_ADDR()
1049 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A5XX_CP_PROTECT_REG_MASK_LEN() argument
1051 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; in A5XX_CP_PROTECT_REG_MASK_LEN()
1055 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_WRITE() argument
1057 return ((val) << A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK; in A5XX_CP_PROTECT_REG_TRAP_WRITE()
1061 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_READ() argument
1063 return ((val) << A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_READ__MASK; in A5XX_CP_PROTECT_REG_TRAP_READ()
1838 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val) in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB() argument
1840 …return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MA… in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB()
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| H A D | a2xx.xml.h | 1172 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR() argument
1174 …return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHA… in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR()
1178 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR() argument
1180 …return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHA… in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR()
1184 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR() argument
1186 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR()
1190 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR() argument
1192 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR()
1196 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR() argument
1198 …return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BE… in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR()
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| /openbmc/linux/drivers/net/wireless/realtek/rtw89/ |
| H A D | fw.h | 341 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_IDX() argument
343 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); in RTW89_SET_FWCMD_SEC_IDX()
346 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_OFFSET() argument
348 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); in RTW89_SET_FWCMD_SEC_OFFSET()
351 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_LEN() argument
353 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); in RTW89_SET_FWCMD_SEC_LEN()
356 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_TYPE() argument
358 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); in RTW89_SET_FWCMD_SEC_TYPE()
361 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_EXT_KEY() argument
363 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); in RTW89_SET_FWCMD_SEC_EXT_KEY()
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| /openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| H A D | types.h | 133 #define CONF_HAS(config, val) ((config) & (1 << (val))) argument
138 #define CONF_IS(config, val) ((config) == (1 << (val))) argument
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) argument
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) argument
141 #define CONF_LT(config, val) ((config) & ((1 << (val))-1)) argument
142 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1)) argument
146 #define NCONF_HAS(val) CONF_HAS(NCONF, val) argument
148 #define NCONF_IS(val) CONF_IS(NCONF, val) argument
149 #define NCONF_GE(val) CONF_GE(NCONF, val) argument
150 #define NCONF_GT(val) CONF_GT(NCONF, val) argument
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| /openbmc/qemu/target/hppa/ |
| H A D | gdbstub.c | 33 uint32_t val; in hppa_cpu_gdb_read_register() local
37 val = cpu_hppa_get_psw(env); in hppa_cpu_gdb_read_register()
40 val = env->gr[n]; in hppa_cpu_gdb_read_register()
43 val = env->cr[CR_SAR]; in hppa_cpu_gdb_read_register()
46 val = env->iaoq_f; in hppa_cpu_gdb_read_register()
49 val = env->iasq_f >> 32; in hppa_cpu_gdb_read_register()
52 val = env->iaoq_b; in hppa_cpu_gdb_read_register()
55 val = env->iasq_b >> 32; in hppa_cpu_gdb_read_register()
58 val = env->cr[CR_EIEM]; in hppa_cpu_gdb_read_register()
61 val = env->cr[CR_IIR]; in hppa_cpu_gdb_read_register()
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| /openbmc/linux/drivers/phy/ |
| H A D | phy-xgene.c | 555 u32 val; in sds_wr() local
565 val = readl(csr_base + indirect_cmd_reg); in sds_wr()
566 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_wr()
568 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_wr()
577 u32 val; in sds_rd() local
585 val = readl(csr_base + indirect_cmd_reg); in sds_rd()
586 } while (!(val & CFG_IND_CMD_DONE_MASK) && in sds_rd()
589 if (!(val & CFG_IND_CMD_DONE_MASK)) in sds_rd()
598 u32 val; in cmu_wr() local
607 SATA_ENET_SDS_IND_RDATA_REG, reg, &val); in cmu_wr()
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| /openbmc/u-boot/drivers/net/phy/ |
| H A D | mv88e61xx.c | 224 int val; in mv88e61xx_smi_wait() local
228 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG); in mv88e61xx_smi_wait()
229 if (val >= 0 && (val & SMI_BUSY) == 0) in mv88e61xx_smi_wait()
292 u16 val) in mv88e61xx_reg_write() argument
302 val); in mv88e61xx_reg_write()
312 SMI_DATA_REG, val); in mv88e61xx_reg_write()
332 int val; in mv88e61xx_phy_wait() local
336 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2, in mv88e61xx_phy_wait()
338 if (val >= 0 && (val & SMI_BUSY) == 0) in mv88e61xx_phy_wait()
403 int reg, u16 val) in mv88e61xx_phy_write() argument
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| /openbmc/linux/drivers/gpu/drm/i915/ |
| H A D | i915_fixed.h | 15 u32 val; member
18 #define FP_16_16_MAX ((uint_fixed_16_16_t){ .val = UINT_MAX })
20 static inline bool is_fixed16_zero(uint_fixed_16_16_t val) in is_fixed16_zero() argument
22 return val.val == 0; in is_fixed16_zero()
25 static inline uint_fixed_16_16_t u32_to_fixed16(u32 val) in u32_to_fixed16() argument
27 uint_fixed_16_16_t fp = { .val = val << 16 }; in u32_to_fixed16()
29 WARN_ON(val > U16_MAX); in u32_to_fixed16()
36 return DIV_ROUND_UP(fp.val, 1 << 16); in fixed16_to_u32_round_up()
41 return fp.val >> 16; in fixed16_to_u32()
47 uint_fixed_16_16_t min = { .val = min(min1.val, min2.val) }; in min_fixed16()
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| /openbmc/linux/arch/loongarch/include/asm/ |
| H A D | percpu.h | 41 unsigned long val, int size) \
48 "am"#asm_op".w" " %[ret], %[val], %[ptr] \n" \
50 : [val] "r" (val)); \
54 "am"#asm_op".d" " %[ret], %[val], %[ptr] \n" \
56 : [val] "r" (val)); \
63 return ret c_op val; \
108 static __always_inline void __percpu_write(void *ptr, unsigned long val, int size) in __percpu_write() argument
112 __asm__ __volatile__("stx.b %[val], $r21, %[ptr] \n" in __percpu_write()
114 : [val] "r" (val), [ptr] "r" (ptr) in __percpu_write()
118 __asm__ __volatile__("stx.h %[val], $r21, %[ptr] \n" in __percpu_write()
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| /openbmc/linux/drivers/accel/ivpu/ |
| H A D | ivpu_hw_37xx.c | 145 u32 val; in ivpu_pll_cmd_send() local
153 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0); in ivpu_pll_cmd_send()
154 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val); in ivpu_pll_cmd_send()
155 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val); in ivpu_pll_cmd_send()
156 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, val); in ivpu_pll_cmd_send()
158 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1); in ivpu_pll_cmd_send()
159 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val); in ivpu_pll_cmd_send()
160 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, PLL_DEFAULT_EPP_VALUE, val); in ivpu_pll_cmd_send()
161 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, val); in ivpu_pll_cmd_send()
163 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD2); in ivpu_pll_cmd_send()
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| H A D | ivpu_hw_40xx.c | 163 u32 val; in ivpu_pll_cmd_send() local
171 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0); in ivpu_pll_cmd_send()
172 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val); in ivpu_pll_cmd_send()
173 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val); in ivpu_pll_cmd_send()
174 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD0, val); in ivpu_pll_cmd_send()
176 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1); in ivpu_pll_cmd_send()
177 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val); in ivpu_pll_cmd_send()
178 val = REG_SET_FLD_NUM(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, EPP, epp, val); in ivpu_pll_cmd_send()
179 REGB_WR32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD1, val); in ivpu_pll_cmd_send()
181 val = REGB_RD32(VPU_40XX_BUTTRESS_WP_REQ_PAYLOAD2); in ivpu_pll_cmd_send()
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| /openbmc/linux/drivers/gpu/drm/msm/dsi/ |
| H A D | dsi.xml.h | 146 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) in DSI_6G_HW_VERSION_MAJOR() argument
148 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; in DSI_6G_HW_VERSION_MAJOR()
152 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) in DSI_6G_HW_VERSION_MINOR() argument
154 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; in DSI_6G_HW_VERSION_MINOR()
158 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) in DSI_6G_HW_VERSION_STEP() argument
160 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; in DSI_6G_HW_VERSION_STEP()
213 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) in DSI_VID_CFG0_VIRT_CHANNEL() argument
215 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; in DSI_VID_CFG0_VIRT_CHANNEL()
219 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) in DSI_VID_CFG0_DST_FORMAT() argument
221 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; in DSI_VID_CFG0_DST_FORMAT()
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| /openbmc/linux/drivers/net/ethernet/chelsio/cxgb4/ |
| H A D | cxgb4_tc_u32_parse.h | 41 int (*val)(struct ch_filter_specification *f, __be32 val, __be32 mask); member
46 __be32 val, __be32 mask) in cxgb4_fill_ipv4_tos() argument
48 f->val.tos = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_tos()
55 __be32 val, __be32 mask) in cxgb4_fill_ipv4_frag() argument
60 frag_val = (ntohl(val) >> 13) & 0x00000007; in cxgb4_fill_ipv4_frag()
64 f->val.frag = 1; in cxgb4_fill_ipv4_frag()
67 f->val.frag = 0; in cxgb4_fill_ipv4_frag()
77 __be32 val, __be32 mask) in cxgb4_fill_ipv4_proto() argument
79 f->val.proto = (ntohl(val) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_proto()
86 __be32 val, __be32 mask) in cxgb4_fill_ipv4_src_ip() argument
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| /openbmc/linux/tools/perf/util/ |
| H A D | expr.y | 38 double val;
73 /* During computing ids, does val represent a constant (non-BOTTOM) value? */
74 static bool is_const(double val)
76 return isfinite(val);
82 .val = BOTTOM,
100 result.val = NAN;
102 result.val = source_count
113 result.val = BOTTOM;
129 if (!compute_ids || (is_const(LHS.val) && is_const(RHS.val))) { \
132 if (isnan(LHS.val) || isnan(RHS.val)) { \
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| /openbmc/linux/arch/s390/include/asm/ |
| H A D | percpu.h | 27 #define arch_this_cpu_to_op_simple(pcp, val, op) \ argument
37 new__ = old__ op (val); \
44 #define this_cpu_add_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
45 #define this_cpu_add_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
46 #define this_cpu_add_return_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
47 #define this_cpu_add_return_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, +) argument
48 #define this_cpu_and_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &) argument
49 #define this_cpu_and_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, &) argument
50 #define this_cpu_or_1(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |) argument
51 #define this_cpu_or_2(pcp, val) arch_this_cpu_to_op_simple(pcp, val, |) argument
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| /openbmc/linux/include/sound/ |
| H A D | emu8000_reg.h | 108 #define EMU8000_CPF_WRITE(emu, chan, val) \ argument
109 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan)), (val))
110 #define EMU8000_PTRX_WRITE(emu, chan, val) \ argument
111 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan)), (val))
112 #define EMU8000_CVCF_WRITE(emu, chan, val) \ argument
113 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan)), (val))
114 #define EMU8000_VTFT_WRITE(emu, chan, val) \ argument
115 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan)), (val))
116 #define EMU8000_PSST_WRITE(emu, chan, val) \ argument
117 snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(6, (chan)), (val))
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