1d0fb9657SStefano Garzarella# See docs/devel/tracing.rst for syntax documentation. 2bfec08b5SMark Cave-Ayland 3*8d40a557SCédric Le Goater# aspeed_pcie.c 4*8d40a557SCédric Le Goateraspeed_pcie_phy_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 5*8d40a557SCédric Le Goateraspeed_pcie_phy_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 6*8d40a557SCédric Le Goateraspeed_pcie_cfg_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 7*8d40a557SCédric Le Goateraspeed_pcie_cfg_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 8*8d40a557SCédric Le Goateraspeed_pcie_cfg_rw(const char *dir, uint8_t bus, uint8_t devfn, uint64_t offset, uint64_t data) "%s bus:0x%x devfn:0x%x addr 0x%" PRIx64 " data 0x%" PRIx64 9*8d40a557SCédric Le Goateraspeed_pcie_cfg_msi_notify(uint64_t offset, uint64_t data) "@0x%" PRIx64 " IRQ 0x%" PRIx64 10*8d40a557SCédric Le Goater 11*8d40a557SCédric Le Goateraspeed_pcie_rc_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 12*8d40a557SCédric Le Goateraspeed_pcie_rc_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 13*8d40a557SCédric Le Goater 14300491f9SPhilippe Mathieu-Daudé# bonito.c 15300491f9SPhilippe Mathieu-Daudébonito_spciconf_small_access(uint64_t addr, unsigned size) "PCI config address is smaller then 32-bit, addr: 0x%"PRIx64", size: %u" 16300491f9SPhilippe Mathieu-Daudé 17500016e5SMarkus Armbruster# grackle.c 18b728fbbcSMark Cave-Aylandgrackle_set_irq(int irq_num, int level) "set_irq num %d level %d" 19b728fbbcSMark Cave-Ayland 20a7db759eSPhilippe Mathieu-Daudé# gt64120.c 21a7db759eSPhilippe Mathieu-Daudégt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64 22a7db759eSPhilippe Mathieu-Daudégt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64 23a7db759eSPhilippe Mathieu-Daudégt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64 24a7db759eSPhilippe Mathieu-Daudégt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64 25a7db759eSPhilippe Mathieu-Daudégt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 26a7db759eSPhilippe Mathieu-Daudé 27dcdf98a9SBALATON Zoltan# mv64361.c 28dcdf98a9SBALATON Zoltanmv64361_region_map(const char *name, uint64_t poffs, uint64_t size, uint64_t moffs) "Mapping %s 0x%"PRIx64"+0x%"PRIx64" @ 0x%"PRIx64 29dcdf98a9SBALATON Zoltanmv64361_region_enable(const char *op, int num) "Should %s region %d" 30dcdf98a9SBALATON Zoltanmv64361_reg_read(uint64_t addr, uint32_t val) "0x%"PRIx64" -> 0x%x" 31dcdf98a9SBALATON Zoltanmv64361_reg_write(uint64_t addr, uint64_t val) "0x%"PRIx64" <- 0x%"PRIx64 32dcdf98a9SBALATON Zoltan 33500016e5SMarkus Armbruster# sabre.c 34bfec08b5SMark Cave-Aylandsabre_set_request(int irq_num) "request irq %d" 35bfec08b5SMark Cave-Aylandsabre_clear_request(int irq_num) "clear request irq %d" 36bfec08b5SMark Cave-Aylandsabre_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 37bfec08b5SMark Cave-Aylandsabre_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 38bfec08b5SMark Cave-Aylandsabre_pci_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 39bfec08b5SMark Cave-Aylandsabre_pci_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 40bfec08b5SMark Cave-Aylandsabre_pci_set_irq(int irq_num, int level) "set irq_in %d level %d" 41bfec08b5SMark Cave-Aylandsabre_pci_set_obio_irq(int irq_num, int level) "set irq %d level %d" 420b0c5e90SMark Cave-Ayland 43500016e5SMarkus Armbruster# uninorth.c 440b0c5e90SMark Cave-Aylandunin_set_irq(int irq_num, int level) "setting INT %d = %d" 450b0c5e90SMark Cave-Aylandunin_get_config_reg(uint32_t reg, uint32_t addr, uint32_t retval) "converted config space accessor 0x%"PRIx32 "/0x%"PRIx32 " -> 0x%"PRIx32 460b0c5e90SMark Cave-Aylandunin_data_write(uint64_t addr, unsigned len, uint64_t val) "write addr 0x%"PRIx64 " len %d val 0x%"PRIx64 470b0c5e90SMark Cave-Aylandunin_data_read(uint64_t addr, unsigned len, uint64_t val) "read addr 0x%"PRIx64 " len %d val 0x%"PRIx64 480662946aSMark Cave-Aylandunin_write(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"PRIx64 490662946aSMark Cave-Aylandunin_read(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"PRIx64 502cfc9f1aSCédric Le Goater 5155abb29eSPhilippe Mathieu-Daudé# ppc4xx_pci.c 5255abb29eSPhilippe Mathieu-Daudéppc4xx_pci_map_irq(int32_t devfn, int irq_num, int slot) "devfn 0x%x irq %d -> %d" 5355abb29eSPhilippe Mathieu-Daudéppc4xx_pci_set_irq(int irq_num) "PCI irq %d" 5455abb29eSPhilippe Mathieu-Daudé 5522dc8a47SPhilippe Mathieu-Daudé# ppc440_pcix.c 5622dc8a47SPhilippe Mathieu-Daudéppc440_pcix_map_irq(int32_t devfn, int irq_num, int slot) "devfn 0x%x irq %d -> %d" 5722dc8a47SPhilippe Mathieu-Daudéppc440_pcix_set_irq(int irq_num) "PCI irq %d" 5822dc8a47SPhilippe Mathieu-Daudéppc440_pcix_update_pim(int idx, uint64_t size, uint64_t la) "Added window %d of size=0x%" PRIx64 " to CPU=0x%" PRIx64 5922dc8a47SPhilippe Mathieu-Daudéppc440_pcix_update_pom(int idx, uint32_t size, uint64_t la, uint64_t pcia) "Added window %d of size=0x%x from CPU=0x%" PRIx64 " to PCI=0x%" PRIx64 6022dc8a47SPhilippe Mathieu-Daudéppc440_pcix_reg_read(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32 6122dc8a47SPhilippe Mathieu-Daudéppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint32_t size) "addr 0x%" PRIx64 " = 0x%" PRIx32 " size 0x%" PRIx32 6222dc8a47SPhilippe Mathieu-Daudé 632cfc9f1aSCédric Le Goater# pnv_phb4.c 642cfc9f1aSCédric Le Goaterpnv_phb4_xive_notify(uint64_t notif_port, uint64_t data) "notif=@0x%"PRIx64" data=0x%"PRIx64 6534b0696bSCédric Le Goaterpnv_phb4_xive_notify_ic(uint64_t addr, uint64_t data) "addr=@0x%"PRIx64" data=0x%"PRIx64 6634b0696bSCédric Le Goaterpnv_phb4_xive_notify_abt(uint64_t notif_port, uint64_t data) "notif=@0x%"PRIx64" data=0x%"PRIx64 670db9350eSMark Cave-Ayland 680db9350eSMark Cave-Ayland# dino.c 690db9350eSMark Cave-Aylanddino_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d" 700db9350eSMark Cave-Aylanddino_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" 710db9350eSMark Cave-Aylanddino_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" 72e029bb00SHelge Deller 73e029bb00SHelge Deller# astro.c 74e029bb00SHelge Dellerastro_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d" 75e029bb00SHelge Dellerastro_chip_read(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64 76e029bb00SHelge Dellerastro_chip_write(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64 77e029bb00SHelge Dellerelroy_read(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64 78e029bb00SHelge Dellerelroy_write(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64 79e029bb00SHelge Dellerelroy_pci_config_data_read(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64 80e029bb00SHelge Dellerelroy_pci_config_data_write(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64 81e029bb00SHelge Delleriosapic_reg_write(uint64_t reg_select, int size, uint64_t val) "reg_select 0x%"PRIx64" size %d val 0x%"PRIx64 82e029bb00SHelge Delleriosapic_reg_read(uint64_t reg_select, int size, uint64_t val) "reg_select 0x%"PRIx64" size %d val 0x%"PRIx64 83