87 	u32 val;  in omap_pipe3_wait_lock()  local
92 		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);  in omap_pipe3_wait_lock()
93 		if (val & PLL_LOCK)  in omap_pipe3_wait_lock()
97 	if (!(val & PLL_LOCK)) {  in omap_pipe3_wait_lock()
107 	u32                     val;  in omap_pipe3_dpll_program()  local
116 	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);  in omap_pipe3_dpll_program()
117 	val &= ~PLL_REGN_MASK;  in omap_pipe3_dpll_program()
118 	val |= dpll_params->n << PLL_REGN_SHIFT;  in omap_pipe3_dpll_program()
119 	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);  in omap_pipe3_dpll_program()
121 	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);  in omap_pipe3_dpll_program()
122 	val &= ~PLL_SELFREQDCO_MASK;  in omap_pipe3_dpll_program()
123 	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;  in omap_pipe3_dpll_program()
124 	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);  in omap_pipe3_dpll_program()
126 	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);  in omap_pipe3_dpll_program()
127 	val &= ~PLL_REGM_MASK;  in omap_pipe3_dpll_program()
128 	val |= dpll_params->m << PLL_REGM_SHIFT;  in omap_pipe3_dpll_program()
129 	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);  in omap_pipe3_dpll_program()
131 	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);  in omap_pipe3_dpll_program()
132 	val &= ~PLL_REGM_F_MASK;  in omap_pipe3_dpll_program()
133 	val |= dpll_params->mf << PLL_REGM_F_SHIFT;  in omap_pipe3_dpll_program()
134 	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);  in omap_pipe3_dpll_program()
136 	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);  in omap_pipe3_dpll_program()
137 	val &= ~PLL_SD_MASK;  in omap_pipe3_dpll_program()
138 	val |= dpll_params->sd << PLL_SD_SHIFT;  in omap_pipe3_dpll_program()
139 	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);  in omap_pipe3_dpll_program()
148 	u32 val, rate;  in omap_control_phy_power()  local
150 	val = readl(phy->power_reg);  in omap_control_phy_power()
156 		val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |  in omap_control_phy_power()
158 		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<  in omap_control_phy_power()
160 		val |= rate <<  in omap_control_phy_power()
163 		val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;  in omap_control_phy_power()
164 		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<  in omap_control_phy_power()
168 	writel(val, phy->power_reg);  in omap_control_phy_power()
174 	u32 val;  in phy_pipe3_power_on()  local
177 	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);  in phy_pipe3_power_on()
178 	if (!(val & PLL_LOCK)) {  in phy_pipe3_power_on()
184 		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);  in phy_pipe3_power_on()
185 		if (val & PLL_IDLE) {  in phy_pipe3_power_on()
186 			val &= ~PLL_IDLE;  in phy_pipe3_power_on()
188 					  PLL_CONFIGURATION2, val);  in phy_pipe3_power_on()
203 	u32 val;  in phy_pipe3_power_off()  local
210 	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);  in phy_pipe3_power_off()
211 	val |= PLL_IDLE;  in phy_pipe3_power_off()
212 	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);  in phy_pipe3_power_off()
217 		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);  in phy_pipe3_power_off()
218 		if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))  in phy_pipe3_power_off()
222 	if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {  in phy_pipe3_power_off()
224 		       __func__, val);  in phy_pipe3_power_off()